[U-Boot] [PATCH 1/2] arm: zynq: Remove fclk-enable property for cse-nor target
Mini cse NOR configuration is running without PL that's why there is no reason to enable clock to PL.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/dts/zynq-cse-nor.dts | 1 - 1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index ba6f9a1a79e3..edc8f59f6cea 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -56,7 +56,6 @@ clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
Trivial DT style fixes.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/dts/zynq-cse-nand.dts | 3 +-- arch/arm/dts/zynq-cse-nor.dts | 1 - 2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts index 9b1dd19a85df..1e16d7fab97d 100644 --- a/arch/arm/dts/zynq-cse-nand.dts +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -38,7 +38,7 @@ #size-cells = <1>; ranges;
- slcr: slcr@f8000000 { + slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; @@ -72,7 +72,6 @@ }; }; }; - };
&dcc { diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index edc8f59f6cea..9710abadcf02 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -79,7 +79,6 @@ }; }; }; - };
&dcc {
participants (1)
-
Michal Simek