[PATCH RESEND 1/2] arm: dts: rockchip: rk3588, rk3588s: sync with Linux
Sync the devicetree with linux-next tag: next-20230831
Signed-off-by: FUKAUMI Naoki naoki@radxa.com --- arch/arm/dts/rk3588.dtsi | 215 +++++++++++++++++++ arch/arm/dts/rk3588s.dtsi | 367 +++++++++++++++++++++++++++++++++ include/dt-bindings/ata/ahci.h | 20 ++ 3 files changed, 602 insertions(+) create mode 100644 include/dt-bindings/ata/ahci.h
diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi index 8be75556af..5519c1430c 100644 --- a/arch/arm/dts/rk3588.dtsi +++ b/arch/arm/dts/rk3588.dtsi @@ -7,6 +7,16 @@ #include "rk3588-pinctrl.dtsi"
/ { + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -75,6 +85,159 @@ status = "disabled"; };
+ pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>; @@ -123,4 +286,56 @@ queue1 {}; }; }; + + sata1: sata@fe220000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index 7dbac9ae2e..5544f66c6f 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/rk3588-power.h> #include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/ata/ahci.h>
/ { compatible = "rockchip,rk3588"; @@ -397,6 +399,50 @@ }; };
+ usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>; @@ -407,6 +453,66 @@ reg = <0x0 0xfd5b0000 0x0 0x1000>; };
+ pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>; @@ -830,6 +936,57 @@ }; };
+ i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 0>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 2>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 23>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>; @@ -1070,6 +1227,108 @@ reg = <0x0 0xfdf82200 0x0 0x20>; };
+ pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>; @@ -1119,6 +1378,52 @@ }; };
+ sata0: sata@fe210000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>; @@ -1134,6 +1439,21 @@ status = "disabled"; };
+ sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power RK3588_PD_SDIO>; + status = "disabled"; + }; + sdhci: mmc@fe2e0000 { compatible = "rockchip,rk3588-dwcmshc"; reg = <0x0 0xfe2e0000 0x0 0x10000>; @@ -1145,6 +1465,9 @@ <&cru TMCLK_EMMC>; clock-names = "core", "bus", "axi", "block", "timer"; max-frequency = <200000000>; + pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, + <&emmc_cmd>, <&emmc_data_strobe>; + pinctrl-names = "default"; resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, <&cru SRST_T_EMMC>; @@ -1742,6 +2065,18 @@ status = "disabled"; };
+ saradc: adc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + i2c6: i2c@fec80000 { compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xfec80000 0x0 0x1000>; @@ -1862,6 +2197,38 @@ #dma-cells = <1>; };
+ combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + status = "disabled"; + }; + system_sram2: sram@ff001000 { compatible = "mmio-sram"; reg = <0x0 0xff001000 0x0 0xef000>; diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h new file mode 100644 index 0000000000..b3f3b7cf9a --- /dev/null +++ b/include/dt-bindings/ata/ahci.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * This header provides constants for most AHCI bindings. + */ + +#ifndef _DT_BINDINGS_ATA_AHCI_H +#define _DT_BINDINGS_ATA_AHCI_H + +/* Host Bus Adapter generic platform capabilities */ +#define HBA_SSS (1 << 27) +#define HBA_SMPS (1 << 28) + +/* Host Bus Adapter port-specific platform capabilities */ +#define HBA_PORT_HPCP (1 << 18) +#define HBA_PORT_MPSP (1 << 19) +#define HBA_PORT_CPD (1 << 20) +#define HBA_PORT_ESP (1 << 21) +#define HBA_PORT_FBSCP (1 << 22) + +#endif
this patch adds support for PCIe3 (M.2 M key) and enables NVMe.
=> pci BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1d87 0x3588 Bridge device 0x04 01.00.00 0x10ec 0x8125 Network controller 0x00 02.00.00 0x1d87 0x3588 Bridge device 0x04 03.00.00 0x1179 0x011a Mass storage controller 0x08 => nvme scan => nvme info Device 0: Vendor: 0x1179 Rev: AGHA4101 Prod: 79CA20WPKRYN Type: Hard Disk Capacity: 488386.3 MB = 476.9 GB (1000215216 x 512)
Signed-off-by: FUKAUMI Naoki naoki@radxa.com
this patch depends: - "rockchip: rk3568: Fix use of PCIe bifurcation" [1] [1] https://patchwork.ozlabs.org/project/uboot/list/?series=366997 --- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 33 +++++++++++++++++++++++++ configs/rock5b-rk3588_defconfig | 1 + 2 files changed, 34 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 1b2fcbb0bb..c790894170 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -27,6 +27,19 @@ regulator-max-microvolt = <12000000>; };
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_vcc3v3_en>; + }; + vcc5v0_usbdcin: vcc5v0-usbdcin { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usbdcin"; @@ -87,6 +100,18 @@ status = "okay"; };
+&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_rst>; + status = "okay"; +}; + &pinctrl { pcie { pcie_reset_h: pcie-reset-h { @@ -97,6 +122,14 @@ rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>, <3 RK_PD0 4 &pcfg_pull_none>; }; + + pcie3_rst: pcie3-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3_vcc3v3_en: pcie3-vcc3v3-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; };
usb { diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 3fa65cbf9b..50551c70f2 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -81,6 +81,7 @@ CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y CONFIG_RTL8169=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
Hi Naoki,
On 2023-09-01 06:58, FUKAUMI Naoki wrote:
Sync the devicetree with linux-next tag: next-20230831
With the soc-dt-6.6 tag now merged into torvalds/linux tree [1] we can probably call this a sync from v6.6-rc1.
However, this patch misses some things:
- It does not remove synced pcie and usb nodes from the related u-boot.dtsi files.
- It is only a partial sync from next-20230831, see following diff:
arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 1 - arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 66 +++ arch/arm/dts/rk3588-edgeble-neu6b.dtsi | 359 ++++++++++++++- arch/arm/dts/rk3588-evb1-v10.dts | 720 ++++++++++++++++++++++++++++++- arch/arm/dts/rk3588-rock-5b.dts | 448 ++++++++++++++++++- arch/arm/dts/rk3588s-rock-5a.dts | 665 +++++++++++++++++++++++++++- 6 files changed, 2244 insertions(+), 15 deletions(-)
- There is a similar patch [2] from Jagan Teki where a rebase was requested.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?i... [2] https://patchwork.ozlabs.org/project/uboot/patch/20230719081745.3546727-1-ja...
Regards, Jonas
Signed-off-by: FUKAUMI Naoki naoki@radxa.com
arch/arm/dts/rk3588.dtsi | 215 +++++++++++++++++++ arch/arm/dts/rk3588s.dtsi | 367 +++++++++++++++++++++++++++++++++ include/dt-bindings/ata/ahci.h | 20 ++ 3 files changed, 602 insertions(+) create mode 100644 include/dt-bindings/ata/ahci.h
[...]
Sync the device tree for RK3588 series with Linux 6.6-rc1.
Signed-off-by: FUKAUMI Naoki naoki@radxa.com --- .../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 1 - arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 1 - .../dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 6 - arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 66 ++ arch/arm/dts/rk3588-edgeble-neu6b.dtsi | 359 ++++++++- arch/arm/dts/rk3588-evb1-v10.dts | 720 +++++++++++++++++- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 113 +-- arch/arm/dts/rk3588-rock-5b.dts | 448 ++++++++++- arch/arm/dts/rk3588.dtsi | 215 ++++++ arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 12 - arch/arm/dts/rk3588s-rock-5a.dts | 665 +++++++++++++++- arch/arm/dts/rk3588s-u-boot.dtsi | 162 ---- arch/arm/dts/rk3588s.dtsi | 367 +++++++++ include/dt-bindings/ata/ahci.h | 20 + 14 files changed, 2866 insertions(+), 289 deletions(-) create mode 100644 include/dt-bindings/ata/ahci.h
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi index 373f369c65..dd0058262b 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi @@ -11,7 +11,6 @@ };
chosen { - stdout-path = &uart2; u-boot,spl-boot-order = &sdmmc; }; }; diff --git a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi index 38e1a1e25f..727580aaa1 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi @@ -25,7 +25,6 @@ no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi index cd7626b24b..a45b3f5e86 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi @@ -11,12 +11,6 @@ };
chosen { - stdout-path = &uart2; u-boot,spl-boot-order = &sdmmc; }; }; - -&sdmmc { - bus-width = <4>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts index e9d5a8bab5..9933765e40 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts @@ -21,7 +21,73 @@ }; };
+&combphy0_ps { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* FAN */ +&pwm2 { + pinctrl-0 = <&pwm2m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +/* RS232 */ +&uart6 { + pinctrl-0 = <&uart6m0_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* RS485 */ +&uart7 { + pinctrl-0 = <&uart7m2_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi index 1c5bcf1280..017559bba3 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi @@ -18,6 +18,42 @@ regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; };
&sdhci { @@ -25,8 +61,329 @@ no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; }; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts index b91af0204d..229a9111f5 100644 --- a/arch/arm/dts/rk3588-evb1-v10.dts +++ b/arch/arm/dts/rk3588-evb1-v10.dts @@ -38,6 +38,20 @@ regulator-max-microvolt = <12000000>; };
+ vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_usb>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -47,6 +61,62 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc12v_dcin>; }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; };
&gmac0 { @@ -106,6 +176,12 @@ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; };
&pwm2 { @@ -117,13 +193,655 @@ no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; };
+&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc5v0_sys>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_gpu_mem_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + regulator-name = "vdd_gpu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_npu_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vdd_vdenc_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd1_1v8_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_codec_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_codec_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_1v8_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd2l_0v9_ddr_s3: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd2l_0v9_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_0v75_hdmi_edp_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_hdmi_edp_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + pmic@1 { + compatible = "rockchip,rk806"; + reg = <0x01>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, + <&rk806_slave_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_slave_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_slave_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_cpu_big1_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd1v8_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_1v8_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_sd_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v8_cam_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_2v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_pll_s0: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_cam_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&sata0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 1b2fcbb0bb..03626e71ea 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -10,10 +10,6 @@ #include <dt-bindings/usb/pd.h>
/ { - aliases { - mmc1 = &sdmmc; - }; - chosen { u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; }; @@ -37,18 +33,6 @@ vin-supply = <&vcc12v_dcin>; };
- vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - vin-supply = <&vcc5v0_sys>; - }; - vcc5v0_usb: vcc5v0-usb { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usb"; @@ -99,12 +83,6 @@ }; };
- usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - usb-typec { usbc0_int: usbc0-int { rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; @@ -116,17 +94,10 @@ }; };
-&sdmmc { - bus-width = <4>; - status = "okay"; -}; - &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; };
&sfc { @@ -148,23 +119,6 @@ }; };
-&usb_host0_ehci { - companion = <&usb_host0_ohci>; - phys = <&u2phy2_host>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usb_host0_ohci { - phys = <&u2phy2_host>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usb2phy2_grf { - status = "okay"; -}; - &u2phy0 { status = "okay"; }; @@ -174,28 +128,15 @@ status = "okay"; };
-&u2phy2 { - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; - reset-names = "phy", "apb"; - clock-output-names = "usb480m_phy2"; - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; +&u2phy1 { status = "okay"; };
-&usb_host1_ehci { - companion = <&usb_host1_ohci>; - phys = <&u2phy3_host>; - phy-names = "usb2-phy"; +&u2phy1_otg { status = "okay"; };
-&usb_host1_ohci { - phys = <&u2phy3_host>; - phy-names = "usb2-phy"; +&usb2phy2_grf { status = "okay"; };
@@ -203,16 +144,12 @@ status = "okay"; };
-&u2phy3 { - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; - reset-names = "phy", "apb"; - clock-output-names = "usb480m_phy3"; - status = "okay"; +&usb_host0_ehci { + companion = <&usb_host0_ohci>; };
-&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; +&usb_host1_ehci { + companion = <&usb_host1_ohci>; };
&usbdp_phy0 { @@ -241,24 +178,6 @@ status = "okay"; };
-&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - &usbdp_phy1 { rockchip,dp-lane-mux = <2 3>; status = "okay"; @@ -268,16 +187,25 @@ status = "okay"; };
-&usbdrd3_1 { +&usbdrd3_0 { status = "okay"; };
-&u2phy1 { +&usbdrd3_1 { status = "okay"; };
-&u2phy1_otg { - status = "okay"; +&usbdrd_dwc3_0 { + usb-role-switch; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; };
&i2c4 { @@ -350,4 +278,3 @@ }; }; }; - diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts index 3e4aee8f70..8ab60968f2 100644 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -11,6 +11,7 @@
aliases { mmc0 = &sdhci; + mmc1 = &sdmmc; serial2 = &uart2; };
@@ -18,17 +19,9 @@ stdout-path = "serial2:1500000n8"; };
- fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 95 145 195 255>; - fan-supply = <&vcc5v0_sys>; - pwms = <&pwm1 0 50000 0>; - #cooling-cells = <2>; - }; - - sound { + analog-sound { compatible = "audio-graph-card"; - label = "Analog"; + label = "rk3588-es8316";
widgets = "Microphone", "Mic Jack", "Headphone", "Headphones"; @@ -43,6 +36,28 @@ pinctrl-0 = <&hp_detect>; };
+ fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -51,6 +66,16 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; };
&cpu_b0 { @@ -69,6 +94,22 @@ cpu-supply = <&vdd_cpu_big1_s0>; };
+&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -133,6 +174,8 @@ reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; #sound-dai-cells = <0>;
port { @@ -173,24 +216,407 @@ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; };
&pwm1 { status = "okay"; };
+&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; };
+&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + /* connected to USB hub, which is powered by vcc5v0_sys */ + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi index 8be75556af..5519c1430c 100644 --- a/arch/arm/dts/rk3588.dtsi +++ b/arch/arm/dts/rk3588.dtsi @@ -7,6 +7,16 @@ #include "rk3588-pinctrl.dtsi"
/ { + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -75,6 +85,159 @@ status = "disabled"; };
+ pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>; @@ -123,4 +286,56 @@ queue1 {}; }; }; + + sata1: sata@fe220000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi index 9bb0e4f89e..c47b0a7112 100644 --- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -10,25 +10,13 @@ #include <dt-bindings/usb/pd.h>
/ { - aliases { - mmc1 = &sdmmc; - }; - chosen { u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; }; };
-&sdmmc { - bus-width = <4>; - status = "okay"; -}; - &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; }; - diff --git a/arch/arm/dts/rk3588s-rock-5a.dts b/arch/arm/dts/rk3588s-rock-5a.dts index 901825514f..8347adcbd0 100644 --- a/arch/arm/dts/rk3588s-rock-5a.dts +++ b/arch/arm/dts/rk3588s-rock-5a.dts @@ -3,6 +3,7 @@ /dts-v1/;
#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> #include "rk3588s.dtsi"
@@ -12,12 +13,252 @@
aliases { mmc0 = &sdhci; + mmc1 = &sdmmc; serial2 = &uart2; };
+ analog-sound { + compatible = "audio-graph-card"; + label = "rk3588-es8316"; + + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais = <&i2s0_8ch_p0>; + }; + chosen { stdout-path = "serial2:1500000n8"; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&io_led>; + + io-led { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc_5v0>; + pwms = <&pwm3 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_5v0: vcc-5v0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + eeprom: eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; +}; + +&i2c7 { + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; };
&gmac1 { @@ -49,11 +290,62 @@ };
&pinctrl { + leds { + io_led: io-led { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + power { + vcc_5v0_en: vcc-5v0-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + rtl8211f { rtl8211f_rst: rtl8211f-rst { rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifibt { + wl_reset: wl-reset { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wl_dis: wl-dis { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>; + }; + + wl_wake_host: wl-wake-host { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_dis: bt-dis { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; };
&sdhci { @@ -61,13 +353,384 @@ no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; };
+&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wl_reset &wl_dis &wl_wake_host &bt_dis &bt_wake_host>; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 245bc8b27c..27b2d7eff8 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -53,57 +53,12 @@ }; };
- usb_host0_ehci: usb@fc800000 { - compatible = "generic-ehci"; - reg = <0x0 0xfc800000 0x0 0x40000>; - interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; - clock-names = "usbhost", "arbiter"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host0_ohci: usb@fc840000 { - compatible = "generic-ohci"; - reg = <0x0 0xfc840000 0x0 0x40000>; - interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; - clock-names = "usbhost", "arbiter"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ehci: usb@fc880000 { - compatible = "generic-ehci"; - reg = <0x0 0xfc880000 0x0 0x40000>; - interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; - clock-names = "usbhost", "arbiter"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ohci: usb@fc8c0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfc8c0000 0x0 0x40000>; - interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; - clock-names = "usbhost", "arbiter"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - pmu1_grf: syscon@fd58a000 { bootph-all; compatible = "rockchip,rk3588-pmu1-grf", "syscon"; reg = <0x0 0xfd58a000 0x0 0x2000>; };
- pipe_phy0_grf: syscon@fd5bc000 { - compatible = "rockchip,pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5bc000 0x0 0x100>; - }; - usb2phy0_grf: syscon@fd5d0000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; @@ -131,29 +86,6 @@ }; };
- usb2phy2_grf: syscon@fd5d8000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", - "simple-mfd"; - reg = <0x0 0xfd5d8000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy2: usb2-phy@8000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x8000 0x10>; - interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - status = "disabled"; - - u2phy2_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - vo0_grf: syscon@fd5a6000 { compatible = "rockchip,rk3588-vo-grf", "syscon"; reg = <0x0 0xfd5a6000 0x0 0x2000>; @@ -165,89 +97,11 @@ reg = <0x0 0xfd5ac000 0x0 0x4000>; };
- usb2phy3_grf: syscon@fd5dc000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", - "simple-mfd"; - reg = <0x0 0xfd5dc000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy3: usb2-phy@c000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0xc000 0x10>; - interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - status = "disabled"; - - u2phy3_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - usbdpphy0_grf: syscon@fd5c8000 { compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; reg = <0x0 0xfd5c8000 0x0 0x4000>; };
- pcie2x1l2: pcie@fe190000 { - compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x40 0x4f>; - clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, - <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, - <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, - <0 0 0 2 &pcie2x1l2_intc 1>, - <0 0 0 3 &pcie2x1l2_intc 2>, - <0 0 0 4 &pcie2x1l2_intc 3>; - linux,pci-domain = <4>; - num-ib-windows = <8>; - num-ob-windows = <8>; - num-viewport = <4>; - max-link-speed = <2>; - msi-map = <0x4000 &gic 0x4000 0x1000>; - num-lanes = <1>; - phys = <&combphy0_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, - <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; - reg = <0xa 0x41000000 0x0 0x00400000>, - <0x0 0xfe190000 0x0 0x00010000>, - <0x0 0xf4000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; - reset-names = "pcie", "periph"; - rockchip,pipe-grf = <&php_grf>; - status = "disabled"; - - pcie2x1l2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - sfc: spi@fe2b0000 { compatible = "rockchip,sfc"; reg = <0x0 0xfe2b0000 0x0 0x4000>; @@ -293,22 +147,6 @@ status = "disabled"; }; }; - - combphy0_ps: phy@fee00000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee00000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, - <&cru PCLK_PHP_ROOT>; - clock-names = "refclk", "apbclk", "phpclk"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; - reset-names = "combphy-apb", "combphy"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy0_grf>; - status = "disabled"; - }; };
&emmc_bus8 { diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index 7dbac9ae2e..5544f66c6f 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/rk3588-power.h> #include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/ata/ahci.h>
/ { compatible = "rockchip,rk3588"; @@ -397,6 +399,50 @@ }; };
+ usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>; @@ -407,6 +453,66 @@ reg = <0x0 0xfd5b0000 0x0 0x1000>; };
+ pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>; @@ -830,6 +936,57 @@ }; };
+ i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 0>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 2>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 23>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>; @@ -1070,6 +1227,108 @@ reg = <0x0 0xfdf82200 0x0 0x20>; };
+ pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>; @@ -1119,6 +1378,52 @@ }; };
+ sata0: sata@fe210000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>; @@ -1134,6 +1439,21 @@ status = "disabled"; };
+ sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power RK3588_PD_SDIO>; + status = "disabled"; + }; + sdhci: mmc@fe2e0000 { compatible = "rockchip,rk3588-dwcmshc"; reg = <0x0 0xfe2e0000 0x0 0x10000>; @@ -1145,6 +1465,9 @@ <&cru TMCLK_EMMC>; clock-names = "core", "bus", "axi", "block", "timer"; max-frequency = <200000000>; + pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, + <&emmc_cmd>, <&emmc_data_strobe>; + pinctrl-names = "default"; resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, <&cru SRST_T_EMMC>; @@ -1742,6 +2065,18 @@ status = "disabled"; };
+ saradc: adc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + i2c6: i2c@fec80000 { compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xfec80000 0x0 0x1000>; @@ -1862,6 +2197,38 @@ #dma-cells = <1>; };
+ combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + status = "disabled"; + }; + system_sram2: sram@ff001000 { compatible = "mmio-sram"; reg = <0x0 0xff001000 0x0 0xef000>; diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h new file mode 100644 index 0000000000..b3f3b7cf9a --- /dev/null +++ b/include/dt-bindings/ata/ahci.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * This header provides constants for most AHCI bindings. + */ + +#ifndef _DT_BINDINGS_ATA_AHCI_H +#define _DT_BINDINGS_ATA_AHCI_H + +/* Host Bus Adapter generic platform capabilities */ +#define HBA_SSS (1 << 27) +#define HBA_SMPS (1 << 28) + +/* Host Bus Adapter port-specific platform capabilities */ +#define HBA_PORT_HPCP (1 << 18) +#define HBA_PORT_MPSP (1 << 19) +#define HBA_PORT_CPD (1 << 20) +#define HBA_PORT_ESP (1 << 21) +#define HBA_PORT_FBSCP (1 << 22) + +#endif
this patch adds support for PCIe3 (M.2 M key) and enables NVMe.
=> pci BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1d87 0x3588 Bridge device 0x04 01.00.00 0x10ec 0x8125 Network controller 0x00 02.00.00 0x1d87 0x3588 Bridge device 0x04 03.00.00 0x1179 0x011a Mass storage controller 0x08 => nvme scan => nvme info Device 0: Vendor: 0x1179 Rev: AGHA4101 Prod: 79CA20WPKRYN Type: Hard Disk Capacity: 488386.3 MB = 476.9 GB (1000215216 x 512)
Signed-off-by: FUKAUMI Naoki naoki@radxa.com
this patch depends: - "rockchip: rk3568: Fix use of PCIe bifurcation" [1] [1] https://patchwork.ozlabs.org/project/uboot/list/?series=366997 --- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 33 +++++++++++++++++++++++++ configs/rock5b-rk3588_defconfig | 1 + 2 files changed, 34 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 03626e71ea..96cc84e5aa 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -23,6 +23,19 @@ regulator-max-microvolt = <12000000>; };
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_vcc3v3_en>; + }; + vcc5v0_usbdcin: vcc5v0-usbdcin { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usbdcin"; @@ -71,6 +84,18 @@ status = "okay"; };
+&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_rst>; + status = "okay"; +}; + &pinctrl { pcie { pcie_reset_h: pcie-reset-h { @@ -81,6 +106,14 @@ rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>, <3 RK_PD0 4 &pcfg_pull_none>; }; + + pcie3_rst: pcie3-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3_vcc3v3_en: pcie3-vcc3v3-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; };
usb-typec { diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 3fa65cbf9b..50551c70f2 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -81,6 +81,7 @@ CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y CONFIG_RTL8169=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
On 2023/9/5 19:47, FUKAUMI Naoki wrote:
this patch adds support for PCIe3 (M.2 M key) and enables NVMe.
=> pci BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1d87 0x3588 Bridge device 0x04 01.00.00 0x10ec 0x8125 Network controller 0x00 02.00.00 0x1d87 0x3588 Bridge device 0x04 03.00.00 0x1179 0x011a Mass storage controller 0x08 => nvme scan => nvme info Device 0: Vendor: 0x1179 Rev: AGHA4101 Prod: 79CA20WPKRYN Type: Hard Disk Capacity: 488386.3 MB = 476.9 GB (1000215216 x 512)
Signed-off-by: FUKAUMI Naoki naoki@radxa.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
this patch depends:
- "rockchip: rk3568: Fix use of PCIe bifurcation" [1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=366997
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 33 +++++++++++++++++++++++++ configs/rock5b-rk3588_defconfig | 1 + 2 files changed, 34 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 03626e71ea..96cc84e5aa 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -23,6 +23,19 @@ regulator-max-microvolt = <12000000>; };
- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
compatible = "regulator-fixed";regulator-name = "vcc3v3_pcie30";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;enable-active-high;gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;startup-delay-us = <5000>;vin-supply = <&vcc5v0_sys>;pinctrl-names = "default";pinctrl-0 = <&pcie3_vcc3v3_en>;- };
- vcc5v0_usbdcin: vcc5v0-usbdcin { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usbdcin";
@@ -71,6 +84,18 @@ status = "okay"; };
+&pcie30phy {
- status = "okay";
+};
+&pcie3x4 {
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie30>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie3_rst>;
- status = "okay";
+};
- &pinctrl { pcie { pcie_reset_h: pcie-reset-h {
@@ -81,6 +106,14 @@ rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>, <3 RK_PD0 4 &pcfg_pull_none>; };
pcie3_rst: pcie3-rst {rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;};pcie3_vcc3v3_en: pcie3-vcc3v3-en {rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;};};
usb-typec {
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 3fa65cbf9b..50551c70f2 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -81,6 +81,7 @@ CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y CONFIG_RTL8169=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
On 2023/9/5 19:47, FUKAUMI Naoki wrote:
Sync the device tree for RK3588 series with Linux 6.6-rc1.
Signed-off-by: FUKAUMI Naoki naoki@radxa.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
.../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 1 - arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 1 - .../dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 6 - arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 66 ++ arch/arm/dts/rk3588-edgeble-neu6b.dtsi | 359 ++++++++- arch/arm/dts/rk3588-evb1-v10.dts | 720 +++++++++++++++++- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 113 +-- arch/arm/dts/rk3588-rock-5b.dts | 448 ++++++++++- arch/arm/dts/rk3588.dtsi | 215 ++++++ arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 12 - arch/arm/dts/rk3588s-rock-5a.dts | 665 +++++++++++++++- arch/arm/dts/rk3588s-u-boot.dtsi | 162 ---- arch/arm/dts/rk3588s.dtsi | 367 +++++++++ include/dt-bindings/ata/ahci.h | 20 + 14 files changed, 2866 insertions(+), 289 deletions(-) create mode 100644 include/dt-bindings/ata/ahci.h
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi index 373f369c65..dd0058262b 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi @@ -11,7 +11,6 @@ };
chosen {
stdout-path = &uart2;diff --git a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi index 38e1a1e25f..727580aaa1 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi @@ -25,7 +25,6 @@ no-sdio; no-sd; non-removable;
- max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay";
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi index cd7626b24b..a45b3f5e86 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi @@ -11,12 +11,6 @@ };
chosen {
stdout-path = &uart2;-&sdmmc {
- bus-width = <4>;
- status = "okay";
-}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts index e9d5a8bab5..9933765e40 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts @@ -21,7 +21,73 @@ }; };
+&combphy0_ps {
- status = "okay";
+};
+&i2c6 {
- status = "okay";
- hym8563: rtc@51 {
compatible = "haoyu,hym8563";reg = <0x51>;interrupt-parent = <&gpio0>;interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;#clock-cells = <0>;clock-output-names = "hym8563";pinctrl-names = "default";pinctrl-0 = <&hym8563_int>;wakeup-source;- };
+};
+&pinctrl {
- hym8563 {
hym8563_int: hym8563-int {rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+/* FAN */ +&pwm2 {
- pinctrl-0 = <&pwm2m1_pins>;
- pinctrl-names = "default";
- status = "okay";
+};
+&sata0 {
- status = "okay";
+};
+&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- no-sdio;
- no-mmc;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
+};
- &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; };
+/* RS232 */ +&uart6 {
- pinctrl-0 = <&uart6m0_xfer>;
- pinctrl-names = "default";
- status = "okay";
+};
+/* RS485 */ +&uart7 {
- pinctrl-0 = <&uart7m2_xfer>;
- pinctrl-names = "default";
- status = "okay";
+}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi index 1c5bcf1280..017559bba3 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi @@ -18,6 +18,42 @@ regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; };
- vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";regulator-name = "vcc_1v1_nldo_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1100000>;vin-supply = <&vcc5v0_sys>;- };
+};
+&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>; };
&sdhci {
@@ -25,8 +61,329 @@ no-sdio; no-sd; non-removable;
- max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; };
+&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- pmic@0 {
compatible = "rockchip,rk806";spi-max-frequency = <1000000>;reg = <0x0>;interrupt-parent = <&gpio0>;interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;pinctrl-names = "default";pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,<&rk806_dvs2_null>, <&rk806_dvs3_null>;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc5-supply = <&vcc5v0_sys>;vcc6-supply = <&vcc5v0_sys>;vcc7-supply = <&vcc5v0_sys>;vcc8-supply = <&vcc5v0_sys>;vcc9-supply = <&vcc5v0_sys>;vcc10-supply = <&vcc5v0_sys>;vcc11-supply = <&vcc_2v0_pldo_s3>;vcc12-supply = <&vcc5v0_sys>;vcc13-supply = <&vcc_1v1_nldo_s3>;vcc14-supply = <&vcc_1v1_nldo_s3>;vcca-supply = <&vcc5v0_sys>;gpio-controller;#gpio-cells = <2>;rk806_dvs1_null: dvs1-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs2_null: dvs2-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs3_null: dvs3-null-pins {pins = "gpio_pwrctrl3";function = "pin_fun0";};regulators {vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {regulator-name = "vdd_gpu_s0";regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-enable-ramp-delay = <400>;regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {regulator-name = "vdd_cpu_lit_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};vdd_log_s0: dcdc-reg3 {regulator-name = "vdd_log_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {regulator-name = "vdd_vdenc_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-init-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};vdd_ddr_s0: dcdc-reg5 {regulator-name = "vdd_ddr_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <900000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <850000>;};};vdd2_ddr_s3: dcdc-reg6 {regulator-name = "vdd2_ddr_s3";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;};};vcc_2v0_pldo_s3: dcdc-reg7 {regulator-name = "vdd_2v0_pldo_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <2000000>;regulator-max-microvolt = <2000000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <2000000>;};};vcc_3v3_s3: dcdc-reg8 {regulator-name = "vcc_3v3_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vddq_ddr_s0: dcdc-reg9 {regulator-name = "vddq_ddr_s0";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s3: dcdc-reg10 {regulator-name = "vcc_1v8_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};avcc_1v8_s0: pldo-reg1 {regulator-name = "avcc_1v8_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s0: pldo-reg2 {regulator-name = "vcc_1v8_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <1800000>;};};avdd_1v2_s0: pldo-reg3 {regulator-name = "avdd_1v2_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_s0: pldo-reg4 {regulator-name = "vcc_3v3_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};vccio_sd_s0: pldo-reg5 {regulator-name = "vccio_sd_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};pldo6_s3: pldo-reg6 {regulator-name = "pldo6_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_0v75_s3: nldo-reg1 {regulator-name = "vdd_0v75_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_ddr_pll_s0: nldo-reg2 {regulator-name = "vdd_ddr_pll_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <850000>;};};avdd_0v75_s0: nldo-reg3 {regulator-name = "avdd_0v75_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-state-mem {regulator-off-in-suspend;};};vdd_0v85_s0: nldo-reg4 {regulator-name = "vdd_0v85_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-state-mem {regulator-off-in-suspend;};};vdd_0v75_s0: nldo-reg5 {regulator-name = "vdd_0v75_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-state-mem {regulator-off-in-suspend;};};};- };
+}; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts index b91af0204d..229a9111f5 100644 --- a/arch/arm/dts/rk3588-evb1-v10.dts +++ b/arch/arm/dts/rk3588-evb1-v10.dts @@ -38,6 +38,20 @@ regulator-max-microvolt = <12000000>; };
- vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_host";regulator-boot-on;regulator-always-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_host_en>;vin-supply = <&vcc5v0_usb>;- };
- vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys";
@@ -47,6 +61,62 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc12v_dcin>; };
- vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usbdcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc5v0_usbdcin>;- };
+};
+&combphy0_ps {
- status = "okay";
+};
+&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
+};
+&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
+};
+&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
+};
+&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
+};
+&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>; };
&gmac0 {
@@ -106,6 +176,12 @@ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; }; };
usb {
vcc5v0_host_en: vcc5v0-host-en {rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};}; };
&pwm2 {
@@ -117,13 +193,655 @@ no-sdio; no-sd; non-removable;
- max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; };
+&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <2>;
- pmic@0 {
compatible = "rockchip,rk806";reg = <0x0>;#gpio-cells = <2>;gpio-controller;interrupt-parent = <&gpio0>;interrupts = <7 IRQ_TYPE_LEVEL_LOW>;pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,<&rk806_dvs2_null>, <&rk806_dvs3_null>;pinctrl-names = "default";spi-max-frequency = <1000000>;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc5-supply = <&vcc5v0_sys>;vcc6-supply = <&vcc5v0_sys>;vcc7-supply = <&vcc5v0_sys>;vcc8-supply = <&vcc5v0_sys>;vcc9-supply = <&vcc5v0_sys>;vcc10-supply = <&vcc5v0_sys>;vcc11-supply = <&vcc_2v0_pldo_s3>;vcc12-supply = <&vcc5v0_sys>;vcc13-supply = <&vcc5v0_sys>;vcc14-supply = <&vcc_1v1_nldo_s3>;vcca-supply = <&vcc5v0_sys>;rk806_dvs1_null: dvs1-null-pins {pins = "gpio_pwrctrl1";function = "pin_fun0";};rk806_dvs2_null: dvs2-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs3_null: dvs3-null-pins {pins = "gpio_pwrctrl3";function = "pin_fun0";};regulators {vdd_gpu_s0: dcdc-reg1 {regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_gpu_s0";regulator-enable-ramp-delay = <400>;regulator-state-mem {regulator-off-in-suspend;};};vdd_npu_s0: dcdc-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_npu_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_log_s0: dcdc-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_log_s0";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_vdenc_s0: dcdc-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_vdenc_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_gpu_mem_s0: dcdc-reg5 {regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-enable-ramp-delay = <400>;regulator-name = "vdd_gpu_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_npu_mem_s0: dcdc-reg6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_npu_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_2v0_pldo_s3: dcdc-reg7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <2000000>;regulator-max-microvolt = <2000000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_2v0_pldo_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <2000000>;};};vdd_vdenc_mem_s0: dcdc-reg8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_vdenc_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd2_ddr_s3: dcdc-reg9 {regulator-always-on;regulator-boot-on;regulator-name = "vdd2_ddr_s3";regulator-state-mem {regulator-on-in-suspend;};};vcc_1v1_nldo_s3: dcdc-reg10 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1100000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_1v1_nldo_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1100000>;};};avcc_1v8_s0: pldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "avcc_1v8_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd1_1v8_ddr_s3: pldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "vdd1_1v8_ddr_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};avcc_1v8_codec_s0: pldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "avcc_1v8_codec_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_s3: pldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_3v3_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vccio_sd_s0: pldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vccio_sd_s0";regulator-state-mem {regulator-off-in-suspend;};};vccio_1v8_s3: pldo-reg6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "vccio_1v8_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_0v75_s3: nldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_0v75_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd2l_0v9_ddr_s3: nldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <900000>;regulator-name = "vdd2l_0v9_ddr_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vdd_0v75_hdmi_edp_s0: nldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-name = "vdd_0v75_hdmi_edp_s0";regulator-state-mem {regulator-off-in-suspend;};};avdd_0v75_s0: nldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-name = "avdd_0v75_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_0v85_s0: nldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-name = "vdd_0v85_s0";regulator-state-mem {regulator-off-in-suspend;};};};- };
- pmic@1 {
compatible = "rockchip,rk806";reg = <0x01>;#gpio-cells = <2>;gpio-controller;interrupt-parent = <&gpio0>;interrupts = <7 IRQ_TYPE_LEVEL_LOW>;pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,<&rk806_slave_dvs3_null>;pinctrl-names = "default";spi-max-frequency = <1000000>;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc5-supply = <&vcc5v0_sys>;vcc6-supply = <&vcc5v0_sys>;vcc7-supply = <&vcc5v0_sys>;vcc8-supply = <&vcc5v0_sys>;vcc9-supply = <&vcc5v0_sys>;vcc10-supply = <&vcc5v0_sys>;vcc11-supply = <&vcc_2v0_pldo_s3>;vcc12-supply = <&vcc5v0_sys>;vcc13-supply = <&vcc_1v1_nldo_s3>;vcc14-supply = <&vcc_2v0_pldo_s3>;vcca-supply = <&vcc5v0_sys>;rk806_slave_dvs1_null: dvs1-null-pins {pins = "gpio_pwrctrl1";function = "pin_fun0";};rk806_slave_dvs2_null: dvs2-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_slave_dvs3_null: dvs3-null-pins {pins = "gpio_pwrctrl3";function = "pin_fun0";};regulators {vdd_cpu_big1_s0: dcdc-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_big1_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_big0_s0: dcdc-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_big0_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_lit_s0: dcdc-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_lit_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_s0: dcdc-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_3v3_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_big1_mem_s0: dcdc-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_big1_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_big0_mem_s0: dcdc-reg6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_big0_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s0: dcdc-reg7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_1v8_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_lit_mem_s0: dcdc-reg8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_lit_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vddq_ddr_s0: dcdc-reg9 {regulator-always-on;regulator-boot-on;regulator-name = "vddq_ddr_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_ddr_s0: dcdc-reg10 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <900000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_ddr_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_cam_s0: pldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_1v8_cam_s0";regulator-state-mem {regulator-off-in-suspend;};};avdd1v8_ddr_pll_s0: pldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "avdd1v8_ddr_pll_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_1v8_pll_s0: pldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_1v8_pll_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_sd_s0: pldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_3v3_sd_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_2v8_cam_s0: pldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_2v8_cam_s0";regulator-state-mem {regulator-off-in-suspend;};};pldo6_s3: pldo-reg6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "pldo6_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_0v75_pll_s0: nldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_0v75_pll_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_ddr_pll_s0: nldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-name = "vdd_ddr_pll_s0";regulator-state-mem {regulator-off-in-suspend;};};avdd_0v85_s0: nldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-ramp-delay = <12500>;regulator-name = "avdd_0v85_s0";regulator-state-mem {regulator-off-in-suspend;};};avdd_1v2_cam_s0: nldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-ramp-delay = <12500>;regulator-name = "avdd_1v2_cam_s0";regulator-state-mem {regulator-off-in-suspend;};};avdd_1v2_s0: nldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-ramp-delay = <12500>;regulator-name = "avdd_1v2_s0";regulator-state-mem {regulator-off-in-suspend;};};};- };
+};
+&sata0 {
- status = "okay";
+};
+&u2phy2 {
- status = "okay";
+};
+&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
+&u2phy3 {
- status = "okay";
+};
+&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
- &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; };
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&usb_host1_ehci {
- status = "okay";
+};
+&usb_host1_ohci {
- status = "okay";
+}; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 1b2fcbb0bb..03626e71ea 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -10,10 +10,6 @@ #include <dt-bindings/usb/pd.h>
/ {
- aliases {
mmc1 = &sdmmc;- };
- chosen { u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; };
@@ -37,18 +33,6 @@ vin-supply = <&vcc12v_dcin>; };
- vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_host";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_host_en>;vin-supply = <&vcc5v0_sys>;- };
- vcc5v0_usb: vcc5v0-usb { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usb";
@@ -99,12 +83,6 @@ }; };
- usb {
vcc5v0_host_en: vcc5v0-host-en {rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- usb-typec { usbc0_int: usbc0-int { rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -116,17 +94,10 @@ }; };
-&sdmmc {
- bus-width = <4>;
- status = "okay";
-};
&sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; };
&sfc {
@@ -148,23 +119,6 @@ }; };
-&usb_host0_ehci {
- companion = <&usb_host0_ohci>;
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-&usb_host0_ohci {
- phys = <&u2phy2_host>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-&usb2phy2_grf {
- status = "okay";
-};
- &u2phy0 { status = "okay"; };
@@ -174,28 +128,15 @@ status = "okay"; };
-&u2phy2 {
- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
- reset-names = "phy", "apb";
- clock-output-names = "usb480m_phy2";
- status = "okay";
-};
-&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
+&u2phy1 { status = "okay"; };
-&usb_host1_ehci {
- companion = <&usb_host1_ohci>;
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
+&u2phy1_otg { status = "okay"; };
-&usb_host1_ohci {
- phys = <&u2phy3_host>;
- phy-names = "usb2-phy";
+&usb2phy2_grf { status = "okay"; };
@@ -203,16 +144,12 @@ status = "okay"; };
-&u2phy3 {
- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
- reset-names = "phy", "apb";
- clock-output-names = "usb480m_phy3";
- status = "okay";
+&usb_host0_ehci {
- companion = <&usb_host0_ohci>; };
-&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+&usb_host1_ehci {
companion = <&usb_host1_ohci>; };
&usbdp_phy0 {
@@ -241,24 +178,6 @@ status = "okay"; };
-&usbdrd3_0 {
- status = "okay";
-};
-&usbdrd_dwc3_0 {
- dr_mode = "otg";
- usb-role-switch;
- port {
#address-cells = <1>;#size-cells = <0>;dwc3_0_role_switch: endpoint@0 {reg = <0>;remote-endpoint = <&usbc0_role_sw>;};- };
-};
- &usbdp_phy1 { rockchip,dp-lane-mux = <2 3>; status = "okay";
@@ -268,16 +187,25 @@ status = "okay"; };
-&usbdrd3_1 { +&usbdrd3_0 { status = "okay"; };
-&u2phy1 { +&usbdrd3_1 { status = "okay"; };
-&u2phy1_otg {
- status = "okay";
+&usbdrd_dwc3_0 {
usb-role-switch;
port {
#address-cells = <1>;#size-cells = <0>;dwc3_0_role_switch: endpoint@0 {reg = <0>;remote-endpoint = <&usbc0_role_sw>;};}; };
&i2c4 {
@@ -350,4 +278,3 @@ }; }; };
diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts index 3e4aee8f70..8ab60968f2 100644 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -11,6 +11,7 @@
aliases { mmc0 = &sdhci;
mmc1 = &sdmmc;@@ -18,17 +19,9 @@ stdout-path = "serial2:1500000n8"; };
- fan: pwm-fan {
compatible = "pwm-fan";cooling-levels = <0 95 145 195 255>;fan-supply = <&vcc5v0_sys>;pwms = <&pwm1 0 50000 0>;#cooling-cells = <2>;- };
- sound {
- analog-sound { compatible = "audio-graph-card";
label = "Analog";
label = "rk3588-es8316";widgets = "Microphone", "Mic Jack", "Headphone", "Headphones";
@@ -43,6 +36,28 @@ pinctrl-0 = <&hp_detect>; };
- fan: pwm-fan {
compatible = "pwm-fan";cooling-levels = <0 95 145 195 255>;fan-supply = <&vcc5v0_sys>;pwms = <&pwm1 0 50000 0>;#cooling-cells = <2>;- };
- vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_host";regulator-boot-on;regulator-always-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_host_en>;vin-supply = <&vcc5v0_sys>;- };
- vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys";
@@ -51,6 +66,16 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; };
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";regulator-name = "vcc_1v1_nldo_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1100000>;vin-supply = <&vcc5v0_sys>;}; };
&cpu_b0 {
@@ -69,6 +94,22 @@ cpu-supply = <&vdd_cpu_big1_s0>; };
+&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
- &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>;
@@ -133,6 +174,8 @@ reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; clock-names = "mclk";
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;assigned-clock-rates = <12288000>;#sound-dai-cells = <0>;
port {
@@ -173,24 +216,407 @@ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; };
usb {
vcc5v0_host_en: vcc5v0-host-en {rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};}; };
&pwm1 { status = "okay"; };
+&saradc {
- vref-supply = <&avcc_1v8_s0>;
- status = "okay";
+};
- &sdhci { bus-width = <8>; no-sdio; no-sd; non-removable;
- max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; };
+&sdmmc {
- max-frequency = <200000000>;
- no-sdio;
- no-mmc;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
+};
+&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- num-cs = <1>;
- pmic@0 {
compatible = "rockchip,rk806";spi-max-frequency = <1000000>;reg = <0x0>;interrupt-parent = <&gpio0>;interrupts = <7 IRQ_TYPE_LEVEL_LOW>;pinctrl-names = "default";pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,<&rk806_dvs2_null>, <&rk806_dvs3_null>;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc5-supply = <&vcc5v0_sys>;vcc6-supply = <&vcc5v0_sys>;vcc7-supply = <&vcc5v0_sys>;vcc8-supply = <&vcc5v0_sys>;vcc9-supply = <&vcc5v0_sys>;vcc10-supply = <&vcc5v0_sys>;vcc11-supply = <&vcc_2v0_pldo_s3>;vcc12-supply = <&vcc5v0_sys>;vcc13-supply = <&vcc_1v1_nldo_s3>;vcc14-supply = <&vcc_1v1_nldo_s3>;vcca-supply = <&vcc5v0_sys>;gpio-controller;#gpio-cells = <2>;rk806_dvs1_null: dvs1-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs2_null: dvs2-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs3_null: dvs3-null-pins {pins = "gpio_pwrctrl3";function = "pin_fun0";};regulators {vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_gpu_s0";regulator-enable-ramp-delay = <400>;regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_lit_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_log_s0: dcdc-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_log_s0";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_vdenc_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_ddr_s0: dcdc-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <900000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_ddr_s0";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <850000>;};};vdd2_ddr_s3: dcdc-reg6 {regulator-always-on;regulator-boot-on;regulator-name = "vdd2_ddr_s3";regulator-state-mem {regulator-on-in-suspend;};};vcc_2v0_pldo_s3: dcdc-reg7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <2000000>;regulator-max-microvolt = <2000000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_2v0_pldo_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <2000000>;};};vcc_3v3_s3: dcdc-reg8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc_3v3_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vddq_ddr_s0: dcdc-reg9 {regulator-always-on;regulator-boot-on;regulator-name = "vddq_ddr_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s3: dcdc-reg10 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc_1v8_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};avcc_1v8_s0: pldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "avcc_1v8_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s0: pldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc_1v8_s0";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <1800000>;};};avdd_1v2_s0: pldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-name = "avdd_1v2_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_s0: pldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_3v3_s0";regulator-state-mem {regulator-off-in-suspend;};};vccio_sd_s0: pldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vccio_sd_s0";regulator-state-mem {regulator-off-in-suspend;};};pldo6_s3: pldo-reg6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "pldo6_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_0v75_s3: nldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-name = "vdd_0v75_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_ddr_pll_s0: nldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-name = "vdd_ddr_pll_s0";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <850000>;};};avdd_0v75_s0: nldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-name = "avdd_0v75_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_0v85_s0: nldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-name = "vdd_0v85_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_0v75_s0: nldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-name = "vdd_0v75_s0";regulator-state-mem {regulator-off-in-suspend;};};};- };
+};
- &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; };
+&u2phy2 {
- status = "okay";
+};
+&u2phy2_host {
- /* connected to USB hub, which is powered by vcc5v0_sys */
- phy-supply = <&vcc5v0_sys>;
- status = "okay";
+};
+&u2phy3 {
- status = "okay";
+};
+&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&usb_host1_ehci {
- status = "okay";
+};
+&usb_host1_ohci {
- status = "okay";
+}; diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi index 8be75556af..5519c1430c 100644 --- a/arch/arm/dts/rk3588.dtsi +++ b/arch/arm/dts/rk3588.dtsi @@ -7,6 +7,16 @@ #include "rk3588-pinctrl.dtsi"
/ {
- pcie30_phy_grf: syscon@fd5b8000 {
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";reg = <0x0 0xfd5b8000 0x0 0x10000>;- };
- pipe_phy1_grf: syscon@fd5c0000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";reg = <0x0 0xfd5c0000 0x0 0x100>;- };
- i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -75,6 +85,159 @@ status = "disabled"; };
- pcie3x4: pcie@fe150000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";#address-cells = <3>;#size-cells = <2>;bus-range = <0x00 0x0f>;clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;clock-names = "aclk_mst", "aclk_slv","aclk_dbi", "pclk","aux", "pipe";device_type = "pci";interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;interrupt-names = "sys", "pmc", "msg", "legacy", "err";#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 7>;interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,<0 0 0 2 &pcie3x4_intc 1>,<0 0 0 3 &pcie3x4_intc 2>,<0 0 0 4 &pcie3x4_intc 3>;linux,pci-domain = <0>;max-link-speed = <3>;msi-map = <0x0000 &its1 0x0000 0x1000>;num-lanes = <4>;phys = <&pcie30phy>;phy-names = "pcie-phy";power-domains = <&power RK3588_PD_PCIE>;ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,<0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;reg = <0xa 0x40000000 0x0 0x00400000>,<0x0 0xfe150000 0x0 0x00010000>,<0x0 0xf0000000 0x0 0x00100000>;reg-names = "dbi", "apb", "config";resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;reset-names = "pwr", "pipe";status = "disabled";pcie3x4_intc: legacy-interrupt-controller {interrupt-controller;#address-cells = <0>;#interrupt-cells = <1>;interrupt-parent = <&gic>;interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;};- };
- pcie3x2: pcie@fe160000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";#address-cells = <3>;#size-cells = <2>;bus-range = <0x10 0x1f>;clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;clock-names = "aclk_mst", "aclk_slv","aclk_dbi", "pclk","aux", "pipe";device_type = "pci";interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;interrupt-names = "sys", "pmc", "msg", "legacy", "err";#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 7>;interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,<0 0 0 2 &pcie3x2_intc 1>,<0 0 0 3 &pcie3x2_intc 2>,<0 0 0 4 &pcie3x2_intc 3>;linux,pci-domain = <1>;max-link-speed = <3>;msi-map = <0x1000 &its1 0x1000 0x1000>;num-lanes = <2>;phys = <&pcie30phy>;phy-names = "pcie-phy";power-domains = <&power RK3588_PD_PCIE>;ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,<0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;reg = <0xa 0x40400000 0x0 0x00400000>,<0x0 0xfe160000 0x0 0x00010000>,<0x0 0xf1000000 0x0 0x00100000>;reg-names = "dbi", "apb", "config";resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;reset-names = "pwr", "pipe";status = "disabled";pcie3x2_intc: legacy-interrupt-controller {interrupt-controller;#address-cells = <0>;#interrupt-cells = <1>;interrupt-parent = <&gic>;interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;};- };
- pcie2x1l0: pcie@fe170000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";bus-range = <0x20 0x2f>;clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,<&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;clock-names = "aclk_mst", "aclk_slv","aclk_dbi", "pclk","aux", "pipe";device_type = "pci";interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;interrupt-names = "sys", "pmc", "msg", "legacy", "err";#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 7>;interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,<0 0 0 2 &pcie2x1l0_intc 1>,<0 0 0 3 &pcie2x1l0_intc 2>,<0 0 0 4 &pcie2x1l0_intc 3>;linux,pci-domain = <2>;max-link-speed = <2>;msi-map = <0x2000 &its0 0x2000 0x1000>;num-lanes = <1>;phys = <&combphy1_ps PHY_TYPE_PCIE>;phy-names = "pcie-phy";power-domains = <&power RK3588_PD_PCIE>;ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,<0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;reg = <0xa 0x40800000 0x0 0x00400000>,<0x0 0xfe170000 0x0 0x00010000>,<0x0 0xf2000000 0x0 0x00100000>;reg-names = "dbi", "apb", "config";resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;reset-names = "pwr", "pipe";#address-cells = <3>;#size-cells = <2>;status = "disabled";pcie2x1l0_intc: legacy-interrupt-controller {interrupt-controller;#address-cells = <0>;#interrupt-cells = <1>;interrupt-parent = <&gic>;interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;};- };
- gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>;
@@ -123,4 +286,56 @@ queue1 {}; }; };
- sata1: sata@fe220000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";reg = <0 0xfe220000 0 0x1000>;interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;clock-names = "sata", "pmalive", "rxoob", "ref", "asic";ports-implemented = <0x1>;#address-cells = <1>;#size-cells = <0>;status = "disabled";sata-port@0 {reg = <0>;hba-port-cap = <HBA_PORT_FBSCP>;phys = <&combphy1_ps PHY_TYPE_SATA>;phy-names = "sata-phy";snps,rx-ts-max = <32>;snps,tx-ts-max = <32>;};- };
- combphy1_ps: phy@fee10000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee10000 0x0 0x100>;clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,<&cru PCLK_PHP_ROOT>;clock-names = "ref", "apb", "pipe";assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;assigned-clock-rates = <100000000>;#phy-cells = <1>;resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;reset-names = "phy", "apb";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy1_grf>;status = "disabled";- };
- pcie30phy: phy@fee80000 {
compatible = "rockchip,rk3588-pcie3-phy";reg = <0x0 0xfee80000 0x0 0x20000>;#phy-cells = <0>;clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;clock-names = "pclk";resets = <&cru SRST_PCIE30_PHY>;reset-names = "phy";rockchip,pipe-grf = <&php_grf>;rockchip,phy-grf = <&pcie30_phy_grf>;status = "disabled";- }; };
diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi index 9bb0e4f89e..c47b0a7112 100644 --- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -10,25 +10,13 @@ #include <dt-bindings/usb/pd.h>
/ {
- aliases {
mmc1 = &sdmmc;- };
- chosen { u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; }; };
-&sdmmc {
- bus-width = <4>;
- status = "okay";
-};
- &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; };
diff --git a/arch/arm/dts/rk3588s-rock-5a.dts b/arch/arm/dts/rk3588s-rock-5a.dts index 901825514f..8347adcbd0 100644 --- a/arch/arm/dts/rk3588s-rock-5a.dts +++ b/arch/arm/dts/rk3588s-rock-5a.dts @@ -3,6 +3,7 @@ /dts-v1/;
#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> #include "rk3588s.dtsi"
@@ -12,12 +13,252 @@
aliases { mmc0 = &sdhci;
mmc1 = &sdmmc;serial2 = &uart2; };
analog-sound {
compatible = "audio-graph-card";label = "rk3588-es8316";widgets = "Microphone", "Mic Jack","Headphone", "Headphones";routing = "MIC2", "Mic Jack","Headphones", "HPOL","Headphones", "HPOR";dais = <&i2s0_8ch_p0>;};
chosen { stdout-path = "serial2:1500000n8"; };
leds {
compatible = "gpio-leds";pinctrl-names = "default";pinctrl-0 = <&io_led>;io-led {color = <LED_COLOR_ID_BLUE>;function = LED_FUNCTION_STATUS;gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";};};
fan: pwm-fan {
compatible = "pwm-fan";cooling-levels = <0 95 145 195 255>;fan-supply = <&vcc_5v0>;pwms = <&pwm3 0 50000 0>;#cooling-cells = <2>;};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";regulator-name = "vcc12v_dcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <12000000>;regulator-max-microvolt = <12000000>;};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_host";regulator-boot-on;regulator-always-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_host_en>;vin-supply = <&vcc5v0_sys>;};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;};
vcc_5v0: vcc-5v0-regulator {
compatible = "regulator-fixed";regulator-name = "vcc_5v0";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-boot-on;regulator-always-on;enable-active-high;gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc_5v0_en>;vin-supply = <&vcc5v0_sys>;};
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";regulator-name = "vcc_1v1_nldo_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1100000>;vin-supply = <&vcc5v0_sys>;};
+};
+&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
+};
+&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
+};
+&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
+};
+&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
+};
+&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
- status = "okay";
- vdd_cpu_big0_s0: regulator@42 {
compatible = "rockchip,rk8602";reg = <0x42>;fcs,suspend-voltage-selector = <1>;regulator-name = "vdd_cpu_big0_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <2300>;vin-supply = <&vcc5v0_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
- vdd_cpu_big1_s0: regulator@43 {
compatible = "rockchip,rk8603", "rockchip,rk8602";reg = <0x43>;fcs,suspend-voltage-selector = <1>;regulator-name = "vdd_cpu_big1_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <2300>;vin-supply = <&vcc5v0_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
+};
+&i2c2 {
- status = "okay";
- vdd_npu_s0: regulator@42 {
compatible = "rockchip,rk8602";reg = <0x42>;fcs,suspend-voltage-selector = <1>;regulator-name = "vdd_npu_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <2300>;vin-supply = <&vcc5v0_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
- eeprom: eeprom@50 {
compatible = "belling,bl24c16a", "atmel,24c16";reg = <0x50>;pagesize = <16>;- };
+};
+&i2c3 {
- status = "okay";
+};
+&i2c5 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5m2_xfer>;
+};
+&i2c7 {
- status = "okay";
- es8316: audio-codec@11 {
compatible = "everest,es8316";reg = <0x11>;clocks = <&cru I2S0_8CH_MCLKOUT>;clock-names = "mclk";assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;assigned-clock-rates = <12288000>;#sound-dai-cells = <0>;port {es8316_p0_0: endpoint {remote-endpoint = <&i2s0_8ch_p0_0>;};};- };
+};
+&i2s0_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s0_lrck
&i2s0_mclk&i2s0_sclk&i2s0_sdi0&i2s0_sdo0>;status = "okay";
i2s0_8ch_p0: port {
i2s0_8ch_p0_0: endpoint {dai-format = "i2s";mclk-fs = <256>;remote-endpoint = <&es8316_p0_0>;};}; };
&gmac1 {
@@ -49,11 +290,62 @@ };
&pinctrl {
- leds {
io_led: io-led {rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- power {
vcc_5v0_en: vcc-5v0-en {rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- rtl8211f { rtl8211f_rst: rtl8211f-rst { rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; }; };
- usb {
vcc5v0_host_en: vcc5v0-host-en {rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- wifibt {
wl_reset: wl-reset {rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;};wl_dis: wl-dis {rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>;};wl_wake_host: wl-wake-host {rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;};bt_dis: bt-dis {rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;};bt_wake_host: bt-wake-host {rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;};- };
+};
+&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3m1_pins>;
- status = "okay";
+};
+&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay"; };
&sdhci {
@@ -61,13 +353,384 @@ no-sdio; no-sd; non-removable;
- max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; };
+&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- no-sdio;
- no-mmc;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s0>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
+};
+&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- pmic@0 {
compatible = "rockchip,rk806";reg = <0x0>;interrupt-parent = <&gpio0>;interrupts = <7 IRQ_TYPE_LEVEL_LOW>;pinctrl-names = "default";pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,<&rk806_dvs2_null>, <&rk806_dvs3_null>;spi-max-frequency = <1000000>;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc5-supply = <&vcc5v0_sys>;vcc6-supply = <&vcc5v0_sys>;vcc7-supply = <&vcc5v0_sys>;vcc8-supply = <&vcc5v0_sys>;vcc9-supply = <&vcc5v0_sys>;vcc10-supply = <&vcc5v0_sys>;vcc11-supply = <&vcc_2v0_pldo_s3>;vcc12-supply = <&vcc5v0_sys>;vcc13-supply = <&vcc_1v1_nldo_s3>;vcc14-supply = <&vcc_1v1_nldo_s3>;vcca-supply = <&vcc5v0_sys>;gpio-controller;#gpio-cells = <2>;rk806_dvs1_null: dvs1-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs2_null: dvs2-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs3_null: dvs3-null-pins {pins = "gpio_pwrctrl3";function = "pin_fun0";};regulators {vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {regulator-name = "vdd_gpu_s0";regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-enable-ramp-delay = <400>;regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {regulator-name = "vdd_cpu_lit_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};vdd_log_s0: dcdc-reg3 {regulator-name = "vdd_log_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {regulator-name = "vdd_vdenc_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};vdd_ddr_s0: dcdc-reg5 {regulator-name = "vdd_ddr_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <900000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <850000>;};};vdd2_ddr_s3: dcdc-reg6 {regulator-name = "vdd2_ddr_s3";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;};};vcc_2v0_pldo_s3: dcdc-reg7 {regulator-name = "vdd_2v0_pldo_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <2000000>;regulator-max-microvolt = <2000000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <2000000>;};};vcc_3v3_s3: dcdc-reg8 {regulator-name = "vcc_3v3_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vddq_ddr_s0: dcdc-reg9 {regulator-name = "vddq_ddr_s0";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s3: dcdc-reg10 {regulator-name = "vcc_1v8_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};avcc_1v8_s0: pldo-reg1 {regulator-name = "avcc_1v8_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s0: pldo-reg2 {regulator-name = "vcc_1v8_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <1800000>;};};avdd_1v2_s0: pldo-reg3 {regulator-name = "avdd_1v2_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_s0: pldo-reg4 {regulator-name = "vcc_3v3_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};vccio_sd_s0: pldo-reg5 {regulator-name = "vccio_sd_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};pldo6_s3: pldo-reg6 {regulator-name = "pldo6_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_0v75_s3: nldo-reg1 {regulator-name = "vdd_0v75_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_ddr_pll_s0: nldo-reg2 {regulator-name = "vdd_ddr_pll_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <850000>;};};avdd_0v75_s0: nldo-reg3 {regulator-name = "avdd_0v75_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-state-mem {regulator-off-in-suspend;};};vdd_0v85_s0: nldo-reg4 {regulator-name = "vdd_0v85_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-state-mem {regulator-off-in-suspend;};};vdd_0v75_s0: nldo-reg5 {regulator-name = "vdd_0v75_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-state-mem {regulator-off-in-suspend;};};};- };
+};
+&u2phy2 {
- status = "okay";
+};
+&u2phy2_host {
- status = "okay";
- phy-supply = <&vcc5v0_host>;
+};
+&u2phy3 {
- status = "okay";
+};
+&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
- &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; };
+&usb_host0_ehci {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&wl_reset &wl_dis &wl_wake_host &bt_dis &bt_wake_host>;
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&usb_host1_ehci {
- status = "okay";
+};
+&usb_host1_ohci {
- status = "okay";
+}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 245bc8b27c..27b2d7eff8 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -53,57 +53,12 @@ }; };
usb_host0_ehci: usb@fc800000 {
compatible = "generic-ehci";reg = <0x0 0xfc800000 0x0 0x40000>;interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";};
usb_host0_ohci: usb@fc840000 {
compatible = "generic-ohci";reg = <0x0 0xfc840000 0x0 0x40000>;interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";};
usb_host1_ehci: usb@fc880000 {
compatible = "generic-ehci";reg = <0x0 0xfc880000 0x0 0x40000>;interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";};
usb_host1_ohci: usb@fc8c0000 {
compatible = "generic-ohci";reg = <0x0 0xfc8c0000 0x0 0x40000>;interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";};
pmu1_grf: syscon@fd58a000 { bootph-all; compatible = "rockchip,rk3588-pmu1-grf", "syscon"; reg = <0x0 0xfd58a000 0x0 0x2000>; };
pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,pipe-phy-grf", "syscon";reg = <0x0 0xfd5bc000 0x0 0x100>;};
usb2phy0_grf: syscon@fd5d0000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
@@ -131,29 +86,6 @@ }; };
- usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon","simple-mfd";reg = <0x0 0xfd5d8000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy2: usb2-phy@8000 {compatible = "rockchip,rk3588-usb2phy";reg = <0x8000 0x10>;interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";#clock-cells = <0>;status = "disabled";u2phy2_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
- vo0_grf: syscon@fd5a6000 { compatible = "rockchip,rk3588-vo-grf", "syscon"; reg = <0x0 0xfd5a6000 0x0 0x2000>;
@@ -165,89 +97,11 @@ reg = <0x0 0xfd5ac000 0x0 0x4000>; };
usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon","simple-mfd";reg = <0x0 0xfd5dc000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy3: usb2-phy@c000 {compatible = "rockchip,rk3588-usb2phy";reg = <0xc000 0x10>;interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";#clock-cells = <0>;status = "disabled";u2phy3_host: host-port {#phy-cells = <0>;status = "disabled";};};};
usbdpphy0_grf: syscon@fd5c8000 { compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; reg = <0x0 0xfd5c8000 0x0 0x4000>; };
pcie2x1l2: pcie@fe190000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";#address-cells = <3>;#size-cells = <2>;bus-range = <0x40 0x4f>;clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,<&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;clock-names = "aclk_mst", "aclk_slv","aclk_dbi", "pclk","aux", "pipe";device_type = "pci";interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;interrupt-names = "sys", "pmc", "msg", "legacy", "err";#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 7>;interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,<0 0 0 2 &pcie2x1l2_intc 1>,<0 0 0 3 &pcie2x1l2_intc 2>,<0 0 0 4 &pcie2x1l2_intc 3>;linux,pci-domain = <4>;num-ib-windows = <8>;num-ob-windows = <8>;num-viewport = <4>;max-link-speed = <2>;msi-map = <0x4000 &gic 0x4000 0x1000>;num-lanes = <1>;phys = <&combphy0_ps PHY_TYPE_PCIE>;phy-names = "pcie-phy";power-domains = <&power RK3588_PD_PCIE>;ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,<0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;reg = <0xa 0x41000000 0x0 0x00400000>,<0x0 0xfe190000 0x0 0x00010000>,<0x0 0xf4000000 0x0 0x00100000>;reg-names = "dbi", "apb", "config";resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;reset-names = "pcie", "periph";rockchip,pipe-grf = <&php_grf>;status = "disabled";pcie2x1l2_intc: legacy-interrupt-controller {interrupt-controller;#address-cells = <0>;#interrupt-cells = <1>;interrupt-parent = <&gic>;interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;};};
sfc: spi@fe2b0000 { compatible = "rockchip,sfc"; reg = <0x0 0xfe2b0000 0x0 0x4000>;
@@ -293,22 +147,6 @@ status = "disabled"; }; };
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee00000 0x0 0x100>;#phy-cells = <1>;clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,<&cru PCLK_PHP_ROOT>;clock-names = "refclk", "apbclk", "phpclk";assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;assigned-clock-rates = <100000000>;resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;reset-names = "combphy-apb", "combphy";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy0_grf>;status = "disabled";}; };
&emmc_bus8 {
diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index 7dbac9ae2e..5544f66c6f 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/rk3588-power.h> #include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/ata/ahci.h>
/ { compatible = "rockchip,rk3588"; @@ -397,6 +399,50 @@ }; };
- usb_host0_ehci: usb@fc800000 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";reg = <0x0 0xfc800000 0x0 0x40000>;interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;phys = <&u2phy2_host>;phy-names = "usb";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host0_ohci: usb@fc840000 {
compatible = "rockchip,rk3588-ohci", "generic-ohci";reg = <0x0 0xfc840000 0x0 0x40000>;interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;phys = <&u2phy2_host>;phy-names = "usb";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host1_ehci: usb@fc880000 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";reg = <0x0 0xfc880000 0x0 0x40000>;interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;phys = <&u2phy3_host>;phy-names = "usb";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host1_ohci: usb@fc8c0000 {
compatible = "rockchip,rk3588-ohci", "generic-ohci";reg = <0x0 0xfc8c0000 0x0 0x40000>;interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;phys = <&u2phy3_host>;phy-names = "usb";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>;
@@ -407,6 +453,66 @@ reg = <0x0 0xfd5b0000 0x0 0x1000>; };
- pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";reg = <0x0 0xfd5bc000 0x0 0x100>;- };
- pipe_phy2_grf: syscon@fd5c4000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";reg = <0x0 0xfd5c4000 0x0 0x100>;- };
- usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";reg = <0x0 0xfd5d8000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy2: usb2-phy@8000 {compatible = "rockchip,rk3588-usb2phy";reg = <0x8000 0x10>;interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;reset-names = "phy", "apb";clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";clock-output-names = "usb480m_phy2";#clock-cells = <0>;status = "disabled";u2phy2_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
- usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";reg = <0x0 0xfd5dc000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy3: usb2-phy@c000 {compatible = "rockchip,rk3588-usb2phy";reg = <0xc000 0x10>;interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;reset-names = "phy", "apb";clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";clock-output-names = "usb480m_phy3";#clock-cells = <0>;status = "disabled";u2phy3_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
- ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -830,6 +936,57 @@ }; };
- i2s4_8ch: i2s@fddc0000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfddc0000 0x0 0x1000>;interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac2 0>;dma-names = "tx";power-domains = <&power RK3588_PD_VO0>;resets = <&cru SRST_M_I2S4_8CH_TX>;reset-names = "tx-m";#sound-dai-cells = <0>;status = "disabled";- };
- i2s5_8ch: i2s@fddf0000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfddf0000 0x0 0x1000>;interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac2 2>;dma-names = "tx";power-domains = <&power RK3588_PD_VO1>;resets = <&cru SRST_M_I2S5_8CH_TX>;reset-names = "tx-m";#sound-dai-cells = <0>;status = "disabled";- };
- i2s9_8ch: i2s@fddfc000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfddfc000 0x0 0x1000>;interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac2 23>;dma-names = "rx";power-domains = <&power RK3588_PD_VO1>;resets = <&cru SRST_M_I2S9_8CH_RX>;reset-names = "rx-m";#sound-dai-cells = <0>;status = "disabled";- };
- qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>;
@@ -1070,6 +1227,108 @@ reg = <0x0 0xfdf82200 0x0 0x20>; };
- pcie2x1l1: pcie@fe180000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";bus-range = <0x30 0x3f>;clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,<&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,<&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;clock-names = "aclk_mst", "aclk_slv","aclk_dbi", "pclk","aux", "pipe";device_type = "pci";interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;interrupt-names = "sys", "pmc", "msg", "legacy", "err";#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 7>;interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,<0 0 0 2 &pcie2x1l1_intc 1>,<0 0 0 3 &pcie2x1l1_intc 2>,<0 0 0 4 &pcie2x1l1_intc 3>;linux,pci-domain = <3>;max-link-speed = <2>;msi-map = <0x3000 &its0 0x3000 0x1000>;num-lanes = <1>;phys = <&combphy2_psu PHY_TYPE_PCIE>;phy-names = "pcie-phy";power-domains = <&power RK3588_PD_PCIE>;ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,<0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,<0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;reg = <0xa 0x40c00000 0x0 0x00400000>,<0x0 0xfe180000 0x0 0x00010000>,<0x0 0xf3000000 0x0 0x00100000>;reg-names = "dbi", "apb", "config";resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;reset-names = "pwr", "pipe";#address-cells = <3>;#size-cells = <2>;status = "disabled";pcie2x1l1_intc: legacy-interrupt-controller {interrupt-controller;#address-cells = <0>;#interrupt-cells = <1>;interrupt-parent = <&gic>;interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;};- };
- pcie2x1l2: pcie@fe190000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";bus-range = <0x40 0x4f>;clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,<&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;clock-names = "aclk_mst", "aclk_slv","aclk_dbi", "pclk","aux", "pipe";device_type = "pci";interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;interrupt-names = "sys", "pmc", "msg", "legacy", "err";#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 7>;interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,<0 0 0 2 &pcie2x1l2_intc 1>,<0 0 0 3 &pcie2x1l2_intc 2>,<0 0 0 4 &pcie2x1l2_intc 3>;linux,pci-domain = <4>;max-link-speed = <2>;msi-map = <0x4000 &its0 0x4000 0x1000>;num-lanes = <1>;phys = <&combphy0_ps PHY_TYPE_PCIE>;phy-names = "pcie-phy";power-domains = <&power RK3588_PD_PCIE>;ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,<0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;reg = <0xa 0x41000000 0x0 0x00400000>,<0x0 0xfe190000 0x0 0x00010000>,<0x0 0xf4000000 0x0 0x00100000>;reg-names = "dbi", "apb", "config";resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;reset-names = "pwr", "pipe";#address-cells = <3>;#size-cells = <2>;status = "disabled";pcie2x1l2_intc: legacy-interrupt-controller {interrupt-controller;#address-cells = <0>;#interrupt-cells = <1>;interrupt-parent = <&gic>;interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;};- };
- gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>;
@@ -1119,6 +1378,52 @@ }; };
- sata0: sata@fe210000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";reg = <0 0xfe210000 0 0x1000>;interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,<&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,<&cru CLK_PIPEPHY0_PIPE_ASIC_G>;clock-names = "sata", "pmalive", "rxoob", "ref", "asic";ports-implemented = <0x1>;#address-cells = <1>;#size-cells = <0>;status = "disabled";sata-port@0 {reg = <0>;hba-port-cap = <HBA_PORT_FBSCP>;phys = <&combphy0_ps PHY_TYPE_SATA>;phy-names = "sata-phy";snps,rx-ts-max = <32>;snps,tx-ts-max = <32>;};- };
- sata2: sata@fe230000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";reg = <0 0xfe230000 0 0x1000>;interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,<&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,<&cru CLK_PIPEPHY2_PIPE_ASIC_G>;clock-names = "sata", "pmalive", "rxoob", "ref", "asic";ports-implemented = <0x1>;#address-cells = <1>;#size-cells = <0>;status = "disabled";sata-port@0 {reg = <0>;hba-port-cap = <HBA_PORT_FBSCP>;phys = <&combphy2_psu PHY_TYPE_SATA>;phy-names = "sata-phy";snps,rx-ts-max = <32>;snps,tx-ts-max = <32>;};- };
- sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>;
@@ -1134,6 +1439,21 @@ status = "disabled"; };
- sdio: mmc@fe2d0000 {
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";reg = <0x00 0xfe2d0000 0x00 0x4000>;interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";fifo-depth = <0x100>;max-frequency = <200000000>;pinctrl-names = "default";pinctrl-0 = <&sdiom1_pins>;power-domains = <&power RK3588_PD_SDIO>;status = "disabled";- };
- sdhci: mmc@fe2e0000 { compatible = "rockchip,rk3588-dwcmshc"; reg = <0x0 0xfe2e0000 0x0 0x10000>;
@@ -1145,6 +1465,9 @@ <&cru TMCLK_EMMC>; clock-names = "core", "bus", "axi", "block", "timer"; max-frequency = <200000000>;
pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,<&emmc_cmd>, <&emmc_data_strobe>;pinctrl-names = "default";@@ -1742,6 +2065,18 @@ status = "disabled"; };
- saradc: adc@fec10000 {
compatible = "rockchip,rk3588-saradc";reg = <0x0 0xfec10000 0x0 0x10000>;interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;#io-channel-cells = <1>;clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;clock-names = "saradc", "apb_pclk";resets = <&cru SRST_P_SARADC>;reset-names = "saradc-apb";status = "disabled";- };
- i2c6: i2c@fec80000 { compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xfec80000 0x0 0x1000>;
@@ -1862,6 +2197,38 @@ #dma-cells = <1>; };
- combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee00000 0x0 0x100>;clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,<&cru PCLK_PHP_ROOT>;clock-names = "ref", "apb", "pipe";assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;assigned-clock-rates = <100000000>;#phy-cells = <1>;resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;reset-names = "phy", "apb";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy0_grf>;status = "disabled";- };
- combphy2_psu: phy@fee20000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee20000 0x0 0x100>;clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,<&cru PCLK_PHP_ROOT>;clock-names = "ref", "apb", "pipe";assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;assigned-clock-rates = <100000000>;#phy-cells = <1>;resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;reset-names = "phy", "apb";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy2_grf>;status = "disabled";- };
- system_sram2: sram@ff001000 { compatible = "mmio-sram"; reg = <0x0 0xff001000 0x0 0xef000>;
diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h new file mode 100644 index 0000000000..b3f3b7cf9a --- /dev/null +++ b/include/dt-bindings/ata/ahci.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/*
- This header provides constants for most AHCI bindings.
- */
+#ifndef _DT_BINDINGS_ATA_AHCI_H +#define _DT_BINDINGS_ATA_AHCI_H
+/* Host Bus Adapter generic platform capabilities */ +#define HBA_SSS (1 << 27) +#define HBA_SMPS (1 << 28)
+/* Host Bus Adapter port-specific platform capabilities */ +#define HBA_PORT_HPCP (1 << 18) +#define HBA_PORT_MPSP (1 << 19) +#define HBA_PORT_CPD (1 << 20) +#define HBA_PORT_ESP (1 << 21) +#define HBA_PORT_FBSCP (1 << 22)
+#endif
participants (3)
-
FUKAUMI Naoki -
Jonas Karlman -
Kever Yang