[U-Boot] [PATCH 1/3] armv8/ls1043a: fixup GIC offset according to SVR and GIC400_ADDR_ALIGN_64K[GIC_ADDR]
The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit GIC400_ADDR_ALIGN_64K[GIC_ADDR] is used to choose which offset will be used.
If GIC_ADDR bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting.
Signed-off-by: Wenbin Song wenbin.song@nxp.com Signed-off-by: Mingkai Hu mingkai.hu@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 47 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 12 +++++- 2 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5d0b7a4..569d2c2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -14,6 +14,40 @@ #include <asm/arch/mp.h> #endif
+#ifdef CONFIG_LS1043A + +/* fixup GIC offset */ +ENTRY(fix_gic_offset) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + ldr x3, =DCFG_CCSR_SVR + ldr w3, [x3] + rev w3, w3 + ands w3, w3, #0xff + cmp w3, #REV1_0 + b.eq 1f + ldr x3, =SCFG_GIC400_ALIGN + ldr w3, [x3] + rev w3, w3 + tbnz w3, #GIC_ADDR_BIT, 1f + ret +1: + ldr x0, =GICD_BASE_4K + ldr x1, =GICC_BASE_4K + ret +ENDPROC(fix_gic_offset) + +ENTRY(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ + mov x29, lr /* Save LR */ + bl fix_gic_offset + bl gic_kick_secondary_cpus + mov lr, x29 /* Restore LR */ + ret +ENDPROC(smp_kick_all_cpus) + +#endif + ENTRY(lowlevel_init) mov x29, lr /* Save LR */
@@ -105,15 +139,23 @@ ENTRY(lowlevel_init) /* Initialize GIC Secure Bank Status */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f +#ifdef CONFIG_LS1043A + bl fix_gic_offset +#else ldr x0, =GICD_BASE +#endif bl gic_init_secure 1: #ifdef CONFIG_GICV3 ldr x0, =GICR_BASE bl gic_init_secure_percpu #elif defined(CONFIG_GICV2) +#ifdef CONFIG_LS1043A + bl fix_gic_offset +#else ldr x0, =GICD_BASE ldr x1, =GICC_BASE +#endif bl gic_init_secure_percpu #endif #endif @@ -335,7 +377,12 @@ ENTRY(secondary_boot_func) #if defined(CONFIG_GICV3) gic_wait_for_interrupt_m x0 #elif defined(CONFIG_GICV2) +#ifdef CONFIG_LS1043A + bl fix_gic_offset + mov x0, x1 +#else ldr x0, =GICC_BASE +#endif gic_wait_for_interrupt_m x0, w1 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 4201e0f..eb6e58d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -172,8 +172,16 @@ #define SMMU_BASE 0x09000000
/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x01401000 -#define GICC_BASE 0x01402000 +#define GICD_BASE 0x01410000 +#define GICC_BASE 0x01420000 +#define GICD_BASE_4K 0x01401000 +#define GICC_BASE_4K 0x01402000 + +#define DCFG_CCSR_SVR 0x1ee00a4 +#define REV1_0 0x10 +#define REV1_1 0x11 +#define GIC_ADDR_BIT 31 +#define SCFG_GIC400_ALIGN 0x1570188
#define CONFIG_SYS_FSL_ERRATUM_A008850 #define CONFIG_SYS_FSL_ERRATUM_A009663
The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. 4K alignment is consistent with rev1 implement.
The default GIC offset in kernel device tree is using 64K alignment, if rev1 silicon used, need to fixup the GIC node to use 4K alignment.
Signed-off-by: Wenbin Song wenbin.song@nxp.com Signed-off-by: Mingkai Hu mingkai.hu@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 47 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +- 2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 1a8321b..5a80ff2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -126,6 +126,52 @@ void fsl_fdt_disable_usb(void *blob) } }
+#ifdef CONFIG_LS1043A +/* Fixup gic node align with 4K */ +static void fdt_fixup_gic(void *blob) +{ + int offset, err; + u64 reg[8]; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int val; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + val = gur_in32(&gur->svr) & 0xff; + + if (val == REV1_1) { + val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT); + if (!val) + return; + } + + offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000"); + if (offset < 0) { + printf("WARNING: fdt_subnode_offset can't find node %s: %s\n", + "interrupt-controller@1400000", fdt_strerror(offset)); + return; + } + + reg[0] = cpu_to_fdt64(0x1401000); + reg[1] = cpu_to_fdt64(0x1000); + reg[2] = cpu_to_fdt64(0x1402000); + reg[3] = cpu_to_fdt64(0x2000); + reg[4] = cpu_to_fdt64(0x1404000); + reg[5] = cpu_to_fdt64(0x2000); + reg[6] = cpu_to_fdt64(0x1406000); + reg[7] = cpu_to_fdt64(0x2000); + + err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg)); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s\n", + "reg", "interrupt-controller@1400000", + fdt_strerror(err)); + return; + } + + return; +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FSL_LSCH2 @@ -143,6 +189,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif + fdt_fixup_gic(blob); #endif
#ifdef CONFIG_MP diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d88543d..1dfef53 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -359,7 +359,8 @@ struct ccsr_scfg { u32 qspi_cfg; u8 res_160[0x180-0x160]; u32 dmamcr; - u8 res_184[0x18c-0x184]; + u8 res_184[0x188-0x184]; + u32 gic_align; u32 debug_icid; u8 res_190[0x1a4-0x190]; u32 snpcnfgcr;
The default MSI node in kernel tree is for LS1043A rev1.1 silicon, if rev1.0 silicon used, need to fixup the MSI node to match it.
Signed-off-by: Wenbin Song wenbin.song@nxp.com Signed-off-by: Mingkai Hu mingkai.hu@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 91 +++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 5a80ff2..14458dc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -170,6 +170,96 @@ static void fdt_fixup_gic(void *blob)
return; } + +static int _fdt_fixup_msi_subnode(void *blob, int parentoffset, + const char *name, int irq_no) +{ + int err, offset; + u32 tmp[3]; + + offset = fdt_subnode_offset(blob, parentoffset, name); + if (offset < 0) { + printf("WARNING: fdt_subnode_offset can't find %s: %s\n", + name, fdt_strerror(offset)); + return 0; + } + + tmp[0] = cpu_to_fdt32(0x0); + tmp[1] = cpu_to_fdt32(irq_no); + tmp[2] = cpu_to_fdt32(0x4); + + err = fdt_setprop(blob, offset, "interrupts", tmp, sizeof(tmp)); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s\n", + "interrupts", name, fdt_strerror(err)); + return 0; + } + + return 1; +} + +static int _fdt_fixup_pci_msi(void *blob, const char *name) +{ + int offset, len, err; + void *p; + int val; + u32 tmp[4][8]; + + offset = fdt_path_offset(blob, name); + if (offset < 0) { + printf("WARNING: fdt_path_offset can't find path %s: %s\n", + name, fdt_strerror(offset)); + return 0; + } + + p = (char *)fdt_getprop(blob, offset, "interrupt-map", &len); + if (!p || len != sizeof(tmp)) { + printf("WARNING: fdt_getprop can't get %s from node %s\n", + "interrupt-map", name); + return 0; + } + + memcpy((char *)tmp, p, len); + val = fdt32_to_cpu(tmp[0][6]); + tmp[1][6] = cpu_to_fdt32(val + 1); + tmp[2][6] = cpu_to_fdt32(val + 2); + tmp[3][6] = cpu_to_fdt32(val + 3); + + err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp)); + if (err < 0) { + printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n", + "interrupt-map", name, fdt_strerror(err)); + return 0; + } + return 1; +} + +/* Fixup msi to v1_0*/ + +static void fdt_fixup_msi(void *blob) +{ + int nodeoffset; + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int val; + + val = gur_in32(&gur->svr) & 0xff; + if (val == REV1_1) + return; + + nodeoffset = fdt_path_offset(blob, "/soc/msi-controller"); + if (nodeoffset < 0) { + printf("WARNING: fdt_path_offset can't find path %s: %s\n", + "/soc/msi-controller", fdt_strerror(nodeoffset)); + return; + } + _fdt_fixup_msi_subnode(blob, nodeoffset, "msi0@1571000", 116); + _fdt_fixup_msi_subnode(blob, nodeoffset, "msi1@1572000", 126); + _fdt_fixup_msi_subnode(blob, nodeoffset, "msi2@1573000", 160); + + _fdt_fixup_pci_msi(blob, "/soc/pcie@3400000"); + _fdt_fixup_pci_msi(blob, "/soc/pcie@3500000"); + _fdt_fixup_pci_msi(blob, "/soc/pcie@3600000"); +} #endif
void ft_cpu_setup(void *blob, bd_t *bd) @@ -190,6 +280,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) } #endif fdt_fixup_gic(blob); + fdt_fixup_msi(blob); #endif
#ifdef CONFIG_MP
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