Enable dynamic DDR calibration to have a reliable behavior on edge temperatures conditions.

Signed-off-by: Max Krummenacher max.krummenacher@toradex.com Signed-off-by: Francesco Dolcini francesco.dolcini@toradex.com ---

board/toradex/colibri_imx6/colibri_imx6.c | 22 ++++++++++++++++++++++ configs/colibri_imx6_defconfig | 1 + 2 files changed, 23 insertions(+)

diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 587d92a8e9..0fdeec51c4 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -998,9 +998,28 @@ static void ddr_init(int *table, int size) writel(table[2 * i + 1], table[2 * i]); }

+/* Perform DDR DRAM calibration */ +static void spl_dram_perform_cal(u8 dsize) +{ +#ifdef CONFIG_MX6_DDRCAL + int err; + struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = dsize, + }; + + err = mmdc_do_write_level_calibration(&ddr_sysinfo); + if (err) + printf("error %d from write level calibration\n", err); + err = mmdc_do_dqs_calibration(&ddr_sysinfo); + if (err) + printf("error %d from dqs calibration\n", err); +#endif +} + static void spl_dram_init(void) { int minc, maxc; + u8 dsize = 2;

switch (get_cpu_temp_grade(&minc, &maxc)) { case TEMP_COMMERCIAL: @@ -1010,6 +1029,7 @@ static void spl_dram_init(void) ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n"); + dsize = 1; ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; @@ -1021,11 +1041,13 @@ static void spl_dram_init(void) ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); + dsize = 1; ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; }; udelay(100); + spl_dram_perform_cal(dsize); }

static iomux_v3_cfg_t const gpio_reset_pad[] = { diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 47b1cfb191..5a4f901fa7 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_MX6DL=y +CONFIG_MX6_DDRCAL=y CONFIG_TARGET_COLIBRI_IMX6=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6-colibri"

Enable dynamic DDR calibration to have a reliable behavior on edge temperatures conditions.

Signed-off-by: Max Krummenacher max.krummenacher@toradex.com Signed-off-by: Francesco Dolcini francesco.dolcini@toradex.com

---

board/toradex/apalis_imx6/apalis_imx6.c | 19 +++++++++++++++++++ configs/apalis_imx6_defconfig | 1 + 2 files changed, 20 insertions(+)

diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 74060daadd..ce64ace0d4 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -1077,6 +1077,24 @@ static void ddr_init(int *table, int size) writel(table[2 * i + 1], table[2 * i]); }

+/* Perform DDR DRAM calibration */ +static void spl_dram_perform_cal(void) +{ +#ifdef CONFIG_MX6_DDRCAL + int err; + struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 2, + }; + + err = mmdc_do_write_level_calibration(&ddr_sysinfo); + if (err) + printf("error %d from write level calibration\n", err); + err = mmdc_do_dqs_calibration(&ddr_sysinfo); + if (err) + printf("error %d from dqs calibration\n", err); +#endif +} + static void spl_dram_init(void) { int minc, maxc; @@ -1095,6 +1113,7 @@ static void spl_dram_init(void) break; }; udelay(100); + spl_dram_perform_cal(); }

void board_init_f(ulong dummy) diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index a0e85ba23a..0e06e75818 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_MX6Q=y +CONFIG_MX6_DDRCAL=y CONFIG_TARGET_APALIS_IMX6=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6-apalis"