[PATCH] arm: mvebu: db-88f6720: Fix CONFIG_SPL_TEXT_BASE and remove wrong memory layout
Memory layout in the comment is from Armada XP platform which uses load address 0x40004030. DB-88f6720 is Armada 375 platform which uses same load address as Armada 38x which is 0x40000030.
Currently SPL support for Armada 375 is unfinished and does not work. There is missing Serdes initialization and DDR3 training code. So nobody noticed that CONFIG_SPL_* options are not correct.
Fix at least CONFIG_SPL_TEXT_BASE constant and remove incorrect comments about memory layout. So it is not misleading.
Signed-off-by: Pali Rohár pali@kernel.org --- configs/db-88f6720_defconfig | 2 +- include/configs/db-88f6720.h | 15 +-------------- 2 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 32a7349993ca..2e8f4c00de50 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-375-db" -CONFIG_SPL_TEXT_BASE=0x40004030 +CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 19fc669f89d1..cf9e44d17c32 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -32,22 +32,9 @@ */ #include "mv-common.h"
-/* - * Memory layout while starting into the bin_hdr via the - * BootROM: - * - * 0x4000.4000 - 0x4003.4000 headers space (192KiB) - * 0x4000.4030 bin_hdr start address - * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) - * 0x4007.fffc BootROM stack top - * - * The address space between 0x4007.fffc and 0x400f.fff is not locked in - * L2 cache thus cannot be used. - */ - /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x0030)
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
On 1/12/22 18:30, Pali Rohár wrote:
Memory layout in the comment is from Armada XP platform which uses load address 0x40004030. DB-88f6720 is Armada 375 platform which uses same load address as Armada 38x which is 0x40000030.
Currently SPL support for Armada 375 is unfinished and does not work. There is missing Serdes initialization and DDR3 training code. So nobody noticed that CONFIG_SPL_* options are not correct.
Fix at least CONFIG_SPL_TEXT_BASE constant and remove incorrect comments about memory layout. So it is not misleading.
Signed-off-by: Pali Rohár pali@kernel.org
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
configs/db-88f6720_defconfig | 2 +- include/configs/db-88f6720.h | 15 +-------------- 2 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 32a7349993ca..2e8f4c00de50 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-375-db" -CONFIG_SPL_TEXT_BASE=0x40004030 +CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 19fc669f89d1..cf9e44d17c32 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -32,22 +32,9 @@ */ #include "mv-common.h"
-/*
- Memory layout while starting into the bin_hdr via the
- BootROM:
- 0x4000.4000 - 0x4003.4000 headers space (192KiB)
- 0x4000.4030 bin_hdr start address
- 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
- 0x4007.fffc BootROM stack top
- The address space between 0x4007.fffc and 0x400f.fff is not locked in
- L2 cache thus cannot be used.
- */
- /* SPL */ /* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x0030)
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
Viele Grüße, Stefan Roese
On 1/12/22 18:30, Pali Rohár wrote:
Memory layout in the comment is from Armada XP platform which uses load address 0x40004030. DB-88f6720 is Armada 375 platform which uses same load address as Armada 38x which is 0x40000030.
Currently SPL support for Armada 375 is unfinished and does not work. There is missing Serdes initialization and DDR3 training code. So nobody noticed that CONFIG_SPL_* options are not correct.
Fix at least CONFIG_SPL_TEXT_BASE constant and remove incorrect comments about memory layout. So it is not misleading.
Signed-off-by: Pali Rohár pali@kernel.org
Applied to u-boot-marvell/master
Thanks, Stefan
configs/db-88f6720_defconfig | 2 +- include/configs/db-88f6720.h | 15 +-------------- 2 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 32a7349993ca..2e8f4c00de50 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="armada-375-db" -CONFIG_SPL_TEXT_BASE=0x40004030 +CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xf1012000 diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 19fc669f89d1..cf9e44d17c32 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -32,22 +32,9 @@ */ #include "mv-common.h"
-/*
- Memory layout while starting into the bin_hdr via the
- BootROM:
- 0x4000.4000 - 0x4003.4000 headers space (192KiB)
- 0x4000.4030 bin_hdr start address
- 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
- 0x4007.fffc BootROM stack top
- The address space between 0x4007.fffc and 0x400f.fff is not locked in
- L2 cache thus cannot be used.
- */
- /* SPL */ /* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x0030)
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
Viele Grüße, Stefan Roese
participants (2)
-
Pali Rohár -
Stefan Roese