Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM(256K) and copy SPL(192K). This further initialise DDR using SPD and environment and copy u-boot(512 kb) from NAND to DDR. Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly

Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next

Changes for v2: sending as it is

board/freescale/t1040qds/Makefile | 9 ++- board/freescale/t1040qds/README | 33 ++++++++++ board/freescale/t1040qds/ddr.c | 7 ++- board/freescale/t1040qds/spl.c | 122 +++++++++++++++++++++++++++++++++++++ board/freescale/t1040qds/tlb.c | 8 ++- boards.cfg | 1 + include/configs/T1040QDS.h | 58 +++++++++++++++--- 7 files changed, 227 insertions(+), 11 deletions(-) create mode 100644 board/freescale/t1040qds/spl.c

diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index 8f0057b..8f3d7ef 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -8,9 +8,16 @@ include $(TOPDIR)/config.mk

LIB = $(obj)lib$(BOARD).o

+ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o +endif + +ifndef CONFIG_SPL_BUILD COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +endif + COBJS-y += ddr.o -COBJS-$(CONFIG_PCI) += pci.o COBJS-y += law.o COBJS-y += tlb.o

diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README index f8b53b4..0e4d32e 100644 --- a/board/freescale/t1040qds/README +++ b/board/freescale/t1040qds/README @@ -167,3 +167,36 @@ T1042 Personality -------------------- T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit Ethernet switch. Rest of the blocks are same as T1040 + + +2 Stage boot loader +------------------- +PBL initialise the internal SRAM and copy SPL(192K) in SRAM. +SPL further initialise DDR using SPD and environment variables and copy +u-boot(512 KB) from flash to DDR. +Finally SPL transer control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - Actual SPL size 96K + padding till 192K for extra code + - No relocation required + + Run time view of SPL framework :- + ----------------------------------------------- + Area | Address | + ----------------------------------------------- + GD, BD | 0x0xFFFC0000 (4K) | + ----------------------------------------------- + HEAP | 0xFFFC1000 (40K) grow downwards | + ----------------------------------------------- + STACK | 0xFFFD0000 (20K) grow upwards | + ----------------------------------------------- + U-boot SPL | 0xfffD0000 - 0xfffffffc (192K) | + ----------------------------------------------- + +Command to build 2 stage NAND boot loader + - modify RCW at board/freescale/t1040qds/t1040_rcw.cfg for nand boot + -66000002 00000000 fc027000 01000000 + +66000002 00000000 ec106000 01000000 + - make T1040QDS_NAND_config + - make u-boot-with-spl-pbl.bin diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 4fd17da..dd2e0cb 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -107,11 +107,14 @@ phys_size_t initdram(int board_type)

puts("Initializing....using SPD\n");

+#ifdef CONFIG_SPL_BUILD dram_size = fsl_ddr_sdram();

dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - - puts(" DDR: "); +#else + puts("DDR has been initialised by pre loader\n"); + dram_size = 0x80000000; +#endif return dram_size; } diff --git a/board/freescale/t1040qds/spl.c b/board/freescale/t1040qds/spl.c new file mode 100644 index 0000000..5f39466 --- /dev/null +++ b/board/freescale/t1040qds/spl.c @@ -0,0 +1,122 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <ns16550.h> +#include <asm/spl.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <malloc.h> +#include <nand.h> +#include <i2c.h> +#include "../common/qixis.h" +#include "t1040qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +ulong get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; + u32 stack = CONFIG_SPL_RELOC_STACK; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + /* clear BSS segment */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* Set STACK pointer */ + asm volatile ("lwz 1, %0" : : "m"(stack)); + + board_init_r(NULL, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + env_init(); + + /* relocate environment function pointers etc. */ + env_relocate(); + + i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); + + gd->ram_size = initdram(0); + puts("Second program loader running in sram...\n"); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_boot(); +#endif +} diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c index 412c591..c733040 100644 --- a/board/freescale/t1040qds/tlb.c +++ b/board/freescale/t1040qds/tlb.c @@ -52,7 +52,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), - +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -82,6 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -103,6 +104,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 11, BOOKE_PAGESZ_4K, 1), #endif

+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 17, BOOKE_PAGESZ_2G, 1) +#endif };

int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 5e10125..295d952 100644 --- a/boards.cfg +++ b/boards.cfg @@ -963,6 +963,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Naveen Burmi NaveenBurmi@freescale.com +Active powerpc mpc85xx - freescale t1040qds T1040QDS_NAND T1040QDS:PPC_T1040,RAMBOOT_PBL,NAND Poonam Aggrwal poonam.aggrwal@freescale.com Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach eibach@gdsys.de Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach eibach@gdsys.de Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach eibach@gdsys.de diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7c6bec8..6269ce5 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -30,10 +30,40 @@ #define CONFIG_PHYS_64BIT

#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SKIP_RELOCATE_SPL +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD0000 +#define CONFIG_SPL_PAD_TO 0x80000 +#define CONFIG_SPL_MAX_SIZE 0x30000 +#define RESET_VECTOR_OFFSET 0x2FFFC +#define BOOT_PAGE_OFFSET 0x20000 +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (512 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif +#define CONFIG_RAMBOOT_TEXT_BASE 0xFFFC0000 #endif

/* High Level Configuration Options */ @@ -97,8 +127,8 @@ #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -144,7 +174,13 @@ unsigned long get_board_ddr_clk(void); /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L3_ADDR + 4 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (40 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L3_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (20 << 10)

#define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -171,7 +207,9 @@ unsigned long get_board_ddr_clk(void);

#define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 +#ifndef CONFIG_SPL_BUILD #define CONFIG_FSL_DDR_INTERACTIVE +#endif

#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -347,7 +385,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif

-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif

#if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT @@ -395,7 +437,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif

/* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER @@ -589,7 +633,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (9 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000