From: Marcel Ziswiler marcel.ziswiler@toradex.com

Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com

---

(no changes since v4)

Changes in v4: - Re-synched with v6.1-rc3.

Changes in v2: - imx8ulp: Re-added s400_mu device tree node.

arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 15 +- arch/arm/dts/imx8ulp-evk.dts | 240 ++----- arch/arm/dts/imx8ulp-pinfunc.h | 4 +- arch/arm/dts/imx8ulp.dtsi | 594 +++++------------- include/dt-bindings/clock/imx8ulp-clock.h | 53 +- include/dt-bindings/power/imx8ulp-power.h | 26 + include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 ++ 7 files changed, 369 insertions(+), 622 deletions(-) create mode 100644 include/dt-bindings/power/imx8ulp-power.h create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h

diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index 7c1dab2acf..ad264f271e 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -3,7 +3,16 @@ * Copyright 2021 NXP */

-&{/soc@0} { +/ { + mu@27020000 { + compatible = "fsl,imx8ulp-mu"; + reg = <0 0x27020000 0 0x10000>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&soc { u-boot,dm-spl; };

@@ -23,10 +32,6 @@ u-boot,dm-spl; };

-&s400_mu { - u-boot,dm-spl; -}; - &lpuart5 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts index da09ff48ff..f1c6d933a1 100644 --- a/arch/arm/dts/imx8ulp-evk.dts +++ b/arch/arm/dts/imx8ulp-evk.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2021 NXP */ @@ -8,17 +8,31 @@ #include "imx8ulp.dtsi"

/ { - model = "FSL i.MX8ULP EVK"; + model = "NXP i.MX8ULP EVK"; compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";

chosen { stdout-path = &lpuart5; - bootargs = "console=ttyLP1,115200 earlycon"; };

- usdhc2_pwrseq: usdhc2_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>; + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + clock_ext_rmii: clock-ext-rmii { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "ext_rmii_clk"; + #clock-cells = <0>; + }; + + clock_ext_ts: clock-ext-ts { + compatible = "fixed-clock"; + /* External ts clock is 50MHZ from PHY on EVK board. */ + clock-frequency = <50000000>; + clock-output-names = "ext_ts_clk"; + #clock-cells = <0>; }; };

@@ -30,161 +44,30 @@ status = "okay"; };

-&iomuxc1 { - pinctrl_lpuart5: lpuart5grp { - fsl,pins = < - MX8ULP_PAD_PTF14__LPUART5_TX 0x03 - MX8ULP_PAD_PTF15__LPUART5_RX 0x03 - >; - }; - - pinctrl_lpi2c7: lpi2c7grp { - fsl,pins = < - MX8ULP_PAD_PTE12__LPI2C7_SCL 0x27 - MX8ULP_PAD_PTE13__LPI2C7_SDA 0x27 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43 - MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 - MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 - MX8ULP_PAD_PTD10__SDHC0_D0 0x43 - MX8ULP_PAD_PTD9__SDHC0_D1 0x43 - MX8ULP_PAD_PTD8__SDHC0_D2 0x43 - MX8ULP_PAD_PTD7__SDHC0_D3 0x43 - MX8ULP_PAD_PTD6__SDHC0_D4 0x43 - MX8ULP_PAD_PTD5__SDHC0_D5 0x43 - MX8ULP_PAD_PTD4__SDHC0_D6 0x43 - MX8ULP_PAD_PTD3__SDHC0_D7 0x43 - MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 - >; - }; - - pinctrl_usdhc2_pte: usdhc2ptegrp { - fsl,pins = < - MX8ULP_PAD_PTE1__SDHC2_D0 0x43 - MX8ULP_PAD_PTE0__SDHC2_D1 0x43 - MX8ULP_PAD_PTE5__SDHC2_D2 0x43 - MX8ULP_PAD_PTE4__SDHC2_D3 0x43 - MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042 - MX8ULP_PAD_PTE3__SDHC2_CMD 0x43 - MX8ULP_PAD_PTE7__PTE7 0x10003 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 - MX8ULP_PAD_PTE15__ENET0_MDC 0x43 - MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 - MX8ULP_PAD_PTE17__ENET0_RXER 0x43 - MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 - MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 - MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 - MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 - MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 - MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043 - MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043 - >; - }; - - pinctrl_usbotg0_id: otg0idgrp { - fsl,pins = < - MX8ULP_PAD_PTF2__USB0_ID 0x10003 - >; - }; - - pinctrl_usbotg1_id: otg1idgrp { - fsl,pins = < - MX8ULP_PAD_PTD23__USB1_ID 0x10003 - >; - }; -}; - &usdhc0 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; pinctrl-1 = <&pinctrl_usdhc0>; - pinctrl-2 = <&pinctrl_usdhc0>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2_pte>; - pinctrl-1 = <&pinctrl_usdhc2_pte>; - pinctrl-2 = <&pinctrl_usdhc2_pte>; - pinctrl-3 = <&pinctrl_usdhc2_pte>; - mmc-pwrseq = <&usdhc2_pwrseq>; - max-frequency = <100000000>; - bus-width = <4>; - keep-power-in-suspend; non-removable; - wakeup-source; - status = "okay"; - - wifi_wake_host { - compatible = "nxp,wifi-wake-host"; - interrupt-parent = <&gpioe>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&lpi2c7 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c7>; - status = "okay"; - - pcal6408: gpio@21 { - compatible = "ti,tca6408"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&flexspi0 { - status = "okay"; - - flash0: atxp032@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <66000000>; - }; -}; - -&flexspi2 { + bus-width = <8>; status = "okay"; - - flash1: mt35xu512aba@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <29000000>; - spi-nor,ddr-quad-read-dummy = <8>; - }; };

&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet>; + pinctrl-1 = <&pinctrl_enet>; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&pcc4 IMX8ULP_CLK_ENET>, + <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, + <&clock_ext_rmii>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>; + assigned-clock-parents = <&clock_ext_ts>; phy-mode = "rmii"; phy-handle = <&ethphy>; status = "okay";

- phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; - mdio { #address-cells = <1>; #size-cells = <0>; @@ -196,28 +79,43 @@ }; };

-&usbotg0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg0_id>; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbphy0 { - fsl,tx-d-cal = <88>; -}; +&iomuxc1 { + pinctrl_enet: enetgrp { + fsl,pins = < + MX8ULP_PAD_PTE15__ENET0_MDC 0x43 + MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 + MX8ULP_PAD_PTE17__ENET0_RXER 0x43 + MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 + MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 + MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 + MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 + MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 + MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 + >; + };

-&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_id>; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX8ULP_PAD_PTF14__LPUART5_TX 0x3 + MX8ULP_PAD_PTF15__LPUART5_RX 0x3 + >; + };

-&usbphy1 { - fsl,tx-d-cal = <88>; + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 + MX8ULP_PAD_PTD10__SDHC0_D0 0x43 + MX8ULP_PAD_PTD9__SDHC0_D1 0x43 + MX8ULP_PAD_PTD8__SDHC0_D2 0x43 + MX8ULP_PAD_PTD7__SDHC0_D3 0x43 + MX8ULP_PAD_PTD6__SDHC0_D4 0x43 + MX8ULP_PAD_PTD5__SDHC0_D5 0x43 + MX8ULP_PAD_PTD4__SDHC0_D6 0x43 + MX8ULP_PAD_PTD3__SDHC0_D7 0x43 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 + >; + }; }; diff --git a/arch/arm/dts/imx8ulp-pinfunc.h b/arch/arm/dts/imx8ulp-pinfunc.h index c21c3b644e..b204ac79b4 100644 --- a/arch/arm/dts/imx8ulp-pinfunc.h +++ b/arch/arm/dts/imx8ulp-pinfunc.h @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ /* - * Copyright 2020 NXP + * Copyright 2021 NXP */

#ifndef __DTS_IMX8ULP_PINFUNC_H diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi index d3b16bd2fe..06ce5f19aa 100644 --- a/arch/arm/dts/imx8ulp.dtsi +++ b/arch/arm/dts/imx8ulp.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2021 NXP */ @@ -6,6 +6,8 @@ #include <dt-bindings/clock/imx8ulp-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/imx8ulp-power.h> + #include "imx8ulp-pinfunc.h"

/ { @@ -14,49 +16,29 @@ #size-cells = <2>;

aliases { + ethernet0 = &fec; gpio0 = &gpiod; gpio1 = &gpioe; gpio2 = &gpiof; - serial0 = &lpuart5; mmc0 = &usdhc0; mmc1 = &usdhc1; mmc2 = &usdhc2; - spi0 = &flexspi0; - spi2 = &flexspi2; - ethernet0 = &fec; - i2c7 = &lpi2c7; - usbphy0 = &usbphy0; - usb0 = &usbotg0; - usbphy1 = &usbphy1; - usb1 = &usbotg1; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; };

- cpus: cpus { + cpus { #address-cells = <2>; #size-cells = <0>;

- idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010033>; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2700>; - wakeup-latency-us = <1500>; - }; - }; - - /* We have 1 clusters with 4 Cortex-A35 cores */ A35_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>; };

A35_1: cpu@1 { @@ -65,7 +47,6 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>; };

A35_L2: l2-cache0 { @@ -73,37 +54,6 @@ }; };

- a35_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <800000>; - clock-latency-ns = <150000>; - }; - - opp-744000000 { - opp-hz = /bits/ 64 <744000000>; - opp-microvolt = <900000>; - clock-latency-ns = <150000>; - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - s400_mu: mu@27020000 { - u-boot,dm-spl; - compatible = "fsl,imx8ulp-mu"; - reg = <0 0x27020000 0 0x10000>; - status = "okay"; - }; - gic: interrupt-controller@2d400000 { compatible = "arm,gic-v3"; reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ @@ -113,6 +63,14 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; };

+ pmu { + compatible = "arm,cortex-a35-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-affinity = <&A35_0>, <&A35_1>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -154,7 +112,7 @@ #clock-cells = <0>; };

- sram@0x2201f000 { + sram@2201f000 { compatible = "mmio-sram"; reg = <0x0 0x2201f000 0x0 0x1000>;

@@ -162,10 +120,9 @@ #size-cells = <1>; ranges = <0 0x0 0x2201f000 0x1000>;

- /* TODO: split or unify */ - scmi_pd: scmi_pd@0 { + scmi_buf: scmi-sram-section@0 { compatible = "arm,scmi-shmem"; - reg = <0x0 0x200>; + reg = <0x0 0x400>; }; };

@@ -175,41 +132,31 @@ arm,smc-id = <0xc20000fe>; #address-cells = <1>; #size-cells = <0>; - shmem = <&scmi_pd>; + shmem = <&scmi_buf>;

scmi_devpd: protocol@11 { reg = <0x11>; #power-domain-cells = <1>; };

- scmi_perf: protocol@13 { - reg = <0x13>; + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; }; }; };

- soc@0 { + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x80000000>; + ranges = <0x0 0x0 0x0 0x40000000>;

- per_bridge0: bus@28000000 { - compatible = "simple-bus"; - reg = <0x28000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flexspi0: flexspi@28039000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,imx8ulp-fspi"; - reg = <0x28039000 0x10000>, - <0x04000000 0x7ffffff>; - reg-names = "fspi_base", "fspi_mmap"; - status = "disabled"; - }; + s4muap: mailbox@27020000 { + compatible = "fsl,imx8ulp-mu-s4"; + reg = <0x27020000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; };

per_bridge3: bus@29000000 { @@ -219,110 +166,21 @@ #size-cells = <1>; ranges;

- edma1: dma-controller@29010000 { - compatible = "fsl,imx8ulp-edma"; - reg = <0x29010000 0x10000>, - <0x29020000 0x10000>, <0x29030000 0x10000>, - <0x29040000 0x10000>, <0x29050000 0x10000>, - <0x29060000 0x10000>, <0x29070000 0x10000>, - <0x29080000 0x10000>, <0x29090000 0x10000>, - <0x290a0000 0x10000>, <0x290b0000 0x10000>, - <0x290c0000 0x10000>, <0x290d0000 0x10000>, - <0x290e0000 0x10000>, <0x290f0000 0x10000>, - <0x29100000 0x10000>, <0x29110000 0x10000>, - <0x29120000 0x10000>, <0x29130000 0x10000>, - <0x29140000 0x10000>, <0x29150000 0x10000>, - <0x29160000 0x10000>, <0x29170000 0x10000>, - <0x29180000 0x10000>, <0x29190000 0x10000>, - <0x291a0000 0x10000>, <0x291b0000 0x10000>, - <0x291c0000 0x10000>, <0x291d0000 0x10000>, - <0x291e0000 0x10000>, <0x291f0000 0x10000>, - <0x29200000 0x10000>, <0x29210000 0x10000>; - #dma-cells = <3>; - dma-channels = <32>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx", - "edma1-chan2-tx", "edma1-chan3-tx", - "edma1-chan4-tx", "edma1-chan5-tx", - "edma1-chan6-tx", "edma1-chan7-tx", - "edma1-chan8-tx", "edma1-chan9-tx", - "edma1-chan10-tx", "edma1-chan11-tx", - "edma1-chan12-tx", "edma1-chan13-tx", - "edma1-chan14-tx", "edma1-chan15-tx", - "edma1-chan16-tx", "edma1-chan17-tx", - "edma1-chan18-tx", "edma1-chan19-tx", - "edma1-chan20-tx", "edma1-chan21-tx", - "edma1-chan22-tx", "edma1-chan23-tx", - "edma1-chan24-tx", "edma1-chan25-tx", - "edma1-chan26-tx", "edma1-chan27-tx", - "edma1-chan28-tx", "edma1-chan29-tx", - "edma1-chan30-tx", "edma1-chan31-tx"; - clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, - <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, - <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, - <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, - <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, - <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, - <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, - <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, - <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, - <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, - <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, - <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, - <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, - <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, - <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, - <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, - <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; - clock-names = "edma-mp-clk", - "edma1-chan0-clk", "edma1-chan1-clk", - "edma1-chan2-clk", "edma1-chan3-clk", - "edma1-chan4-clk", "edma1-chan5-clk", - "edma1-chan6-clk", "edma1-chan7-clk", - "edma1-chan8-clk", "edma1-chan9-clk", - "edma1-chan10-clk", "edma1-chan11-clk", - "edma1-chan12-clk", "edma1-chan13-clk", - "edma1-chan14-clk", "edma1-chan15-clk", - "edma1-chan16-clk", "edma1-chan17-clk", - "edma1-chan18-clk", "edma1-chan19-clk", - "edma1-chan20-clk", "edma1-chan21-clk", - "edma1-chan22-clk", "edma1-chan23-clk", - "edma1-chan24-clk", "edma1-chan25-clk", - "edma1-chan26-clk", "edma1-chan27-clk", - "edma1-chan28-clk", "edma1-chan29-clk", - "edma1-chan30-clk", "edma1-chan31-clk"; - status = "okay"; + mu: mailbox@29220000 { + compatible = "fsl,imx8ulp-mu"; + reg = <0x29220000 0x10000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu3: mailbox@29230000 { + compatible = "fsl,imx8ulp-mu"; + reg = <0x29230000 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_MU3_A>; + #mbox-cells = <2>; + status = "disabled"; };

wdog3: watchdog@292a0000 { @@ -331,15 +189,13 @@ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; - assigned-clocks-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; timeout-sec = <40>; };

cgc1: clock-controller@292c0000 { compatible = "fsl,imx8ulp-cgc1"; reg = <0x292c0000 0x10000>; - clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; - clock-names = "rosc", "sosc", "frosc", "lposc"; #clock-cells = <1>; };

@@ -347,6 +203,7 @@ compatible = "fsl,imx8ulp-pcc3"; reg = <0x292d0000 0x10000>; #clock-cells = <1>; + #reset-cells = <1>; };

tpm5: tpm@29340000 { @@ -356,6 +213,33 @@ clocks = <&pcc3 IMX8ULP_CLK_TPM5>, <&pcc3 IMX8ULP_CLK_TPM5>; clock-names = "ipg", "per"; + status = "disabled"; + }; + + lpi2c4: i2c@29370000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29370000 0x10000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, + <&pcc3 IMX8ULP_CLK_LPI2C4>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c5: i2c@29380000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29380000 0x10000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, + <&pcc3 IMX8ULP_CLK_LPI2C5>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + status = "disabled"; };

lpuart4: serial@29390000 { @@ -370,10 +254,41 @@ lpuart5: serial@293a0000 { compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x293a0000 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; clock-names = "ipg"; status = "disabled"; }; + + lpspi4: spi@293b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; + reg = <0x293b0000 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, + <&pcc3 IMX8ULP_CLK_LPSPI4>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpspi5: spi@293c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; + reg = <0x293c0000 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, + <&pcc3 IMX8ULP_CLK_LPSPI5>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; };

per_bridge4: bus@29800000 { @@ -387,77 +302,84 @@ compatible = "fsl,imx8ulp-pcc4"; reg = <0x29800000 0x10000>; #clock-cells = <1>; + #reset-cells = <1>; };

- lpi2c6: lpi2c6@29840000 { + lpi2c6: i2c@29840000 { compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x29840000 0x10000>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, <&pcc4 IMX8ULP_CLK_LPI2C6>; clock-names = "per", "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; status = "disabled"; };

- lpi2c7: lpi2c7@29850000 { + lpi2c7: i2c@29850000 { compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x29850000 0x10000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, <&pcc4 IMX8ULP_CLK_LPI2C7>; clock-names = "per", "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; status = "disabled"; };

- flexspi2: flexspi@29810000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,imx8ulp-fspi"; - reg = <0x29810000 0x10000>, - <0x60000000 0xfffffff>; - reg-names = "fspi_base", "fspi_mmap"; + lpuart6: serial@29860000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29860000 0x1000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; + clock-names = "ipg"; status = "disabled"; };

- flexspi2_nand: flexspi2_nand@29810000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8-fspi-nand"; - reg = <0x29810000 0x10000>, <0x60000000 0x10000000>; - reg-names = "FlexSPI", "FlexSPI-memory"; + lpuart7: serial@29870000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29870000 0x1000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; + clock-names = "ipg"; status = "disabled"; };

iomuxc1: pinctrl@298c0000 { compatible = "fsl,imx8ulp-iomuxc1"; reg = <0x298c0000 0x10000>; - fsl,mux_mask = <0xf00>; };

usdhc0: mmc@298d0000 { - compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc"; + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; reg = <0x298d0000 0x10000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cgc1 IMX8ULP_CLK_DUMMY>, - <&cgc1 IMX8ULP_CLK_DUMMY>, + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC0>; clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; };

usdhc1: mmc@298e0000 { - compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc"; + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; reg = <0x298e0000 0x10000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cgc1 IMX8ULP_CLK_DUMMY>, - <&cgc1 IMX8ULP_CLK_DUMMY>, + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -470,117 +392,50 @@ <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, <&pcc4 IMX8ULP_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC2>; - assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; - assigned-clock-rates = <396000000>, <396000000>; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; };

- usbotg0: usb@29900000 { - compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", - "fsl,imx27-usb"; - reg = <0x29900000 0x200>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc4 IMX8ULP_CLK_USB0>; - fsl,usbphy = <&usbphy0>; - fsl,usbmisc = <&usbmisc0 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x8>; - rx-burst-size-dword = <0x8>; - status = "disabled"; - }; - - usbmisc0: usbmisc@29900200 { - #index-cells = <1>; - compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x29900200 0x200>; - }; - - usbphy0: usbphy@29910000 { - compatible = "fsl,imx8ulp-usbphy", - "fsl,imx7ulp-usbphy", "fsl,imx23-usbphy"; - reg = <0x29910000 0x1000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>; - }; - - usbotg1: usb@29920000 { - compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", - "fsl,imx27-usb"; - reg = <0x29920000 0x200>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc4 IMX8ULP_CLK_USB1>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc1 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x8>; - rx-burst-size-dword = <0x8>; - status = "disabled"; - }; - - usbmisc1: usbmisc@29920200 { - #index-cells = <1>; - compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x29920200 0x200>; - }; - - usbphy1: usbphy@29930000 { - compatible = "fsl,imx8ulp-usbphy", - "fsl,imx7ulp-usbphy", "fsl,imx23-usbphy"; - reg = <0x29930000 0x1000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>; - }; - fec: ethernet@29950000 { - compatible = "fsl,imx8ulp-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x29950000 0x10000>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc4 IMX8ULP_CLK_ENET>, - <&pcc4 IMX8ULP_CLK_ENET>, - <&cgc1 IMX8ULP_CLK_ENETSTAMP_SEL>, - <&pcc4 IMX8ULP_CLK_ENET>, - <&pcc4 IMX8ULP_CLK_ENET>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; + interrupt-names = "int0"; + fsl,num-tx-queues = <1>; + fsl,num-rx-queues = <1>; status = "disabled"; }; - };

- gpioe: gpio@2d000000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x2d000080 0x1000 0x2d000040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, - <&pcc4 IMX8ULP_CLK_PCTLE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 32 24>; + gpioe: gpio@2d000080 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, + <&pcc4 IMX8ULP_CLK_PCTLE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 32 24>; };

- gpiof: gpio@2d010000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x2d010080 0x1000 0x2d010040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, - <&pcc4 IMX8ULP_CLK_PCTLF>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 64 24>; + gpiof: gpio@2d010080 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, + <&pcc4 IMX8ULP_CLK_PCTLF>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 64 32>; };

per_bridge5: bus@2d800000 { @@ -590,117 +445,9 @@ #size-cells = <1>; ranges;

- edma2: dma-controller@2d800000 { - compatible = "fsl,imx8ulp-edma"; - reg = <0x2d800000 0x10000>, - <0x2d810000 0x10000>, <0x2d820000 0x10000>, - <0x2d830000 0x10000>, <0x2d840000 0x10000>, - <0x2d850000 0x10000>, <0x2d860000 0x10000>, - <0x2d870000 0x10000>, <0x2d880000 0x10000>, - <0x2d890000 0x10000>, <0x2d8a0000 0x10000>, - <0x2d8b0000 0x10000>, <0x2d8c0000 0x10000>, - <0x2d8d0000 0x10000>, <0x2d8e0000 0x10000>, - <0x2d8f0000 0x10000>, <0x2d900000 0x10000>, - <0x2d910000 0x10000>, <0x2d920000 0x10000>, - <0x2d930000 0x10000>, <0x2d940000 0x10000>, - <0x2d950000 0x10000>, <0x2d960000 0x10000>, - <0x2d970000 0x10000>, <0x2d980000 0x10000>, - <0x2d990000 0x10000>, <0x2d9a0000 0x10000>, - <0x2d9b0000 0x10000>, <0x2d9c0000 0x10000>, - <0x2d9d0000 0x10000>, <0x2d9e0000 0x10000>, - <0x2d9f0000 0x10000>, <0x2da00000 0x10000>; - #dma-cells = <3>; - dma-channels = <32>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx", - "edma2-chan2-tx", "edma2-chan3-tx", - "edma2-chan4-tx", "edma2-chan5-tx", - "edma2-chan6-tx", "edma2-chan7-tx", - "edma2-chan8-tx", "edma2-chan9-tx", - "edma2-chan10-tx", "edma2-chan11-tx", - "edma2-chan12-tx", "edma2-chan13-tx", - "edma2-chan14-tx", "edma2-chan15-tx", - "edma2-chan16-tx", "edma2-chan17-tx", - "edma2-chan18-tx", "edma2-chan19-tx", - "edma2-chan20-tx", "edma2-chan21-tx", - "edma2-chan22-tx", "edma2-chan23-tx", - "edma2-chan24-tx", "edma2-chan25-tx", - "edma2-chan26-tx", "edma2-chan27-tx", - "edma2-chan28-tx", "edma2-chan29-tx", - "edma2-chan30-tx", "edma2-chan31-tx"; - clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, - <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, - <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, - <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, - <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, - <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, - <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, - <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, - <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, - <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, - <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, - <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, - <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, - <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, - <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, - <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, - <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; - clock-names = "edma-mp-clk", - "edma2-chan0-clk", "edma2-chan1-clk", - "edma2-chan2-clk", "edma2-chan3-clk", - "edma2-chan4-clk", "edma2-chan5-clk", - "edma2-chan6-clk", "edma2-chan7-clk", - "edma2-chan8-clk", "edma2-chan9-clk", - "edma2-chan10-clk", "edma2-chan11-clk", - "edma2-chan12-clk", "edma2-chan13-clk", - "edma2-chan14-clk", "edma2-chan15-clk", - "edma2-chan16-clk", "edma2-chan17-clk", - "edma2-chan18-clk", "edma2-chan19-clk", - "edma2-chan20-clk", "edma2-chan21-clk", - "edma2-chan22-clk", "edma2-chan23-clk", - "edma2-chan24-clk", "edma2-chan25-clk", - "edma2-chan26-clk", "edma2-chan27-clk", - "edma2-chan28-clk", "edma2-chan29-clk", - "edma2-chan30-clk", "edma2-chan31-clk"; - status = "okay"; - }; - cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>; - clocks = <&sosc>, <&frosc>; - clock-names = "sosc", "frosc"; #clock-cells = <1>; };

@@ -708,12 +455,13 @@ compatible = "fsl,imx8ulp-pcc5"; reg = <0x2da70000 0x10000>; #clock-cells = <1>; + #reset-cells = <1>; }; };

- gpiod: gpio@2e200000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x2e200080 0x1000 0x2e200040 0x40>; + gpiod: gpio@2e200080 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; gpio-controller; #gpio-cells = <2>; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h index 49166a1830..953ecfe8eb 100644 --- a/include/dt-bindings/clock/imx8ulp-clock.h +++ b/include/dt-bindings/clock/imx8ulp-clock.h @@ -1,16 +1,14 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ /* - * Copyright 2020 NXP + * Copyright 2021 NXP */

#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H #define __DT_BINDINGS_CLOCK_IMX8ULP_H

#define IMX8ULP_CLK_DUMMY 0 -#define IMX8ULP_CLK_ROSC 1 -#define IMX8ULP_CLK_FROSC 2 -#define IMX8ULP_CLK_LPOSC 3 -#define IMX8ULP_CLK_SOSC 4 + +/* CGC1 */ #define IMX8ULP_CLK_SPLL2 5 #define IMX8ULP_CLK_SPLL3 6 #define IMX8ULP_CLK_A35_SEL 7 @@ -57,14 +55,15 @@ #define IMX8ULP_CLK_FROSC_DIV1_GATE 48 #define IMX8ULP_CLK_FROSC_DIV2_GATE 49 #define IMX8ULP_CLK_FROSC_DIV3_GATE 50 -#define IMX8ULP_CLK_ENETSTAMP_SEL 51 -#define IMX8ULP_CLK_SAI4_SEL 52 -#define IMX8ULP_CLK_SAI5_SEL 53 -#define IMX8ULP_CLK_AUD_CLK1 54 -#define IMX8ULP_CLK_ARM 55 +#define IMX8ULP_CLK_SAI4_SEL 51 +#define IMX8ULP_CLK_SAI5_SEL 52 +#define IMX8ULP_CLK_AUD_CLK1 53 +#define IMX8ULP_CLK_ARM 54 +#define IMX8ULP_CLK_ENET_TS_SEL 55

#define IMX8ULP_CLK_CGC1_END 56

+/* CGC2 */ #define IMX8ULP_CLK_PLL4_PRE_SEL 0 #define IMX8ULP_CLK_PLL4 1 #define IMX8ULP_CLK_PLL4_VCODIV 2 @@ -110,8 +109,12 @@ #define IMX8ULP_CLK_SAI6_SEL 42 #define IMX8ULP_CLK_SAI7_SEL 43 #define IMX8ULP_CLK_SPDIF_SEL 44 +#define IMX8ULP_CLK_HIFI_SEL 45 +#define IMX8ULP_CLK_HIFI_DIVCORE 46 +#define IMX8ULP_CLK_HIFI_DIVPLAT 47 +#define IMX8ULP_CLK_DSI_PHY_REF 48

-#define IMX8ULP_CLK_CGC2_END 45 +#define IMX8ULP_CLK_CGC2_END 49

/* PCC3 */ #define IMX8ULP_CLK_WDOG3 0 @@ -160,9 +163,12 @@ #define IMX8ULP_CLK_DMA1_CH29 43 #define IMX8ULP_CLK_DMA1_CH30 44 #define IMX8ULP_CLK_DMA1_CH31 45 +#define IMX8ULP_CLK_MU3_A 46 +#define IMX8ULP_CLK_MU0_B 47

-#define IMX8ULP_CLK_PCC3_END 46 +#define IMX8ULP_CLK_PCC3_END 48

+/* PCC4 */ #define IMX8ULP_CLK_FLEXSPI2 0 #define IMX8ULP_CLK_TPM6 1 #define IMX8ULP_CLK_TPM7 2 @@ -189,24 +195,25 @@

#define IMX8ULP_CLK_PCC4_END 23

+/* PCC5 */ #define IMX8ULP_CLK_TPM8 0 #define IMX8ULP_CLK_SAI6 1 #define IMX8ULP_CLK_SAI7 2 #define IMX8ULP_CLK_SPDIF 3 -#define IMX8ULP_CLK_ISI 4 -#define IMX8ULP_CLK_CSI_REGS 5 +#define IMX8ULP_CLK_ISI 4 +#define IMX8ULP_CLK_CSI_REGS 5 #define IMX8ULP_CLK_PCTLD 6 -#define IMX8ULP_CLK_CSI 7 -#define IMX8ULP_CLK_DSI 8 +#define IMX8ULP_CLK_CSI 7 +#define IMX8ULP_CLK_DSI 8 #define IMX8ULP_CLK_WDOG5 9 #define IMX8ULP_CLK_EPDC 10 -#define IMX8ULP_CLK_PXP 11 +#define IMX8ULP_CLK_PXP 11 #define IMX8ULP_CLK_SFA2 12 #define IMX8ULP_CLK_GPU2D 13 #define IMX8ULP_CLK_GPU3D 14 #define IMX8ULP_CLK_DC_NANO 15 -#define IMX8ULP_CLK_CSI_CLK_UI 16 -#define IMX8ULP_CLK_CSI_CLK_ESC 17 +#define IMX8ULP_CLK_CSI_CLK_UI 16 +#define IMX8ULP_CLK_CSI_CLK_ESC 17 #define IMX8ULP_CLK_RGPIOD 18 #define IMX8ULP_CLK_DMA2_MP 19 #define IMX8ULP_CLK_DMA2_CH0 20 @@ -241,7 +248,11 @@ #define IMX8ULP_CLK_DMA2_CH29 49 #define IMX8ULP_CLK_DMA2_CH30 50 #define IMX8ULP_CLK_DMA2_CH31 51 +#define IMX8ULP_CLK_MU2_B 52 +#define IMX8ULP_CLK_MU3_B 53 +#define IMX8ULP_CLK_AVD_SIM 54 +#define IMX8ULP_CLK_DSI_TX_ESC 55

-#define IMX8ULP_CLK_PCC5_END 52 +#define IMX8ULP_CLK_PCC5_END 56

#endif diff --git a/include/dt-bindings/power/imx8ulp-power.h b/include/dt-bindings/power/imx8ulp-power.h new file mode 100644 index 0000000000..a556b2e96d --- /dev/null +++ b/include/dt-bindings/power/imx8ulp-power.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DT_BINDINGS_IMX8ULP_POWER_H__ +#define __DT_BINDINGS_IMX8ULP_POWER_H__ + +#define IMX8ULP_PD_DMA1 0 +#define IMX8ULP_PD_FLEXSPI2 1 +#define IMX8ULP_PD_USB0 2 +#define IMX8ULP_PD_USDHC0 3 +#define IMX8ULP_PD_USDHC1 4 +#define IMX8ULP_PD_USDHC2_USB1 5 +#define IMX8ULP_PD_DCNANO 6 +#define IMX8ULP_PD_EPDC 7 +#define IMX8ULP_PD_DMA2 8 +#define IMX8ULP_PD_GPU2D 9 +#define IMX8ULP_PD_GPU3D 10 +#define IMX8ULP_PD_HIFI4 11 +#define IMX8ULP_PD_ISI 12 +#define IMX8ULP_PD_MIPI_CSI 13 +#define IMX8ULP_PD_MIPI_DSI 14 +#define IMX8ULP_PD_PXP 15 + +#endif diff --git a/include/dt-bindings/reset/imx8ulp-pcc-reset.h b/include/dt-bindings/reset/imx8ulp-pcc-reset.h new file mode 100644 index 0000000000..e99a4735c3 --- /dev/null +++ b/include/dt-bindings/reset/imx8ulp-pcc-reset.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2021 NXP + */ + +#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H +#define DT_BINDING_PCC_RESET_IMX8ULP_H + +/* PCC3 */ +#define PCC3_WDOG3_SWRST 0 +#define PCC3_WDOG4_SWRST 1 +#define PCC3_LPIT1_SWRST 2 +#define PCC3_TPM4_SWRST 3 +#define PCC3_TPM5_SWRST 4 +#define PCC3_FLEXIO1_SWRST 5 +#define PCC3_I3C2_SWRST 6 +#define PCC3_LPI2C4_SWRST 7 +#define PCC3_LPI2C5_SWRST 8 +#define PCC3_LPUART4_SWRST 9 +#define PCC3_LPUART5_SWRST 10 +#define PCC3_LPSPI4_SWRST 11 +#define PCC3_LPSPI5_SWRST 12 + +/* PCC4 */ +#define PCC4_FLEXSPI2_SWRST 0 +#define PCC4_TPM6_SWRST 1 +#define PCC4_TPM7_SWRST 2 +#define PCC4_LPI2C6_SWRST 3 +#define PCC4_LPI2C7_SWRST 4 +#define PCC4_LPUART6_SWRST 5 +#define PCC4_LPUART7_SWRST 6 +#define PCC4_SAI4_SWRST 7 +#define PCC4_SAI5_SWRST 8 +#define PCC4_USDHC0_SWRST 9 +#define PCC4_USDHC1_SWRST 10 +#define PCC4_USDHC2_SWRST 11 +#define PCC4_USB0_SWRST 12 +#define PCC4_USB0_PHY_SWRST 13 +#define PCC4_USB1_SWRST 14 +#define PCC4_USB1_PHY_SWRST 15 +#define PCC4_ENET_SWRST 16 + +/* PCC5 */ +#define PCC5_TPM8_SWRST 0 +#define PCC5_SAI6_SWRST 1 +#define PCC5_SAI7_SWRST 2 +#define PCC5_SPDIF_SWRST 3 +#define PCC5_ISI_SWRST 4 +#define PCC5_CSI_REGS_SWRST 5 +#define PCC5_CSI_SWRST 6 +#define PCC5_DSI_SWRST 7 +#define PCC5_WDOG5_SWRST 8 +#define PCC5_EPDC_SWRST 9 +#define PCC5_PXP_SWRST 10 +#define PCC5_GPU2D_SWRST 11 +#define PCC5_GPU3D_SWRST 12 +#define PCC5_DC_NANO_SWRST 13 + +#endif /*DT_BINDING_RESET_IMX8ULP_H */

From: Marcel Ziswiler marcel.ziswiler@toradex.com

Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com

---

(no changes since v4)

Changes in v4: - Re-synched with v6.1-rc3.

arch/arm/dts/imx8mq-evk.dts | 43 +++++++ arch/arm/dts/imx8mq-librem5-r3.dtsi | 45 +++++++ arch/arm/dts/imx8mq-librem5-r4.dts | 20 +-- arch/arm/dts/imx8mq-librem5.dtsi | 153 +++++++++++++++++++++-- arch/arm/dts/imx8mq-u-boot.dtsi | 10 +- arch/arm/dts/imx8mq.dtsi | 19 +-- include/dt-bindings/reset/imx8mq-reset.h | 61 ++++----- 7 files changed, 281 insertions(+), 70 deletions(-) create mode 100644 arch/arm/dts/imx8mq-librem5-r3.dtsi

diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts index 99fed35168..82387b9cb8 100644 --- a/arch/arm/dts/imx8mq-evk.dts +++ b/arch/arm/dts/imx8mq-evk.dts @@ -71,12 +71,36 @@ linux,autosuspend-period = <125>; };

+ audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; };

+ sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai3>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -386,6 +410,16 @@ status = "okay"; };

+&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -548,6 +582,15 @@ >; };

+ pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + pinctrl_spdif1: spdif1grp { fsl,pins = < MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 diff --git a/arch/arm/dts/imx8mq-librem5-r3.dtsi b/arch/arm/dts/imx8mq-librem5-r3.dtsi new file mode 100644 index 0000000000..e4f8b47cce --- /dev/null +++ b/arch/arm/dts/imx8mq-librem5-r3.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2021 Purism SPC kernel@puri.sm + +/dts-v1/; + +/* + * This file describes hardware that is shared among r3 ("Dogwood") and + * later revisions of the Librem 5 so it has to be included in dts there. + */ + +#include "imx8mq-librem5.dtsi" + +/ { + model = "Purism Librem 5r3"; + compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; +}; + +&accel_gyro { + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; +}; + +&bq25895 { + ti,battery-regulation-voltage = <4200000>; /* uV */ + ti,charge-current = <1500000>; /* uA */ + ti,termination-current = <144000>; /* uA */ +}; + +&camera_front { + pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>; + shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_r3_camera_pwr: r3camerapwrgrp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83 + >; + }; +}; + +&proximity { + proximity-near-level = <25>; +}; diff --git a/arch/arm/dts/imx8mq-librem5-r4.dts b/arch/arm/dts/imx8mq-librem5-r4.dts index cbfb49aa25..1056b7981b 100644 --- a/arch/arm/dts/imx8mq-librem5-r4.dts +++ b/arch/arm/dts/imx8mq-librem5-r4.dts @@ -1,35 +1,27 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Purism SPC kernel@puri.sm +// Copyright (C) 2021 Purism SPC kernel@puri.sm

/dts-v1/;

-#include "imx8mq-librem5.dtsi" +#include "imx8mq-librem5-r3.dtsi"

/ { model = "Purism Librem 5r4"; compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq"; };

-&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - &bat { maxim,rsns-microohm = <1667>; };

-&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - &led_backlight { led-max-microamp = <25000>; };

+&lcd_panel { + compatible = "ys,ys57pss36bh5gq"; +}; + &proximity { proximity-near-level = <10>; }; diff --git a/arch/arm/dts/imx8mq-librem5.dtsi b/arch/arm/dts/imx8mq-librem5.dtsi index 60d47c7149..ae08556b2e 100644 --- a/arch/arm/dts/imx8mq-librem5.dtsi +++ b/arch/arm/dts/imx8mq-librem5.dtsi @@ -7,6 +7,7 @@

#include "dt-bindings/input/input.h" #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/usb/pd.h" #include "imx8mq.dtsi" @@ -14,6 +15,7 @@ / { model = "Purism Librem 5"; compatible = "purism,librem5", "fsl,imx8mq"; + chassis-type = "handset";

backlight_dsi: backlight-dsi { compatible = "led-backlight"; @@ -36,18 +38,45 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_keys>;

- vol-down { + key-vol-down { label = "VOL_DOWN"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <50>; + wakeup-source; };

- vol-up { + key-vol-up { label = "VOL_UP"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; debounce-interval = <50>; + wakeup-source; + }; + }; + + led-controller { + compatible = "pwm-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + max-brightness = <248>; + pwms = <&pwm2 0 50000 0>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + max-brightness = <248>; + pwms = <&pwm4 0 50000 0>; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + max-brightness = <248>; + pwms = <&pwm3 0 50000 0>; }; };

@@ -62,6 +91,40 @@ enable-active-high; };

+ /* + * the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC + * since we can't have it twice in the 2 different regulator nodes. + */ + reg_csi_1v8: regulator-csi-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&reg_vdd_3v3>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* controlled by the CAMERA_POWER_KEY HKS */ + reg_vcam_1v2: regulator-vcam-1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&reg_vdd_1v8>; + enable-active-high; + }; + + reg_vcam_2v8: regulator-vcam-2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDA_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&reg_vdd_3v3>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_gnss: regulator-gnss { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -237,8 +300,13 @@ cpu-supply = <&buck2_reg>; };

+&csi1 { + status = "okay"; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; + status = "okay";

ddrc_opp_table: opp-table { compatible = "operating-points-v2"; @@ -283,15 +351,10 @@ };

partition@30000 { - label = "protected1"; - reg = <0x30000 0x10000>; + label = "firmware"; + reg = <0x30000 0x1d0000>; read-only; }; - - partition@40000 { - label = "rw"; - reg = <0x40000 0x1C0000>; - }; }; };

@@ -329,12 +392,24 @@ >; };

+ pinctrl_camera_pwr: camerapwrgrp { + fsl,pins = < + /* CAMERA_PWR_EN_3V3 */ + MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x83 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + /* CSI1_NRST */ + MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x83 + >; + }; + pinctrl_charger_in: chargeringrp { fsl,pins = < /* CHRG_INT */ MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80 - /* CHG_STATUS_B */ - MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 >; };

@@ -698,6 +773,10 @@ interrupt-names = "irq";

connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -725,7 +804,7 @@ compatible = "rohm,bd71837"; reg = <0x4b>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; + pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>; clocks = <&pmic_osc>; clock-names = "osc"; clock-output-names = "pmic_clk"; @@ -958,6 +1037,31 @@ >; };

+ camera_front: camera@20 { + compatible = "hynix,hi846"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-rates = <25000000>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + vdda-supply = <&reg_vcam_2v8>; + vddd-supply = <&reg_vcam_1v2>; + vddio-supply = <&reg_csi_1v8>; + rotation = <90>; + orientation = <0>; + + port { + camera1_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 + <80000000 200000000 300000000>; + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; + backlight@36 { compatible = "ti,lm36922"; reg = <0x36>; @@ -996,6 +1100,12 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay";

+ vcm@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + vcc-supply = <&reg_csi_1v8>; + }; + bat: fuel-gauge@36 { compatible = "maxim,max17055"; reg = <0x36>; @@ -1003,6 +1113,7 @@ interrupts = <20 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gauge>; + power-supplies = <&bq25895>; maxim,over-heat-temp = <700>; maxim,over-volt = <4500>; maxim,rsns-microohm = <5000>; @@ -1019,7 +1130,7 @@ ti,precharge-current = <130000>; /* uA */ ti,minimum-sys-voltage = <3700000>; /* uV */ ti,boost-voltage = <5000000>; /* uV */ - ti,boost-max-current = <500000>; /* uA */ + ti,boost-max-current = <1500000>; /* uA */ ti,use-vinmin-threshold = <1>; /* enable VINDPM */ ti,vinmin-threshold = <3900000>; /* uV */ monitored-battery = <&bat>; @@ -1031,6 +1142,21 @@ status = "okay"; };

+&mipi_csi1 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + + mipi1_sensor_ep: endpoint { + remote-endpoint = <&camera1_ep>; + data-lanes = <1 2>; + }; + }; + }; +}; + &mipi_dsi { #address-cells = <1>; #size-cells = <0>; @@ -1174,6 +1300,7 @@ #size-cells = <0>; dr_mode = "otg"; snps,dis_u3_susphy_quirk; + usb-role-switch; status = "okay";

port@0 { diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index c69c6cc58b..8d385e8da4 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -10,23 +10,23 @@

};

-&{/soc@0} { +&soc { u-boot,dm-spl; };

-&{/soc@0/bus@30000000} { +&aips1 { u-boot,dm-spl; };

-&{/soc@0/bus@30400000} { +&aips2 { u-boot,dm-spl; };

-&{/soc@0/bus@30800000} { +&aips3 { u-boot,dm-spl; };

-&{/soc@0/bus@32c00000} { +&aips4 { u-boot,dm-spl; };

diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index 49eadb081b..19eaa52356 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -94,7 +94,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; };

@@ -320,7 +320,7 @@ arm,no-tick-in-suspend; };

- soc@0 { + soc: soc@0 { compatible = "fsl,imx8mq-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -329,7 +329,7 @@ nvmem-cells = <&imx8mq_uid>; nvmem-cell-names = "soc_unique_id";

- bus@30000000 { /* AIPS1 */ + aips1: bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; #address-cells = <1>; @@ -507,7 +507,7 @@ <0x00030005 0x00000053>, <0x00030006 0x0000005f>, <0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; + #thermal-sensor-cells = <1>; };

wdog1: watchdog@30280000 { @@ -534,7 +534,7 @@ status = "disabled"; };

- sdma2: sdma@302c0000 { + sdma2: dma-controller@302c0000 { compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; reg = <0x302c0000 0x10000>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; @@ -784,7 +784,7 @@ }; };

- bus@30400000 { /* AIPS2 */ + aips2: bus@30400000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30400000 0x400000>; #address-cells = <1>; @@ -844,7 +844,7 @@ }; };

- bus@30800000 { /* AIPS3 */ + aips3: bus@30800000 { /* AIPS3 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30800000 0x400000>; #address-cells = <1>; @@ -1018,6 +1018,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; };

sec_jr1: jr@2000 { @@ -1301,7 +1302,7 @@ status = "disabled"; };

- sdma1: sdma@30bd0000 { + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; reg = <0x30bd0000 0x10000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -1369,7 +1370,7 @@ }; };

- bus@32c00000 { /* AIPS4 */ + aips4: bus@32c00000 { /* AIPS4 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; #address-cells = <1>; diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h index 9a301082d3..705870693e 100755 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ b/include/dt-bindings/reset/imx8mq-reset.h @@ -28,37 +28,40 @@ #define IMX8MQ_RESET_A53_L2RESET 17 #define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 #define IMX8MQ_RESET_OTG1_PHY_RESET 19 -#define IMX8MQ_RESET_OTG2_PHY_RESET 20 -#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 -#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 -#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 -#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 -#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 -#define IMX8MQ_RESET_PCIEPHY 26 -#define IMX8MQ_RESET_PCIEPHY_PERST 27 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 -#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ #define IMX8MQ_RESET_DISP_RESET 31 #define IMX8MQ_RESET_GPU_RESET 32 -#define IMX8MQ_RESET_VPU_RESET 33 -#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC1_PRST 44 -#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 -#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 -#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_SW_M4C_RST 50 +#define IMX8MQ_RESET_SW_M4P_RST 51 +#define IMX8MQ_RESET_M4_ENABLE 52

-#define IMX8MQ_RESET_NUM 50 +#define IMX8MQ_RESET_NUM 53

#endif

From: Marcel Ziswiler marcel.ziswiler@toradex.com

Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com Tested-By: Tim Harvey tharvey@gateworks.com #imx8m{m,n,p}-venice-*

---

Changes in v5: - Add Tim's tested-by. Thanks!

Changes in v4: - Re-synched with v6.1-rc3.

arch/arm/dts/imx8mp-dhcom-pdk2.dts | 29 +- arch/arm/dts/imx8mp-dhcom-som.dtsi | 20 +- arch/arm/dts/imx8mp-evk.dts | 179 +++++++---- arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts | 2 +- arch/arm/dts/imx8mp-icore-mx8mp.dtsi | 2 +- arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 48 +-- arch/arm/dts/imx8mp-u-boot.dtsi | 2 +- arch/arm/dts/imx8mp-venice-gw74xx.dts | 284 +++++++++++++----- arch/arm/dts/imx8mp-verdin.dtsi | 32 +- arch/arm/dts/imx8mp.dtsi | 147 ++++++++- include/dt-bindings/clock/imx8mp-clock.h | 13 +- include/dt-bindings/interconnect/fsl,imx8mp.h | 59 ++++ include/dt-bindings/power/imx8mp-power.h | 21 +- include/dt-bindings/reset/imx8mp-reset.h | 50 +++ 14 files changed, 683 insertions(+), 205 deletions(-) create mode 100644 include/dt-bindings/interconnect/fsl,imx8mp.h create mode 100644 include/dt-bindings/reset/imx8mp-reset.h

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts b/arch/arm/dts/imx8mp-dhcom-pdk2.dts index c9a481ac9a..382fbedaf6 100644 --- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts +++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts @@ -17,14 +17,13 @@ / { model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)"; compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som", - "fsl,imx8mp"; + "fsl,imx8mp";

chosen { stdout-path = &uart1; };

gpio-keys { - #size-cells = <0>; compatible = "gpio-keys";

button-0 { @@ -67,7 +66,7 @@ led { compatible = "gpio-leds";

- led-5 { + led-0 { color = <LED_COLOR_ID_GREEN>; default-state = "off"; function = LED_FUNCTION_INDICATOR; @@ -76,7 +75,7 @@ pinctrl-names = "default"; };

- led-6 { + led-1 { color = <LED_COLOR_ID_GREEN>; default-state = "off"; function = LED_FUNCTION_INDICATOR; @@ -85,7 +84,7 @@ pinctrl-names = "default"; };

- led-7 { + led-2 { color = <LED_COLOR_ID_GREEN>; default-state = "off"; function = LED_FUNCTION_INDICATOR; @@ -94,7 +93,7 @@ pinctrl-names = "default"; };

- led-8 { + led-3 { color = <LED_COLOR_ID_GREEN>; default-state = "off"; function = LED_FUNCTION_INDICATOR; @@ -123,10 +122,11 @@ mdio { ethphypdk: ethernet-phy@7 { /* KSZ 9021 */ compatible = "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio4>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy1>; pinctrl-names = "default"; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + max-speed = <100>; reg = <7>; reset-assert-us = <1000>; reset-deassert-us = <1000>; @@ -143,7 +143,6 @@ txd2-skew-ps = <0>; txd3-skew-ps = <0>; txen-skew-ps = <0>; - max-speed = <100>; }; }; }; @@ -155,3 +154,15 @@ &usb3_1 { fsl,over-current-active-low; }; + +&iomuxc { + /* + * GPIO_A,B,C,D are connected to buttons. + * GPIO_E,F,H,I are connected to LEDs. + * GPIO_M is connected to CLKOUT2. + */ + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_g &pinctrl_dhcom_j + &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_int>; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi index 197840d1a6..0f13ee3627 100644 --- a/arch/arm/dts/imx8mp-dhcom-som.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2021-2022 Marek Vasut marex@denx.de */ @@ -224,10 +224,6 @@ };

&i2c3 { - /* - * iMX8MP 1P33A Errata ERR007805 - * I2C is limited to 384 kHz due to SoC bug. - */ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; @@ -393,10 +389,6 @@ };

&i2c4 { - /* - * iMX8MP 1P33A Errata ERR007805 - * I2C is limited to 384 kHz due to SoC bug. - */ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; @@ -407,10 +399,6 @@ };

&i2c5 { /* HDMI EDID bus */ - /* - * iMX8MP 1P33A Errata ERR007805 - * I2C is limited to 384 kHz due to SoC bug. - */ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c5>; @@ -802,8 +790,8 @@

pinctrl_i2c5: dhcom-i2c5-grp { fsl,pins = < - MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x40000084 - MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x40000084 + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 >; };

@@ -830,7 +818,7 @@ pinctrl_rtc: dhcom-rtc-grp { fsl,pins = < /* RTC_#INT Interrupt */ - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6 + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080 >; };

diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts index 4c3ac4214a..9f1469db55 100644 --- a/arch/arm/dts/imx8mp-evk.dts +++ b/arch/arm/dts/imx8mp-evk.dts @@ -5,6 +5,7 @@

/dts-v1/;

+#include <dt-bindings/phy/phy-imx8-pcie.h> #include "imx8mp.dtsi"

/ { @@ -33,6 +34,12 @@ <0x1 0x00000000 0 0xc0000000>; };

+ pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_can1_stby: regulator-can1-stby { compatible = "regulator-fixed"; regulator-name = "can1-stby"; @@ -55,6 +62,17 @@ enable-active-high; };

+ reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -67,18 +85,20 @@ }; };

-&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <&reg_can1_stby>; - status = "okay"; +&A53_0 { + cpu-supply = <&reg_arm>; };

-&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <&reg_can2_stby>; - status = "disabled";/* can2 pin conflict with pdm */ +&A53_1 { + cpu-supply = <&reg_arm>; +}; + +&A53_2 { + cpu-supply = <&reg_arm>; +}; + +&A53_3 { + cpu-supply = <&reg_arm>; };

&eqos { @@ -197,6 +217,20 @@ }; };

+&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <&reg_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <&reg_can2_stby>; + status = "disabled";/* can2 pin conflict with pdm */ +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -221,7 +255,7 @@ regulator-ramp-delay = <3125>; };

- BUCK2 { + reg_arm: BUCK2 { regulator-name = "BUCK2"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1025000>; @@ -334,6 +368,28 @@ */ };

+&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + vpcie-supply = <&reg_pcie0>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -395,41 +451,41 @@ &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 >; };

pinctrl_fec: fecgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f - MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 >; };

@@ -461,28 +517,41 @@

pinctrl_gpio_led: gpioledgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 >; };

pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 >; };

pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 >; };

pinctrl_i2c5: i2c5grp { fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3 - MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 + >; + }; + + pinctrl_pcie0_reg: pcie0reggrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 >; };

@@ -500,20 +569,20 @@

pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; };

pinctrl_uart2: uart2grp { fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 >; };

pinctrl_usb1_vbus: usb1grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19 + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 >; };

@@ -525,7 +594,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; };

@@ -537,7 +606,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; };

@@ -549,7 +618,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; };

diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts index dd703b6a5e..a02b31c42d 100644 --- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts +++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts @@ -2,7 +2,7 @@ /* * Copyright (c) 2018 NXP * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */

/dts-v1/; diff --git a/arch/arm/dts/imx8mp-icore-mx8mp.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp.dtsi index 5116079cce..a6319824ea 100644 --- a/arch/arm/dts/imx8mp-icore-mx8mp.dtsi +++ b/arch/arm/dts/imx8mp-icore-mx8mp.dtsi @@ -2,7 +2,7 @@ /* * Copyright (c) 2018 NXP * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */

/ { diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts index 984a6b9ded..6aa720bafe 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts @@ -116,48 +116,48 @@ &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 >; };

pinctrl_i2c2: i2c2grp { fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 >; };

pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3 - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3 + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 >; };

pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; };

pinctrl_uart1: uart1grp { fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 >; };

@@ -175,7 +175,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; };

@@ -187,7 +187,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; };

@@ -199,7 +199,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; }; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index b5d640df7e..f9883aa133 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -10,7 +10,7 @@ }; };

-&{/soc@0} { +&soc { u-boot,dm-pre-reloc; u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts index 101d311476..06b4c93c58 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx.dts +++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts @@ -8,6 +8,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h>

#include "imx8mp.dtsi"

@@ -100,6 +101,12 @@ }; };

+ pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -123,8 +130,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_can>; regulator-name = "can2_stby"; - gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; - enable-active-high; + gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -135,13 +141,29 @@ compatible = "regulator-fixed"; regulator-name = "wl"; gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; + startup-delay-us = <70000>; enable-active-high; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; };

+&A53_0 { + cpu-supply = <&reg_arm>; +}; + +&A53_1 { + cpu-supply = <&reg_arm>; +}; + +&A53_2 { + cpu-supply = <&reg_arm>; +}; + +&A53_3 { + cpu-supply = <&reg_arm>; +}; + /* off-board header */ &ecspi2 { pinctrl-names = "default"; @@ -200,8 +222,8 @@ &gpio2 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", + "", "", "", "", "", "", "pcie3_wdis#", "", + "", "", "pcie2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", ""; };

@@ -362,7 +384,7 @@ regulator-ramp-delay = <3125>; };

- BUCK2 { + reg_arm: BUCK2 { regulator-name = "BUCK2"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1025000>; @@ -484,35 +506,40 @@ lan1: port@0 { reg = <0>; label = "lan1"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; };

lan2: port@1 { reg = <1>; label = "lan2"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; };

lan3: port@2 { reg = <2>; label = "lan3"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; };

lan4: port@3 { reg = <3>; label = "lan4"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; };

lan5: port@4 { reg = <4>; label = "lan5"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; };

- port@6 { - reg = <6>; + port@5 { + reg = <5>; label = "cpu"; ethernet = <&fec>; phy-mode = "rgmii-id"; @@ -542,6 +569,28 @@ status = "okay"; };

+&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + status = "okay"; +}; + /* GPS / off-board header */ &uart1 { pinctrl-names = "default"; @@ -556,6 +605,21 @@ status = "okay"; };

+/* bluetooth HCI */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; + cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -563,20 +627,35 @@ };

/* USB1 - Type C front panel */ -&usb3_phy0 { +&usb3_0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; + fsl,over-current-active-low; status = "okay"; };

-&usb3_0 { - fsl,over-current-active-low; +&usb3_phy0 { status = "okay"; };

&usb_dwc3_0 { - dr_mode = "host"; + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; status = "okay"; + + connector { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "Type-C"; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; };

/* USB2 - USB3.0 Hub */ @@ -596,6 +675,25 @@ status = "okay"; };

+/* SDIO WiFi */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + non-removable; + vmmc-supply = <&reg_wifi_en>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@0 { + compatible = "cypress,cyw4373-fmac"; + reg = <0>; + }; +}; + /* eMMC */ &usdhc3 { assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; @@ -622,15 +720,14 @@

pinctrl_hog: hoggrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */ - MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */ - MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */ - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */ - MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */ - MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */ - MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */ - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */ - MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */ + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */ + MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ + MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ + MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */ MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ @@ -639,47 +736,47 @@

pinctrl_accel: accelgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159 + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 >; };

pinctrl_eqos: eqosgrp { fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f - MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */ + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */ >; };

pinctrl_fec: fecgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f - MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141 - MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140 + MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140 >; };

@@ -692,61 +789,67 @@

pinctrl_gsc: gscgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159 + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150 >; };

pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 >; };

pinctrl_i2c2: i2c2grp { fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 >; };

pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 >; };

pinctrl_i2c4: i2c4grp { fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 >; };

pinctrl_ksz: kszgrp { fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */ - MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */ + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */ >; };

pinctrl_gpio_leds: ledgrp { fsl,pins = < - MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19 - MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19 + MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10 + MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 + >; + }; + + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110 >; };

pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141 + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 >; };

pinctrl_pps: ppsgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 >; };

@@ -758,22 +861,22 @@

pinctrl_reg_usb2: regusb2grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141 + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 >; };

pinctrl_reg_wifi: regwifigrp { fsl,pins = < - MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110 >; };

pinctrl_sai2: sai2grp { fsl,pins = < - MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC - MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 - MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK - MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 >; };

@@ -811,7 +914,7 @@

pinctrl_uart3_gpio: uart3gpiogrp { fsl,pins = < - MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119 + MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110 >; };

@@ -825,7 +928,12 @@ pinctrl_usb1: usb1grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 - MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140 + >; + }; + + pinctrl_usbcon1: usb1congrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; };

@@ -840,6 +948,28 @@ >; };

+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 diff --git a/arch/arm/dts/imx8mp-verdin.dtsi b/arch/arm/dts/imx8mp-verdin.dtsi index 68100a1726..7b712d1888 100644 --- a/arch/arm/dts/imx8mp-verdin.dtsi +++ b/arch/arm/dts/imx8mp-verdin.dtsi @@ -49,7 +49,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>;

- wakeup { + button-wakeup { debounce-interval = <10>; /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; @@ -146,6 +146,30 @@ }; };

+&A53_0 { + cpu-supply = <&reg_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <&reg_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <&reg_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <&reg_vdd_arm>; +}; + +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + /* Verdin SPI_1 */ &ecspi1 { #address-cells = <1>; @@ -445,7 +469,7 @@ regulator-ramp-delay = <3125>; };

- BUCK2 { + reg_vdd_arm: BUCK2 { nxp,dvs-run-voltage = <950000>; nxp,dvs-standby-voltage = <850000>; regulator-always-on; @@ -619,7 +643,7 @@ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; reg = <0x4a>; /* Verdin GPIO_2 (SODIMM 208) */ - reset-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; status = "disabled"; }; }; @@ -696,7 +720,7 @@ pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; reg = <0x4a>; /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ - reset-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; status = "disabled"; };

diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index d9542dfff8..bb916a0948 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -5,8 +5,10 @@

#include <dt-bindings/clock/imx8mp-clock.h> #include <dt-bindings/power/imx8mp-power.h> +#include <dt-bindings/reset/imx8mp-reset.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/interconnect/fsl,imx8mp.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h>

@@ -195,7 +197,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; };

@@ -293,7 +295,7 @@ arm,no-tick-in-suspend; };

- soc@0 { + soc: soc@0 { compatible = "fsl,imx8mp-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -469,6 +471,11 @@ wakeup-source; status = "disabled"; }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx8mp-snvs-lpgpr", + "fsl,imx7d-snvs-lpgpr"; + }; };

clk: clock-controller@30380000 { @@ -595,7 +602,34 @@ pgc_ispdwp: power-domain@18 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; - clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; + }; + + pgc_vpumix: power-domain@19 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; + clocks =<&clk IMX8MP_CLK_VPU_ROOT>; + }; + + pgc_vpu_g1: power-domain@20 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + }; + + pgc_vpu_g2: power-domain@21 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + }; + + pgc_vpu_vc8000e: power-domain@22 { + #power-domain-cells = <0>; + power-domains = <&pgc_vpumix>; + reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; }; }; @@ -791,6 +825,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; };

sec_jr1: jr@2000 { @@ -903,7 +938,7 @@ <&clk IMX8MP_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -917,7 +952,7 @@ <&clk IMX8MP_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -931,7 +966,7 @@ <&clk IMX8MP_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -1018,6 +1053,26 @@ }; };

+ noc: interconnect@32700000 { + compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MP_CLK_NOC>; + #interconnect-cells = <1>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200M { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-1000M { + opp-hz = /bits/ 64 <1000000000>; + }; + }; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; @@ -1043,6 +1098,18 @@ "lcdif1", "isi", "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2"; + interconnects = + <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, + <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; + interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", + "isi1", "isi2", "isp0", "isp1", + "dwe"; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, @@ -1063,6 +1130,17 @@ #power-domain-cells = <1>; };

+ pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mp-pcie-phy"; + reg = <0x32f00000 0x10000>; + resets = <&src IMX8MP_RESET_PCIEPHY>, + <&src IMX8MP_RESET_PCIEPHY_PERST>; + reset-names = "pciephy", "perst"; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + hsio_blk_ctrl: blk-ctrl@32f10000 { compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; reg = <0x32f10000 0x24>; @@ -1074,10 +1152,46 @@ <&pgc_hsiomix>, <&pgc_pcie_phy>; power-domain-names = "bus", "usb", "usb-phy1", "usb-phy2", "pcie", "pcie-phy"; + interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, + <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, + <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, + <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; + interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; #power-domain-cells = <1>; }; };

+ pcie: pcie@33800000 { + compatible = "fsl,imx8mp-pcie"; + reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <3>; + linux,pci-domain = <0>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + gpu3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; @@ -1109,6 +1223,23 @@ power-domains = <&pgc_gpu2d>; };

+ vpumix_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + #power-domain-cells = <1>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, + <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; + power-domain-names = "bus", "g1", "g2", "vc8000e"; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, + <&clk IMX8MP_CLK_VPU_G2_ROOT>, + <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + clock-names = "g1", "g2", "vc8000e"; + interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, + <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, + <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; + interconnect-names = "g1", "g2", "vc8000e"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, @@ -1168,7 +1299,7 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; - snps,dis-u2-freeclk-exists-quirk; + snps,gfladj-refclk-lpm-sel-quirk; };

}; @@ -1210,7 +1341,7 @@ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; - snps,dis-u2-freeclk-exists-quirk; + snps,gfladj-refclk-lpm-sel-quirk; }; };

diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index e8d68fbb6e..9d5cc2ddde 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -117,7 +117,6 @@ #define IMX8MP_CLK_AUDIO_AHB 108 #define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 #define IMX8MP_CLK_IPG_ROOT 110 -#define IMX8MP_CLK_IPG_AUDIO_ROOT 111 #define IMX8MP_CLK_DRAM_ALT 112 #define IMX8MP_CLK_DRAM_APB 113 #define IMX8MP_CLK_VPU_G1 114 @@ -125,7 +124,6 @@ #define IMX8MP_CLK_CAN1 116 #define IMX8MP_CLK_CAN2 117 #define IMX8MP_CLK_MEMREPAIR 118 -#define IMX8MP_CLK_PCIE_PHY 119 #define IMX8MP_CLK_PCIE_AUX 120 #define IMX8MP_CLK_I2C5 121 #define IMX8MP_CLK_I2C6 122 @@ -182,8 +180,6 @@ #define IMX8MP_CLK_MEDIA_CAM2_PIX 173 #define IMX8MP_CLK_MEDIA_LDB 174 #define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 -#define IMX8MP_CLK_PCIE2_CTRL 176 -#define IMX8MP_CLK_PCIE2_PHY 177 #define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 #define IMX8MP_CLK_ECSPI3 179 #define IMX8MP_CLK_PDM 180 @@ -321,8 +317,15 @@ #define IMX8MP_CLK_AUDIO_AXI 310 #define IMX8MP_CLK_HSIO_AXI 311 #define IMX8MP_CLK_MEDIA_ISP 312 +#define IMX8MP_CLK_MEDIA_DISP2_PIX 313 +#define IMX8MP_CLK_CLKOUT1_SEL 314 +#define IMX8MP_CLK_CLKOUT1_DIV 315 +#define IMX8MP_CLK_CLKOUT1 316 +#define IMX8MP_CLK_CLKOUT2_SEL 317 +#define IMX8MP_CLK_CLKOUT2_DIV 318 +#define IMX8MP_CLK_CLKOUT2 319

-#define IMX8MP_CLK_END 313 +#define IMX8MP_CLK_END 320

#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 diff --git a/include/dt-bindings/interconnect/fsl,imx8mp.h b/include/dt-bindings/interconnect/fsl,imx8mp.h new file mode 100644 index 0000000000..7357d41752 --- /dev/null +++ b/include/dt-bindings/interconnect/fsl,imx8mp.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright 2022 NXP + * Peng Fan peng.fan@nxp.com + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H + +#define IMX8MP_ICN_NOC 0 +#define IMX8MP_ICN_MAIN 1 +#define IMX8MP_ICS_DRAM 2 +#define IMX8MP_ICS_OCRAM 3 +#define IMX8MP_ICM_A53 4 +#define IMX8MP_ICM_SUPERMIX 5 +#define IMX8MP_ICM_GIC 6 +#define IMX8MP_ICM_MLMIX 7 + +#define IMX8MP_ICN_AUDIO 8 +#define IMX8MP_ICM_DSP 9 +#define IMX8MP_ICM_SDMA2PER 10 +#define IMX8MP_ICM_SDMA2BURST 11 +#define IMX8MP_ICM_SDMA3PER 12 +#define IMX8MP_ICM_SDMA3BURST 13 +#define IMX8MP_ICM_EDMA 14 + +#define IMX8MP_ICN_GPU 15 +#define IMX8MP_ICM_GPU2D 16 +#define IMX8MP_ICM_GPU3D 17 + +#define IMX8MP_ICN_HDMI 18 +#define IMX8MP_ICM_HRV 19 +#define IMX8MP_ICM_LCDIF_HDMI 20 +#define IMX8MP_ICM_HDCP 21 + +#define IMX8MP_ICN_HSIO 22 +#define IMX8MP_ICM_NOC_PCIE 23 +#define IMX8MP_ICM_USB1 24 +#define IMX8MP_ICM_USB2 25 +#define IMX8MP_ICM_PCIE 26 + +#define IMX8MP_ICN_MEDIA 27 +#define IMX8MP_ICM_LCDIF_RD 28 +#define IMX8MP_ICM_LCDIF_WR 29 +#define IMX8MP_ICM_ISI0 30 +#define IMX8MP_ICM_ISI1 31 +#define IMX8MP_ICM_ISI2 32 +#define IMX8MP_ICM_ISP0 33 +#define IMX8MP_ICM_ISP1 34 +#define IMX8MP_ICM_DWE 35 + +#define IMX8MP_ICN_VIDEO 36 +#define IMX8MP_ICM_VPU_G1 37 +#define IMX8MP_ICM_VPU_G2 38 +#define IMX8MP_ICM_VPU_H1 39 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */ diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h index 3f72bf7818..2fe3c2abad 100644 --- a/include/dt-bindings/power/imx8mp-power.h +++ b/include/dt-bindings/power/imx8mp-power.h @@ -38,9 +38,22 @@ #define IMX8MP_MEDIABLK_PD_ISI 3 #define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4 #define IMX8MP_MEDIABLK_PD_LCDIF_2 5 -#define IMX8MP_MEDIABLK_PD_ISP2 6 -#define IMX8MP_MEDIABLK_PD_ISP1 7 -#define IMX8MP_MEDIABLK_PD_DWE 8 -#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 9 +#define IMX8MP_MEDIABLK_PD_ISP 6 +#define IMX8MP_MEDIABLK_PD_DWE 7 +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8 + +#define IMX8MP_HDMIBLK_PD_IRQSTEER 0 +#define IMX8MP_HDMIBLK_PD_LCDIF 1 +#define IMX8MP_HDMIBLK_PD_PAI 2 +#define IMX8MP_HDMIBLK_PD_PVI 3 +#define IMX8MP_HDMIBLK_PD_TRNG 4 +#define IMX8MP_HDMIBLK_PD_HDMI_TX 5 +#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6 +#define IMX8MP_HDMIBLK_PD_HDCP 7 +#define IMX8MP_HDMIBLK_PD_HRV 8 + +#define IMX8MP_VPUBLK_PD_G1 0 +#define IMX8MP_VPUBLK_PD_G2 1 +#define IMX8MP_VPUBLK_PD_VC8000E 2

#endif diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h new file mode 100644 index 0000000000..2e8c9104b6 --- /dev/null +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 NXP + */ + +#ifndef DT_BINDING_RESET_IMX8MP_H +#define DT_BINDING_RESET_IMX8MP_H + +#define IMX8MP_RESET_A53_CORE_POR_RESET0 0 +#define IMX8MP_RESET_A53_CORE_POR_RESET1 1 +#define IMX8MP_RESET_A53_CORE_POR_RESET2 2 +#define IMX8MP_RESET_A53_CORE_POR_RESET3 3 +#define IMX8MP_RESET_A53_CORE_RESET0 4 +#define IMX8MP_RESET_A53_CORE_RESET1 5 +#define IMX8MP_RESET_A53_CORE_RESET2 6 +#define IMX8MP_RESET_A53_CORE_RESET3 7 +#define IMX8MP_RESET_A53_DBG_RESET0 8 +#define IMX8MP_RESET_A53_DBG_RESET1 9 +#define IMX8MP_RESET_A53_DBG_RESET2 10 +#define IMX8MP_RESET_A53_DBG_RESET3 11 +#define IMX8MP_RESET_A53_ETM_RESET0 12 +#define IMX8MP_RESET_A53_ETM_RESET1 13 +#define IMX8MP_RESET_A53_ETM_RESET2 14 +#define IMX8MP_RESET_A53_ETM_RESET3 15 +#define IMX8MP_RESET_A53_SOC_DBG_RESET 16 +#define IMX8MP_RESET_A53_L2RESET 17 +#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 +#define IMX8MP_RESET_OTG1_PHY_RESET 19 +#define IMX8MP_RESET_OTG2_PHY_RESET 20 +#define IMX8MP_RESET_SUPERMIX_RESET 21 +#define IMX8MP_RESET_AUDIOMIX_RESET 22 +#define IMX8MP_RESET_MLMIX_RESET 23 +#define IMX8MP_RESET_PCIEPHY 24 +#define IMX8MP_RESET_PCIEPHY_PERST 25 +#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 +#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 +#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 +#define IMX8MP_RESET_MEDIA_RESET 29 +#define IMX8MP_RESET_GPU2D_RESET 30 +#define IMX8MP_RESET_GPU3D_RESET 31 +#define IMX8MP_RESET_GPU_RESET 32 +#define IMX8MP_RESET_VPU_RESET 33 +#define IMX8MP_RESET_VPU_G1_RESET 34 +#define IMX8MP_RESET_VPU_G2_RESET 35 +#define IMX8MP_RESET_VPUVC8KE_RESET 36 +#define IMX8MP_RESET_NOC_RESET 37 + +#define IMX8MP_RESET_NUM 38 + +#endif

From: Marcel Ziswiler marcel.ziswiler@toradex.com

Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com Tested-By: Tim Harvey tharvey@gateworks.com #imx8m{m,n,p}-venice-*

---

Changes in v5: - Add Tim's tested-by. Thanks!

Changes in v4: - Re-based after Adam's common imx8mn-u-boot device tree creation. - Re-synched with v6.1-rc3.

arch/arm/dts/imx8mn-beacon-baseboard.dtsi | 4 +- arch/arm/dts/imx8mn-evk.dtsi | 45 ++++++++++++++++++++++- arch/arm/dts/imx8mn-var-som-symphony.dts | 6 +-- arch/arm/dts/imx8mn-venice-gw7902.dts | 9 ++--- arch/arm/dts/imx8mn.dtsi | 14 +++---- include/dt-bindings/interconnect/imx8mn.h | 41 +++++++++++++++++++++ 6 files changed, 101 insertions(+), 18 deletions(-) create mode 100644 include/dt-bindings/interconnect/imx8mn.h

diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi index 02f37dcda7..9e82069c94 100644 --- a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi @@ -146,7 +146,7 @@ };

&easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; };

@@ -182,7 +182,7 @@ &usbotg1 { vbus-supply = <&reg_usb_otg_vbus>; disable-over-current; - dr_mode="otg"; + dr_mode = "otg"; status = "okay"; };

diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi index d1f6cccfa0..261c365400 100644 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -47,6 +47,11 @@ linux,autosuspend-period = <125>; };

+ audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -57,6 +62,25 @@ clock-names = "mclk"; };

+ sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "fsl,imx-audio-wm8524"; model = "wm8524-audio"; @@ -78,7 +102,7 @@ };

&easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; };

@@ -183,6 +207,16 @@ }; };

+&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MN_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -354,6 +388,15 @@ >; };

+ pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts b/arch/arm/dts/imx8mn-var-som-symphony.dts index f61c48776c..3ed7021a48 100644 --- a/arch/arm/dts/imx8mn-var-som-symphony.dts +++ b/arch/arm/dts/imx8mn-var-som-symphony.dts @@ -26,19 +26,19 @@ gpio-keys { compatible = "gpio-keys";

- back { + key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; };

- home { + key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; };

- menu { + key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts index 367a232675..dd4302ac1d 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ b/arch/arm/dts/imx8mn-venice-gw7902.dts @@ -39,13 +39,13 @@ gpio-keys { compatible = "gpio-keys";

- user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; };

- user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -59,14 +59,14 @@ interrupts = <1>; };

- eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; };

- tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; @@ -213,7 +213,6 @@ compatible = "microchip,mcp2515"; reg = <0>; clocks = <&can20m>; - oscillator-frequency = <20000000>; interrupt-parent = <&gpio2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; spi-max-frequency = <10000000>; diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index e41e1d56f9..cb2836bfbd 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -212,7 +212,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; };

@@ -269,7 +269,7 @@ arm,no-tick-in-suspend; };

- soc@0 { + soc: soc@0 { compatible = "fsl,imx8mn-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -422,7 +422,7 @@ "ctx2_rx", "ctx2_tx", "ctx3_rx", "ctx3_tx"; firmware-name = "imx/easrc/easrc-imx8mn.bin"; - fsl,asrc-rate = <8000>; + fsl,asrc-rate = <8000>; fsl,asrc-format = <2>; status = "disabled"; }; @@ -672,7 +672,6 @@ <&clk IMX8MN_CLK_GPU_SHADER>, <&clk IMX8MN_CLK_GPU_BUS_ROOT>, <&clk IMX8MN_CLK_GPU_AHB>; - resets = <&src IMX8MQ_RESET_GPU_RESET>; };

pgc_dispmix: power-domain@3 { @@ -857,6 +856,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; };

sec_jr1: jr@2000 { @@ -941,7 +941,7 @@ <&clk IMX8MN_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -955,7 +955,7 @@ <&clk IMX8MN_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -969,7 +969,7 @@ <&clk IMX8MN_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; diff --git a/include/dt-bindings/interconnect/imx8mn.h b/include/dt-bindings/interconnect/imx8mn.h new file mode 100644 index 0000000000..307b977100 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mn.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H + +#define IMX8MN_ICN_NOC 1 +#define IMX8MN_ICS_DRAM 2 +#define IMX8MN_ICS_OCRAM 3 +#define IMX8MN_ICM_A53 4 + +#define IMX8MN_ICM_GPU 5 +#define IMX8MN_ICN_GPU 6 + +#define IMX8MN_ICM_CSI1 7 +#define IMX8MN_ICM_CSI2 8 +#define IMX8MN_ICM_ISI 9 +#define IMX8MN_ICM_LCDIF 10 +#define IMX8MN_ICN_MIPI 11 + +#define IMX8MN_ICM_USB 12 + +#define IMX8MN_ICM_SDMA2 13 +#define IMX8MN_ICM_SDMA3 14 +#define IMX8MN_ICN_AUDIO 15 + +#define IMX8MN_ICN_ENET 16 +#define IMX8MN_ICM_ENET 17 + +#define IMX8MN_ICM_NAND 18 +#define IMX8MN_ICM_SDMA1 19 +#define IMX8MN_ICM_USDHC1 20 +#define IMX8MN_ICM_USDHC2 21 +#define IMX8MN_ICM_USDHC3 22 +#define IMX8MN_ICN_MAIN 23 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */

From: Marcel Ziswiler marcel.ziswiler@toradex.com

Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com Tested-By: Tim Harvey tharvey@gateworks.com #imx8m{m,n,p}-venice-*

---

Changes in v5: - Add Tim's tested-by. Thanks!

Changes in v4: - Re-synched with v6.1-rc3.

arch/arm/dts/imx8mm-beacon-baseboard.dtsi | 4 +- arch/arm/dts/imx8mm-evk.dtsi | 43 +++++++++++++++++++ arch/arm/dts/imx8mm-icore-mx8mm.dtsi | 14 +++---- arch/arm/dts/imx8mm-mx8menlo.dts | 14 +++---- arch/arm/dts/imx8mm-u-boot.dtsi | 2 +- arch/arm/dts/imx8mm-venice-gw700x.dtsi | 24 +++++------ arch/arm/dts/imx8mm-venice-gw7901.dts | 12 ++++-- arch/arm/dts/imx8mm-venice-gw7902.dts | 14 +++---- arch/arm/dts/imx8mm-venice-gw7903.dts | 6 +-- arch/arm/dts/imx8mm-venice-gw7904.dts | 4 ++ arch/arm/dts/imx8mm-verdin.dtsi | 50 +++++++++++++++++------ include/dt-bindings/interconnect/imx8mm.h | 50 +++++++++++++++++++++++ 12 files changed, 179 insertions(+), 58 deletions(-) create mode 100644 include/dt-bindings/interconnect/imx8mm.h

diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi index f338a886d8..03266bd90a 100644 --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi @@ -285,14 +285,14 @@ &usbotg1 { vbus-supply = <&reg_usbotg1>; disable-over-current; - dr_mode="otg"; + dr_mode = "otg"; status = "okay"; };

&usbotg2 { pinctrl-names = "default"; disable-over-current; - dr_mode="host"; + dr_mode = "host"; status = "okay"; };

diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index c42b966f7a..7d6317d95b 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -75,6 +75,11 @@ linux,autosuspend-period = <125>; };

+ audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -83,6 +88,25 @@ wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; };

+ sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -346,6 +370,16 @@ status = "okay"; };

+&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -494,6 +528,15 @@ >; };

+ pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 diff --git a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi index b40148d728..def7bb5d37 100644 --- a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi +++ b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi @@ -2,7 +2,7 @@ /* * Copyright (c) 2018 NXP * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */

/ { @@ -84,42 +84,42 @@ };

reg_buck1: buck1 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; };

reg_buck2: buck2 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; };

reg_buck3: buck3 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; };

reg_buck4: buck4 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; };

reg_buck5: buck5 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; };

reg_buck6: buck6 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; diff --git a/arch/arm/dts/imx8mm-mx8menlo.dts b/arch/arm/dts/imx8mm-mx8menlo.dts index 92eaf4ef45..32f6f2f50c 100644 --- a/arch/arm/dts/imx8mm-mx8menlo.dts +++ b/arch/arm/dts/imx8mm-mx8menlo.dts @@ -20,13 +20,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>;

- user1 { + led-1 { label = "TestLed601"; gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; };

- user2 { + led-2 { label = "TestLed602"; gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -152,11 +152,11 @@ * CPLD_reset is RESET_SOFT in schematic */ gpio-line-names = - "CPLD_D[1]", "CPLD_int", "CPLD_reset", "", - "", "CPLD_D[0]", "", "", - "", "", "", "CPLD_D[2]", - "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]", - "CPLD_D[7]", "", "", "", + "CPLD_D[6]", "CPLD_int", "CPLD_reset", "", + "", "CPLD_D[7]", "", "", + "", "", "", "CPLD_D[5]", + "CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]", + "CPLD_D[0]", "", "", "", "", "", "", "", "", "", "", "KBD_intK", "", "", "", ""; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index a5e30f7994..60d49bc3d7 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -9,7 +9,7 @@ }; };

-&{/soc@0} { +&soc { u-boot,dm-pre-reloc; u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi index 00f86cada3..66a0d103c9 100644 --- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi @@ -16,13 +16,13 @@ gpio-keys { compatible = "gpio-keys";

- user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; };

- user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -36,14 +36,14 @@ interrupts = <1>; };

- eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; };

- tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; @@ -286,8 +286,8 @@ regulator-name = "buck1"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; regulator-boot-on; regulator-always-on; }; @@ -297,8 +297,8 @@ regulator-name = "buck2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; regulator-always-on; }; @@ -308,8 +308,8 @@ regulator-name = "buck3"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; regulator-always-on; };

@@ -318,8 +318,8 @@ regulator-name = "buck4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts index 24737e8903..d3ee6fc4ba 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901.dts +++ b/arch/arm/dts/imx8mm-venice-gw7901.dts @@ -38,13 +38,13 @@ gpio-keys { compatible = "gpio-keys";

- user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; };

- user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -58,14 +58,14 @@ interrupts = <1>; };

- eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; };

- tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; @@ -626,24 +626,28 @@ lan1: port@0 { reg = <0>; label = "lan1"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; };

lan2: port@1 { reg = <1>; label = "lan2"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; };

lan3: port@2 { reg = <2>; label = "lan3"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; };

lan4: port@3 { reg = <3>; label = "lan4"; + phy-mode = "internal"; local-mac-address = [00 00 00 00 00 00]; };

diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index 8e8d0d34c2..31f4c735fe 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -42,13 +42,13 @@ gpio-keys { compatible = "gpio-keys";

- user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; };

- user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -62,14 +62,14 @@ interrupts = <1>; };

- eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; };

- tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; @@ -222,7 +222,6 @@ compatible = "microchip,mcp2515"; reg = <0>; clocks = <&can20m>; - oscillator-frequency = <20000000>; interrupt-parent = <&gpio2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; spi-max-frequency = <10000000>; @@ -651,7 +650,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; uart-has-rtscts; status = "okay"; }; @@ -742,9 +741,6 @@ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ - MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ - MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts b/arch/arm/dts/imx8mm-venice-gw7903.dts index 1b69ac0e12..19f6d2943d 100644 --- a/arch/arm/dts/imx8mm-venice-gw7903.dts +++ b/arch/arm/dts/imx8mm-venice-gw7903.dts @@ -33,13 +33,13 @@ gpio-keys { compatible = "gpio-keys";

- user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; };

- user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -53,7 +53,7 @@ interrupts = <1>; };

- eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; diff --git a/arch/arm/dts/imx8mm-venice-gw7904.dts b/arch/arm/dts/imx8mm-venice-gw7904.dts index 2b68fb3e43..a67771d021 100644 --- a/arch/arm/dts/imx8mm-venice-gw7904.dts +++ b/arch/arm/dts/imx8mm-venice-gw7904.dts @@ -617,6 +617,10 @@ status = "okay"; };

+&pgc_mipi { + status = "disabled"; +}; + /* off-board RS232 */ &uart1 { pinctrl-names = "default"; diff --git a/arch/arm/dts/imx8mm-verdin.dtsi b/arch/arm/dts/imx8mm-verdin.dtsi index eafa88d980..bcab830c6e 100644 --- a/arch/arm/dts/imx8mm-verdin.dtsi +++ b/arch/arm/dts/imx8mm-verdin.dtsi @@ -32,10 +32,10 @@ };

/* Fixed clock dedicated to SPI CAN controller */ - clk20m: oscillator { + clk40m: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <20000000>; + clock-frequency = <40000000>; };

gpio-keys { @@ -43,7 +43,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>;

- wakeup { + key-wakeup { debounce-interval = <10>; /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; @@ -53,6 +53,21 @@ }; };

+ hdmi_connector: hdmi-connector { + compatible = "hdmi-connector"; + ddc-i2c-bus = <&i2c2>; + label = "hdmi"; + type = "a"; + status = "disabled"; + }; + + panel_lvds: panel-lvds { + compatible = "panel-lvds"; + backlight = <&backlight>; + data-mapping = "vesa-24"; + status = "disabled"; + }; + /* Carrier Board Supplies */ reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; @@ -154,6 +169,14 @@ cpu-supply = <&reg_vdd_arm>; };

+&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>;

@@ -194,8 +217,8 @@

can1: can@0 { compatible = "microchip,mcp251xfd"; - clocks = <&clk20m>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clk40m>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_int>; reg = <0>; @@ -359,8 +382,8 @@ nxp,dvs-standby-voltage = <850000>; regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <950000>; - regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <805000>; regulator-name = "On-module +VDD_ARM (BUCK2)"; regulator-ramp-delay = <3125>; }; @@ -368,8 +391,8 @@ reg_vdd_dram: BUCK3 { regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <950000>; - regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <805000>; regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; };

@@ -408,7 +431,7 @@ reg_vdd_snvs: LDO2 { regulator-always-on; regulator-boot-on; - regulator-max-microvolt = <900000>; + regulator-max-microvolt = <800000>; regulator-min-microvolt = <800000>; regulator-name = "On-module +V0.8_SNVS (LDO2)"; }; @@ -553,8 +576,8 @@ status = "disabled"; };

- lvds_ti_sn65dsi83: bridge@2c { - compatible = "ti,sn65dsi83"; + lvds_ti_sn65dsi84: bridge@2c { + compatible = "ti,sn65dsi84"; /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ /* Verdin GPIO_10_DSI (SODIMM 21) */ enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; @@ -595,7 +618,7 @@ pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; reg = <0x4a>; /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ - reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; status = "disabled"; };

@@ -737,6 +760,7 @@ };

&usbphynop2 { + power-domains = <&pgc_otg2>; vcc-supply = <&reg_vdd_3v3>; };

diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h new file mode 100644 index 0000000000..8f10bb06cb --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mm.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon abailon@baylibre.com + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H + +#define IMX8MM_ICN_NOC 1 +#define IMX8MM_ICS_DRAM 2 +#define IMX8MM_ICS_OCRAM 3 +#define IMX8MM_ICM_A53 4 + +#define IMX8MM_ICM_VPU_H1 5 +#define IMX8MM_ICM_VPU_G1 6 +#define IMX8MM_ICM_VPU_G2 7 +#define IMX8MM_ICN_VIDEO 8 + +#define IMX8MM_ICM_GPU2D 9 +#define IMX8MM_ICM_GPU3D 10 +#define IMX8MM_ICN_GPU 11 + +#define IMX8MM_ICM_CSI 12 +#define IMX8MM_ICM_LCDIF 13 +#define IMX8MM_ICN_MIPI 14 + +#define IMX8MM_ICM_USB1 15 +#define IMX8MM_ICM_USB2 16 +#define IMX8MM_ICM_PCIE 17 +#define IMX8MM_ICN_HSIO 18 + +#define IMX8MM_ICM_SDMA2 19 +#define IMX8MM_ICM_SDMA3 20 +#define IMX8MM_ICN_AUDIO 21 + +#define IMX8MM_ICN_ENET 22 +#define IMX8MM_ICM_ENET 23 + +#define IMX8MM_ICN_MAIN 24 +#define IMX8MM_ICM_NAND 25 +#define IMX8MM_ICM_SDMA1 26 +#define IMX8MM_ICM_USDHC1 27 +#define IMX8MM_ICM_USDHC2 28 +#define IMX8MM_ICM_USDHC3 29 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */