This patch provides support to program a flash bank address register.

extended/bank address register contains an information to access the 4th byte addressing in 3-byte address mode.

reff' the spec for more details about bank addr register in Page-63, Table 8.16 http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf

Signed-off-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com Reviewed-by: Simon Glass sjg@chromium.org --- Changes for v5: - none Changes for v4: - remove bank cmds Changes for v3: - none Changes for v2: - none

drivers/mtd/spi/spi_flash.c | 26 ++++++++++++++++++++++++++ drivers/mtd/spi/spi_flash_internal.h | 3 +++ 2 files changed, 29 insertions(+)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 0e38f59..9ddd070 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -278,6 +278,32 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) return 0; }

+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) +{ + u8 cmd; + int ret; + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + return ret; + } + + ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &bank_sel, 1); + if (ret) { + debug("SF: fail to write bank addr register\n"); + return ret; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: write bank addr register timed out\n"); + return ret; + } + + return 0; +} + #ifdef CONFIG_OF_CONTROL int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) { diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 141cfa8..772fef6 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -77,6 +77,9 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) /* Program the status register. */ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);

+/* Program the bank address register */ +int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel); + /* * Same as spi_flash_cmd_read() except it also claims/releases the SPI * bus. Used as common part of the ->read() operation.