[U-Boot] [PATCH 0/7] ARM: DRA7: DDR3: Enable hw leveling
This series updates the DDR3 init sequence and adds support for hw leveling for all DRA7 platforms.
Tested memtest and reboot on DRA7-evm , DRA72-evm, BeagleBoard-x15 boards.
Lokesh Vutla (7): ARM: DRA7: DDR3: Add support for HW leveling ARM: BeagleBoard-X15: Enable HW leveling ARM: DRA7-evm: Enable HW leveling ARM: DRA72-evm: Enable HW leveling ARM: DRA7: Add is_dra72x cpu check definition ARM: DRA7: Update DDR IO configuration ARM: DRA7: Update DDR IO registers
arch/arm/cpu/armv7/omap-common/emif-common.c | 146 +++++++++++++++++++++++---- arch/arm/cpu/armv7/omap5/hw_data.c | 16 +-- arch/arm/cpu/armv7/omap5/hwinit.c | 12 ++- arch/arm/cpu/armv7/omap5/sdram.c | 115 ++++++++++++++++++--- arch/arm/include/asm/emif.h | 9 ++ arch/arm/include/asm/omap_common.h | 7 ++ board/ti/beagle_x15/board.c | 41 ++++++-- 7 files changed, 288 insertions(+), 58 deletions(-)
DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap-common/emif-common.c | 146 +++++++++++++++++++++++---- arch/arm/cpu/armv7/omap5/sdram.c | 76 +++++++++++++- arch/arm/include/asm/emif.h | 9 ++ board/ti/beagle_x15/board.c | 15 ++- 4 files changed, 220 insertions(+), 26 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index c01a98f..3ee4695 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -242,13 +242,122 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) __udelay(130); }
-static void ddr3_leveling(u32 base, const struct emif_regs *regs) +static void update_hwleveling_output(u32 base, const struct emif_regs *regs) { - if (is_omap54xx()) - omap5_ddr3_leveling(base, regs); + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; + u32 reg, i; + + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; + + /* Update PHY_REG_RDDQS_RATIO */ + emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; + for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } + + /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ + emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; + for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } + + /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ + emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; + for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } + + /* Disable Leveling */ + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); }
-static void ddr3_init(u32 base, const struct emif_regs *regs) +static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* Clear Error Status */ + clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); + + clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); + + /* Disable refreshed before leveling */ + clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT, + EMIF_REG_INITREF_DIS_SHIFT); + + /* Start Full leveling */ + writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); + + __udelay(300); + + /* Check for leveling timeout */ + if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) { + printf("Leveling timeout on EMIF%d\n", emif_num(base)); + return; + } + + /* Enable refreshes after leveling */ + clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT); + + debug("HW leveling success\n"); + /* + * Update slave ratios in EXT_PHY_CTRLx registers + * as per HW leveling output + */ + update_hwleveling_output(base, regs); +} + +static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + if (warm_reset()) + emif_reset_phy(base); + do_ext_phy_settings(base, regs); + + writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, + &emif->emif_sdram_ref_ctrl); + /* Update timing registers */ + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); + + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); + writel(regs->zq_config, &emif->emif_zq_config); + writel(regs->temp_alert_config, &emif->emif_temp_alert_config); + writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); + + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); + + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + + __udelay(1000); + + writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); + + if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) + dra7_ddr3_leveling(base, regs); +} + +static void omap5_ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -269,25 +378,20 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
- /* - * The same sequence should work on OMAP5432 as well. But strange that - * it is not working - */ - if (is_dra7xx()) { - do_ext_phy_settings(base, regs); - writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - } else { - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - do_ext_phy_settings(base, regs); - } + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + do_ext_phy_settings(base, regs);
- /* enable leveling */ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + omap5_ddr3_leveling(base, regs); +}
- ddr3_leveling(base, regs); +static void ddr3_init(u32 base, const struct emif_regs *regs) +{ + if (is_omap54xx()) + omap5_ddr3_init(base, regs); + else + dra7_ddr3_init(base, regs); }
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS @@ -1075,7 +1179,7 @@ static void do_sdram_init(u32 base) if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { set_lpmode_selfrefresh(base); emif_reset_phy(base); - ddr3_leveling(base, regs); + omap5_ddr3_leveling(base, regs); }
/* Write to the shadow registers */ diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 5f8daa1..2e23852 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -421,8 +421,14 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = { 0x0 };
+/* Ext phy ctrl 1-35 regs */ const u32 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { + 0x10040100, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, 0x00980098, 0x00340034, 0x00350035, @@ -441,7 +447,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { 0x00500050, 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x0, 0x0, @@ -450,8 +456,14 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { 0x0 };
+/* Ext phy ctrl 1-35 regs */ const u32 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { + 0x10040100, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, 0x00980098, 0x00330033, 0x00330033, @@ -470,7 +482,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { 0x00500050, 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x0, 0x0, @@ -479,8 +491,14 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { 0x0 };
+/* Ext phy ctrl 1-35 regs */ const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { + 0x10040100, + 0x00A400A4, + 0x00A900A9, + 0x00B000B0, + 0x00B000B0, 0x00A400A4, 0x00390039, 0x00320032, @@ -562,7 +580,7 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) *regs = &mr_regs; }
-void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs) { u32 *ext_phy_ctrl_base = 0; u32 *emif_ext_phy_ctrl_base = 0; @@ -601,6 +619,58 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) } }
+static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *emif_ext_phy_ctrl_base = 0; + u32 emif_nr; + const u32 *ext_phy_ctrl_const_regs; + u32 i, hw_leveling, size; + + emif_nr = (base == EMIF1_BASE) ? 1 : 2; + + hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT; + + emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1); + + emif_get_ext_phy_ctrl_const_regs(emif_nr, + &ext_phy_ctrl_const_regs, &size); + + writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]); + writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]); + + if (!hw_leveling) { + /* + * Copy the predefined PHY register values + * in case of sw leveling + */ + for (i = 1; i < 25; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + } else { + /* + * Write the init value for HW levling to occur + */ + for (i = 21; i < 35; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + } +} + +void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ + if (is_omap54xx()) + do_ext_phy_settings_omap5(base, regs); + else + do_ext_phy_settings_dra7(base, regs); +} + #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS static const struct lpddr2_ac_timings timings_jedec_532_mhz = { .max_freq = 532000000, diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 7a545ea..a97d2fd 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -44,6 +44,8 @@ #define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30) #define EMIF_REG_FAST_INIT_SHIFT 29 #define EMIF_REG_FAST_INIT_MASK (1 << 29) +#define EMIF_REG_LEVLING_TO_SHIFT 4 +#define EMIF_REG_LEVELING_TO_MASK (7 << 4) #define EMIF_REG_PHY_DLL_READY_SHIFT 2 #define EMIF_REG_PHY_DLL_READY_MASK (1 << 2)
@@ -509,6 +511,13 @@ #define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 #define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
+/* EMIF_PHY_CTRL_36 */ +#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR (1 << 8) + +#define PHY_RDDQS_RATIO_REGS 5 +#define PHY_FIFO_WE_SLAVE_RATIO_REGS 5 +#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS 10 + /*Leveling Fields */ #define DDR3_WR_LVL_INT 0x73 #define DDR3_RD_LVL_INT 0x33 diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index 3a7e04d..75dd8e8 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -68,7 +68,13 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .emif_rd_wr_exec_thresh = 0x00000305 };
+/* Ext phy ctrl regs 1-35 */ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { + 0x10040100, + 0x00740074, + 0x00780078, + 0x007c007c, + 0x007b007b, 0x00800080, 0x00360036, 0x00340034, @@ -90,7 +96,7 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040,
0x00400040, @@ -126,6 +132,11 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { };
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { + 0x10040100, + 0x00820082, + 0x008b008b, + 0x00800080, + 0x007e007e, 0x00800080, 0x00370037, 0x00390039, @@ -145,7 +156,7 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040,
0x00400040,
On Wed, Jun 03, 2015 at 02:43:21PM +0530, Lokesh Vutla wrote:
DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Jun 03, 2015 at 02:43:21PM +0530, Lokesh Vutla wrote:
DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Updating EMIF registers to enable HW leveling on BeagleBoard-X15.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/beagle_x15/board.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index 75dd8e8..76654c8 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -55,15 +55,15 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0e24400a, - .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00740074, .emif_ddr_ext_phy_ctrl_3 = 0x00780078, .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -103,7 +103,12 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x00400040, 0x00400040, 0x00400040, - 0x00400040 + 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 };
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { @@ -118,15 +123,15 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0e24400a, - .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00820082, .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, .emif_ddr_ext_phy_ctrl_4 = 0x00800080, .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -163,7 +168,12 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x00400040, 0x00400040, 0x00400040, - 0x00400040 + 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 };
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
On Wed, Jun 03, 2015 at 02:43:22PM +0530, Lokesh Vutla wrote:
Updating EMIF registers to enable HW leveling on BeagleBoard-X15.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Jun 03, 2015 at 02:43:22PM +0530, Lokesh Vutla wrote:
Updating EMIF registers to enable HW leveling on BeagleBoard-X15.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Hi Lokesh,
We are working on U-Boot for CompuLab board based on AM57xx SoC (CL-SOM-AM57x).
We figured out the following note in AM57xx TRM for EMIF register EMIF_DDR_PHY_CONTROL_1, bits 25:27 (WRLVL_MASK, RDLVLGATE_MASK, RDLVL_MASK)
"NOTE: Read-Write Leveling is not supported on this device. Set this value to 0x1."
This contradicts with the following patch, enabling HW leveling for BeagleBoard-X15.
Please, advice, if it save and required to apply HW leveling related registers settings.
Does DRA7x DDR3 HW leveling code is relevant for AM57xx ?
Thank you,
Dmitry Lifshitz
On 06/03/2015 12:13 PM, Lokesh Vutla wrote:
Updating EMIF registers to enable HW leveling on BeagleBoard-X15.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
board/ti/beagle_x15/board.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index 75dd8e8..76654c8 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -55,15 +55,15 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00740074, .emif_ddr_ext_phy_ctrl_3 = 0x00780078, .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 };
@@ -103,7 +103,12 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x00400040, 0x00400040, 0x00400040,
- 0x00400040
0x00400040,
0x0,
0x0,
0x0,
0x0,
0x0 };
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
@@ -118,15 +123,15 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00820082, .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, .emif_ddr_ext_phy_ctrl_4 = 0x00800080, .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 };
@@ -163,7 +168,12 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x00400040, 0x00400040, 0x00400040,
- 0x00400040
0x00400040,
0x0,
0x0,
0x0,
0x0,
0x0 };
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
Hi,
On Monday 14 December 2015 06:40 PM, Dmitry Lifshitz wrote:
Hi Lokesh,
We are working on U-Boot for CompuLab board based on AM57xx SoC (CL-SOM-AM57x).
We figured out the following note in AM57xx TRM for EMIF register EMIF_DDR_PHY_CONTROL_1, bits 25:27 (WRLVL_MASK, RDLVLGATE_MASK, RDLVL_MASK)
"NOTE: Read-Write Leveling is not supported on this device. Set this value to 0x1."
Actually this is not true. It is supported and has been successfully tested. TRM needs to be updated. Thanks for catching this. Ill take the necessary steps for this update in TRM.
Thanks and regards, Lokesh
This contradicts with the following patch, enabling HW leveling for BeagleBoard-X15.
Please, advice, if it save and required to apply HW leveling related registers settings.
Does DRA7x DDR3 HW leveling code is relevant for AM57xx ?
Thank you,
Dmitry Lifshitz
On 06/03/2015 12:13 PM, Lokesh Vutla wrote:
Updating EMIF registers to enable HW leveling on BeagleBoard-X15.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
board/ti/beagle_x15/board.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index 75dd8e8..76654c8 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -55,15 +55,15 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00740074, .emif_ddr_ext_phy_ctrl_3 = 0x00780078, .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 };
@@ -103,7 +103,12 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x00400040, 0x00400040, 0x00400040,
- 0x00400040
0x00400040,
0x0,
0x0,
0x0,
0x0,
0x0 };
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs
= { @@ -118,15 +123,15 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00820082, .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, .emif_ddr_ext_phy_ctrl_4 = 0x00800080, .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 };
@@ -163,7 +168,12 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x00400040, 0x00400040, 0x00400040,
- 0x00400040
0x00400040,
0x0,
0x0,
0x0,
0x0,
0x0 };
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
Hi Lokesh,
On 12/16/2015 02:54 PM, Lokesh Vutla wrote:
Hi,
On Monday 14 December 2015 06:40 PM, Dmitry Lifshitz wrote:
Hi Lokesh,
We are working on U-Boot for CompuLab board based on AM57xx SoC (CL-SOM-AM57x).
We figured out the following note in AM57xx TRM for EMIF register EMIF_DDR_PHY_CONTROL_1, bits 25:27 (WRLVL_MASK, RDLVLGATE_MASK, RDLVL_MASK)
"NOTE: Read-Write Leveling is not supported on this device. Set this value to 0x1."
Actually this is not true. It is supported and has been successfully tested. TRM needs to be updated. Thanks for catching this. Ill take the necessary steps for this update in TRM.
Thank you for the update.
Does TI has any kind of tool (for AM57x SoC family) that may help to configure/validate EMIF and PHY registers settings?
Thanks,
Dmitry
Thanks and regards, Lokesh
This contradicts with the following patch, enabling HW leveling for BeagleBoard-X15.
Please, advice, if it save and required to apply HW leveling related registers settings.
Does DRA7x DDR3 HW leveling code is relevant for AM57xx ?
Thank you,
Dmitry Lifshitz
On 06/03/2015 12:13 PM, Lokesh Vutla wrote:
Updating EMIF registers to enable HW leveling on BeagleBoard-X15.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
board/ti/beagle_x15/board.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index 75dd8e8..76654c8 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -55,15 +55,15 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00740074, .emif_ddr_ext_phy_ctrl_3 = 0x00780078, .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 };
@@ -103,7 +103,12 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x00400040, 0x00400040, 0x00400040,
- 0x00400040
0x00400040,
0x0,
0x0,
0x0,
0x0,
0x0 };
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs
= { @@ -118,15 +123,15 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
- .emif_ddr_phy_ctlr_1_init = 0x0024400b,
- .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00820082, .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, .emif_ddr_ext_phy_ctrl_4 = 0x00800080, .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 };
@@ -163,7 +168,12 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x00400040, 0x00400040, 0x00400040,
- 0x00400040
0x00400040,
0x0,
0x0,
0x0,
0x0,
0x0 };
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
Updating EMIF registers to enable HW leveling on DRA7-evm.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/sdram.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 2e23852..942a80a 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -149,15 +149,15 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00910091, .emif_ddr_ext_phy_ctrl_3 = 0x00950095, .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -174,15 +174,15 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00910091, .emif_ddr_ext_phy_ctrl_3 = 0x00950095, .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -453,6 +453,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 };
@@ -488,6 +493,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 };
On Wed, Jun 03, 2015 at 02:43:23PM +0530, Lokesh Vutla wrote:
Updating EMIF registers to enable HW leveling on DRA7-evm.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Jun 03, 2015 at 02:43:23PM +0530, Lokesh Vutla wrote:
Updating EMIF registers to enable HW leveling on DRA7-evm.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/sdram.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 942a80a..3022b9e 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -191,15 +191,15 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .sdram_config_init = 0x61862B32, .sdram_config = 0x61862B32, .sdram_config2 = 0x08000000, - .ref_ctrl = 0x0000493E, + .ref_ctrl = 0x0000514C, .ref_ctrl_final = 0x0000144A, .sdram_tim1 = 0xD113781C, - .sdram_tim2 = 0x308F7FE3, - .sdram_tim3 = 0x009F86A8, + .sdram_tim2 = 0x305A7FDA, + .sdram_tim3 = 0x409F86A8, .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190B, + .zq_config = 0x5007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400D, + .emif_ddr_phy_ctlr_1_init = 0x0024400D, .emif_ddr_phy_ctlr_1 = 0x0E24400D, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, @@ -207,7 +207,7 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -533,6 +533,11 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 };
On Wed, Jun 03, 2015 at 02:43:24PM +0530, Lokesh Vutla wrote:
Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Jun 03, 2015 at 02:43:24PM +0530, Lokesh Vutla wrote:
Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
A generic is_dra72x cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/omap_common.h | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 123c84f..3387c1d 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -617,12 +617,19 @@ static inline u8 is_omap54xx(void) }
#define DRA7XX 0x07000000 +#define DRA72X 0x07200000
static inline u8 is_dra7xx(void) { extern u32 *const omap_si_rev; return ((*omap_si_rev & 0xFF000000) == DRA7XX); } + +static inline u8 is_dra72x(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xFFF00000) == DRA72X; +} #endif
/*
On Wed, Jun 03, 2015 at 02:43:25PM +0530, Lokesh Vutla wrote:
A generic is_dra72x cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Jun 03, 2015 at 02:43:25PM +0530, Lokesh Vutla wrote:
A generic is_dra72x cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/hwinit.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 8d6b59e..03c2b97 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -75,16 +75,20 @@ static void io_settings_ddr3(void)
writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); - writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); + + if (!is_dra7xx()) { + writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); + }
/* omap5432 does not use lpddr2 */ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); - writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
writel(ioregs->ctrl_emif_sdram_config_ext, (*ctrl)->control_emif1_sdram_config_ext); - writel(ioregs->ctrl_emif_sdram_config_ext, - (*ctrl)->control_emif2_sdram_config_ext); + if (!is_dra72x()) + writel(ioregs->ctrl_emif_sdram_config_ext, + (*ctrl)->control_emif2_sdram_config_ext);
if (is_omap54xx()) { /* Disable DLL select */
On Wed, Jun 03, 2015 at 02:43:26PM +0530, Lokesh Vutla wrote:
DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Jun 03, 2015 at 02:43:26PM +0530, Lokesh Vutla wrote:
DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Update DDR IO register values.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index b9734fe..6de5974 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -578,11 +578,11 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = { .ctrl_ddrch = 0x40404040, .ctrl_lpddr2ch = 0x40404040, .ctrl_ddr3ch = 0x80808080, - .ctrl_ddrio_0 = 0xA2084210, - .ctrl_ddrio_1 = 0x84210840, + .ctrl_ddrio_0 = 0x00094A40, + .ctrl_ddrio_1 = 0x04A52000, .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0x0001C1A7, - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_emif_sdram_config_ext = 0x0001C127, + .ctrl_emif_sdram_config_ext_final = 0x0001C127, .ctrl_ddr_ctrl_ext_0 = 0xA2000000, };
@@ -590,11 +590,11 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = { .ctrl_ddrch = 0x40404040, .ctrl_lpddr2ch = 0x40404040, .ctrl_ddr3ch = 0x60606080, - .ctrl_ddrio_0 = 0xA2084210, - .ctrl_ddrio_1 = 0x84210840, + .ctrl_ddrio_0 = 0x00094A40, + .ctrl_ddrio_1 = 0x04A52000, .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0x0001C1A7, - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_emif_sdram_config_ext = 0x0001C127, + .ctrl_emif_sdram_config_ext_final = 0x0001C127, .ctrl_ddr_ctrl_ext_0 = 0xA2000000, };
On Wed, Jun 03, 2015 at 02:43:27PM +0530, Lokesh Vutla wrote:
Update DDR IO register values.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Wed, Jun 03, 2015 at 02:43:27PM +0530, Lokesh Vutla wrote:
Update DDR IO register values.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
On Wed, Jun 03, 2015 at 02:43:20PM +0530, Lokesh Vutla wrote:
This series updates the DDR3 init sequence and adds support for hw leveling for all DRA7 platforms.
Tested memtest and reboot on DRA7-evm , DRA72-evm, BeagleBoard-x15 boards.
For sanity sake, tested on omap5_uevm (but indeed, the code didn't change just a few related calling paths for that family).
participants (4)
-
Dmitry Lifshitz -
Lokesh Vutla -
Lokesh Vutla -
Tom Rini