[U-Boot] [PATCH] ARM: mx5: Enable L2 cache
Enable L2 cache for improving the system performance.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index fc7c767..e4cd85c 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,12 @@ #endif
mcr 15, 1, r0, c9, c0, 2 + + /* enable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #2 + mcr 15, 0, r0, c1, c0, 1 + .endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
Hi Fabio,
On 30/09/2013 18:16, Fabio Estevam wrote:
Enable L2 cache for improving the system performance.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index fc7c767..e4cd85c 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,12 @@ #endif
mcr 15, 1, r0, c9, c0, 2
- /* enable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- orr r0, r0, #2
- mcr 15, 0, r0, c1, c0, 1
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
This is a repost from a your previous patch on August, 19th, where you report slow tftp transfer even with L2-cache enable. Was this issue solved or it is completeley unrelated to the cache ?
Best regards, Stefano
Hi Stefano,
On Wed, Oct 2, 2013 at 5:36 AM, Stefano Babic sbabic@denx.de wrote:
This is a repost from a your previous patch on August, 19th, where you report slow tftp transfer even with L2-cache enable. Was this issue solved or it is completeley unrelated to the cache ?
Actually the motivation for sending this patch this time was because I am currently working with a customer's USB centric application. By only applying this patch we can see CPU usage being decreased from 35% to 25%.
The TFTP transfer in U-boot is still slow though, but this needs to be investigated separately.
Regards,
Fabio Estevam
Hi Fabio,
On 02/10/2013 15:43, Fabio Estevam wrote:
Hi Stefano,
On Wed, Oct 2, 2013 at 5:36 AM, Stefano Babic sbabic@denx.de wrote:
This is a repost from a your previous patch on August, 19th, where you report slow tftp transfer even with L2-cache enable. Was this issue solved or it is completeley unrelated to the cache ?
Actually the motivation for sending this patch this time was because I am currently working with a customer's USB centric application. By only applying this patch we can see CPU usage being decreased from 35% to 25%.
The TFTP transfer in U-boot is still slow though, but this needs to be investigated separately.
Ok, understood, thanks - I'll pick up this one for the next PR.
Best regards, Stefano Babic
Hi Stefano,
On Wed, Oct 2, 2013 at 11:45 AM, Stefano Babic sbabic@denx.de wrote:
Ok, understood, thanks - I'll pick up this one for the next PR.
I still don't see this patch applied yet.
Regards,
Fabio Estevam
Hi Fabio,
On 31/10/2013 17:07, Fabio Estevam wrote:
Hi Stefano,
On Wed, Oct 2, 2013 at 11:45 AM, Stefano Babic sbabic@denx.de wrote:
Ok, understood, thanks - I'll pick up this one for the next PR.
I still don't see this patch applied yet.
Sorry, I will apply it.
Thanks for remind, Stefano
On 30/09/2013 18:16, Fabio Estevam wrote:
Enable L2 cache for improving the system performance.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
Applied to u-boot-imx, thanks !
Best regards, Stefano Babic
participants (3)
-
Fabio Estevam -
Fabio Estevam -
Stefano Babic