[RFC PATCH 0/4] Alternative debug outputs for rockchip devices
I don't intend for the last change to be included in mainline, I just need some form of serial output to see why archlinuxarm, alpine linux, and Fedora workstation all fail to boot on this hardware (rk3399-gru-kevin). Or at least, I think its failing. At the point of booting the kernel the bottom inch or so of the screen corrupts a bit and then nothing. It could be working, but without output on screen or uart2dbga I have no idea what is going wrong.
I *would* use the uart-to-usb functionality of the rk3399, but as far as I know this only works with the 2.0, and I'm not sure if those are available on the rk3399-gru-kevin's type c ports. Do correct me if I'm wrong.
In addition, the GRF_SOC_CON7:grf_uart_dbg_sel is, as far as I know, undocumented, outside of the GRF_UART_DBG_SEL_C enum in grf_rk3399, so the other two options (A and B) are just based on my assumptions. If someone who *actually knows* could elaborate on it and correct me if needed I'd greatly appreciate it.
Marty E. Plummer (4): rockchip: rk3288: enable u-boot.rom for speedy rockchip: rk3288: enable uart2->usb redirection rockchip: rk3399: fix typo in grf file rockchip: rk3399: attempt to redirect uart2dbga to sdcard
arch/arm/dts/rk3399-gru.dtsi | 7 +--- arch/arm/dts/rk3399.dtsi | 4 +- .../include/asm/arch-rockchip/grf_rk3288.h | 41 +++++++++++++++++++ .../include/asm/arch-rockchip/grf_rk3399.h | 5 ++- arch/arm/mach-rockchip/rk3288/Kconfig | 2 + arch/arm/mach-rockchip/rk3288/rk3288.c | 20 +++++++++ arch/arm/mach-rockchip/rk3399/rk3399.c | 18 ++++---- 7 files changed, 80 insertions(+), 17 deletions(-)
Trivial change, builds a bootable u-boot.rom properly.
Signed-off-by: Marty E. Plummer hanetzer@startmail.com ---
arch/arm/mach-rockchip/rk3288/Kconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index e8c57843a3..99bf2397e6 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -37,7 +37,9 @@ config TARGET_CHROMEBOOK_MINNIE
config TARGET_CHROMEBOOK_SPEEDY bool "Google/Rockchip Veyron-Speedy Chromebook" + select HAS_ROM select BOARD_LATE_INIT + select ROCKCHIP_SPI_IMAGE help Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports, micro HDMI, an 11.6 inch display, micro-SD card,
On Thu, 22 Sept 2022 at 00:47, Marty E. Plummer hanetzer@startmail.com wrote:
Trivial change, builds a bootable u-boot.rom properly.
Signed-off-by: Marty E. Plummer hanetzer@startmail.com
arch/arm/mach-rockchip/rk3288/Kconfig | 2 ++ 1 file changed, 2 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
Code snagged from rk3188's u-boot implementation and the linux kernel's implementation of rockchip.usb_uart=1 Tested on rk3288-veyron-speedy
patman/checkpatch.pl doesn't like my indentation here and I can't quite figure out what it actually wants. Complaint is: arch/arm/mach-rockchip/rk3288/rk3288.c:95: check: Alignment should match open parenthesis arch/arm/mach-rockchip/rk3288/rk3288.c:99: check: Alignment should match open parenthesis arch/arm/mach-rockchip/rk3288/rk3288.c:101: check: Alignment should match open parenthesis arch/arm/mach-rockchip/rk3288/rk3288.c:108: check: Alignment should match open parenthesis
Signed-off-by: Marty E. Plummer hanetzer@startmail.com ---
.../include/asm/arch-rockchip/grf_rk3288.h | 41 +++++++++++++++++++ arch/arm/mach-rockchip/rk3288/rk3288.c | 20 +++++++++ 2 files changed, 61 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 894d3a40b0..d94cd9a27a 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -1152,4 +1152,45 @@ enum GPIO_BIAS { #define GPIO_PULL_MASK 0x3 #define GPIO_PULL_SHIFT(x) ((x) * 2)
+/* GRF_UOC_CON0 */ +enum { + SIDDQ_SHIFT = 13, + SIDDQ_MASK = 1 << SIDDQ_SHIFT, + + UOC_DISABLE_SHIFT = 4, + UOC_DISABLE_MASK = 1 << UOC_DISABLE_SHIFT, + + COMMON_ON_N_SHIFT = 0, + COMMON_ON_N_MASK = 1 << COMMON_ON_N_SHIFT, +}; + +/* GRF_UOC_CON2 */ +enum { + SOFT_CON_SEL_SHIFT = 2, + SOFT_CON_SEL_MASK = 1 << SOFT_CON_SEL_SHIFT, +}; + +/* GRF_UOC0_CON3 */ +enum { + BYPASSSEL_SHIFT = 7, + BYPASSSEL_MASK = 1 << BYPASSSEL_SHIFT, + + BYPASSDMEN_SHIFT = 6, + BYPASSDMEN_MASK = 1 << BYPASSDMEN_SHIFT, + + TERMSEL_FULLSPEED_SHIFT = 5, + TERMSEL_FULLSPEED_MASK = 1 << TERMSEL_FULLSPEED_SHIFT, + + XCVRSELECT_SHIFT = 3, + XCVRSELECT_FSTRANSC = 1, + XCVRSELECT_MASK = 3 << XCVRSELECT_SHIFT, + + OPMODE_SHIFT = 1, + OPMODE_NODRIVING = 1, + OPMODE_MASK = 3 << OPMODE_SHIFT, + + SUSPENDN_SHIFT = 0, + SUSPENDN_MASK = 1 << SUSPENDN_SHIFT, +}; + #endif diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 3ad2887575..d9bb1add87 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -89,6 +89,26 @@ int arch_cpu_init(void) rk_clrreg(&grf->soc_con0, 1 << 12);
rk3288_qos_init(); + + if (IS_ENABLED(CONFIG_ROCKCHIP_USB_UART)) { + rk_clrsetreg(&grf->uoc0_con[0], + SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK, + 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT | + 1 << COMMON_ON_N_SHIFT); + rk_clrsetreg(&grf->uoc0_con[2], + SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT); + rk_clrsetreg(&grf->uoc0_con[3], + OPMODE_MASK | XCVRSELECT_MASK | + TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK, + OPMODE_NODRIVING << OPMODE_SHIFT | + XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT | + 1 << TERMSEL_FULLSPEED_SHIFT | + 1 << SUSPENDN_SHIFT); + rk_clrsetreg(&grf->uoc0_con[3], + BYPASSSEL_MASK | BYPASSDMEN_MASK, + 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT); + } + #endif
return 0;
On Thu, 22 Sept 2022 at 00:47, Marty E. Plummer hanetzer@startmail.com wrote:
Code snagged from rk3188's u-boot implementation and the linux kernel's implementation of rockchip.usb_uart=1 Tested on rk3288-veyron-speedy
patman/checkpatch.pl doesn't like my indentation here and I can't quite figure out what it actually wants. Complaint is: arch/arm/mach-rockchip/rk3288/rk3288.c:95: check: Alignment should match open parenthesis arch/arm/mach-rockchip/rk3288/rk3288.c:99: check: Alignment should match open parenthesis arch/arm/mach-rockchip/rk3288/rk3288.c:101: check: Alignment should match open parenthesis arch/arm/mach-rockchip/rk3288/rk3288.c:108: check: Alignment should match open parenthesis
Signed-off-by: Marty E. Plummer hanetzer@startmail.com
.../include/asm/arch-rockchip/grf_rk3288.h | 41 +++++++++++++++++++ arch/arm/mach-rockchip/rk3288/rk3288.c | 20 +++++++++ 2 files changed, 61 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
(see below)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 894d3a40b0..d94cd9a27a 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -1152,4 +1152,45 @@ enum GPIO_BIAS { #define GPIO_PULL_MASK 0x3 #define GPIO_PULL_SHIFT(x) ((x) * 2)
+/* GRF_UOC_CON0 */ +enum {
SIDDQ_SHIFT = 13,SIDDQ_MASK = 1 << SIDDQ_SHIFT,UOC_DISABLE_SHIFT = 4,UOC_DISABLE_MASK = 1 << UOC_DISABLE_SHIFT,COMMON_ON_N_SHIFT = 0,COMMON_ON_N_MASK = 1 << COMMON_ON_N_SHIFT,+};
+/* GRF_UOC_CON2 */ +enum {
SOFT_CON_SEL_SHIFT = 2,SOFT_CON_SEL_MASK = 1 << SOFT_CON_SEL_SHIFT,+};
+/* GRF_UOC0_CON3 */ +enum {
BYPASSSEL_SHIFT = 7,BYPASSSEL_MASK = 1 << BYPASSSEL_SHIFT,BYPASSDMEN_SHIFT = 6,BYPASSDMEN_MASK = 1 << BYPASSDMEN_SHIFT,TERMSEL_FULLSPEED_SHIFT = 5,TERMSEL_FULLSPEED_MASK = 1 << TERMSEL_FULLSPEED_SHIFT,XCVRSELECT_SHIFT = 3,XCVRSELECT_FSTRANSC = 1,XCVRSELECT_MASK = 3 << XCVRSELECT_SHIFT,OPMODE_SHIFT = 1,OPMODE_NODRIVING = 1,OPMODE_MASK = 3 << OPMODE_SHIFT,SUSPENDN_SHIFT = 0,SUSPENDN_MASK = 1 << SUSPENDN_SHIFT,+};
#endif diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 3ad2887575..d9bb1add87 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -89,6 +89,26 @@ int arch_cpu_init(void) rk_clrreg(&grf->soc_con0, 1 << 12);
rk3288_qos_init();
if (IS_ENABLED(CONFIG_ROCKCHIP_USB_UART)) {rk_clrsetreg(&grf->uoc0_con[0],SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
S shold line up with &
1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |1 << COMMON_ON_N_SHIFT);rk_clrsetreg(&grf->uoc0_con[2],SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);rk_clrsetreg(&grf->uoc0_con[3],OPMODE_MASK | XCVRSELECT_MASK |TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,OPMODE_NODRIVING << OPMODE_SHIFT |XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |1 << TERMSEL_FULLSPEED_SHIFT |1 << SUSPENDN_SHIFT);rk_clrsetreg(&grf->uoc0_con[3],BYPASSSEL_MASK | BYPASSDMEN_MASK,1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);}#endif
return 0;-- 2.37.3
Not even used as far as I can see, but still.
Signed-off-by: Marty E. Plummer hanetzer@startmail.com ---
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index dd89cd2050..658cc0dfc4 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -466,7 +466,7 @@ enum { /* GRF_GPIO4C_IOMUX */ GRF_GPIO4C0_SEL_SHIFT = 0, GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT, - GRF_UART2DGBB_SIN = 2, + GRF_UART2DBGB_SIN = 2, GRF_HDMII2C_SCL = 3, GRF_GPIO4C1_SEL_SHIFT = 2, GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
On Thu, 22 Sept 2022 at 00:47, Marty E. Plummer hanetzer@startmail.com wrote:
Not even used as far as I can see, but still.
Signed-off-by: Marty E. Plummer hanetzer@startmail.com
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index dd89cd2050..658cc0dfc4 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -466,7 +466,7 @@ enum { /* GRF_GPIO4C_IOMUX */ GRF_GPIO4C0_SEL_SHIFT = 0, GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
GRF_UART2DGBB_SIN = 2,
GRF_UART2DBGB_SIN = 2, GRF_HDMII2C_SCL = 3, GRF_GPIO4C1_SEL_SHIFT = 2, GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,-- 2.37.3
The meat of my problem. rk3399 has the ability to redirect uart2 to sdcard pins. This setup half works; I can push input into the uart, but not see output.
Signed-off-by: Marty E. Plummer hanetzer@startmail.com
---
arch/arm/dts/rk3399-gru.dtsi | 7 ++----- arch/arm/dts/rk3399.dtsi | 4 ++-- .../arm/include/asm/arch-rockchip/grf_rk3399.h | 3 +++ arch/arm/mach-rockchip/rk3399/rk3399.c | 18 +++++++++--------- 4 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index b80f19066b..8c87c1cf19 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -510,7 +510,7 @@ ap_i2c_audio: &i2c8 { };
&sdmmc { - status = "okay"; + status = "disabled";
/* * Note: configure "sdmmc_cd" as card detect even though it's actually @@ -520,14 +520,11 @@ ap_i2c_audio: &i2c8 { * turned on that the system will still make sure the port is * configured as SDMMC and not JTAG. */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin - &sdmmc_bus4>;
bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + // cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; disable-wp; sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 3871c7fd83..55d5ee15be 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -638,7 +638,7 @@ reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; - pinctrl-0 = <&uart2c_xfer>; + pinctrl-0 = <&uart2a_xfer>; status = "disabled"; };
@@ -2571,7 +2571,7 @@ uart2a_xfer: uart2a-xfer { rockchip,pins = <4 RK_PB0 2 &pcfg_pull_up>, - <4 RK_PB1 2 &pcfg_pull_none>; + <4 RK_PB1 2 &pcfg_pull_up>; }; };
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index 658cc0dfc4..e1bfa31af7 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -554,6 +554,9 @@ enum { /* GRF_SOC_CON7 */ GRF_UART_DBG_SEL_SHIFT = 10, GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, + // assumptions, none of this is documented in the TRM as far as I can see + GRF_UART_DBG_SEL_A = 0, + GRF_UART_DBG_SEL_B = 1, GRF_UART_DBG_SEL_C = 2,
/* GRF_SOC_CON20 */ diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 21db03b961..7d35e524dc 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -157,17 +157,17 @@ void board_debug_uart_init(void) GPIO_PULL_NORMAL); }
- /* Enable early UART2 channel C on the RK3399 */ - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C3_SEL_MASK, - GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C4_SEL_MASK, - GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); - /* Set channel C as UART2 input */ + /* Enable early UART2 channel A on the RK3399 */ + rk_clrsetreg(&grf->gpio4b_iomux, + GRF_GPIO4B0_SEL_MASK, + GRF_UART2DBGA_SIN << GRF_GPIO4B0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio4b_iomux, + GRF_GPIO4B1_SEL_MASK, + GRF_UART2DBGA_SOUT << GRF_GPIO4B0_SEL_SHIFT); + /* Set channel A as UART2 input */ rk_clrsetreg(&grf->soc_con7, GRF_UART_DBG_SEL_MASK, - GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); + GRF_UART_DBG_SEL_A << GRF_UART_DBG_SEL_SHIFT); #endif } #endif
Hi Marty,
On Thu, 22 Sept 2022 at 00:47, Marty E. Plummer hanetzer@startmail.com wrote:
The meat of my problem. rk3399 has the ability to redirect uart2 to sdcard pins. This setup half works; I can push input into the uart, but not see output.
Signed-off-by: Marty E. Plummer hanetzer@startmail.com
arch/arm/dts/rk3399-gru.dtsi | 7 ++----- arch/arm/dts/rk3399.dtsi | 4 ++-- .../arm/include/asm/arch-rockchip/grf_rk3399.h | 3 +++ arch/arm/mach-rockchip/rk3399/rk3399.c | 18 +++++++++--------- 4 files changed, 16 insertions(+), 16 deletions(-)
Perhaps the C code could be behind a Kconfig, with a comment about how to change the DT?
Regards, Simon
On Wed, Sep 28, 2022 at 04:20:37AM -0600, Simon Glass wrote:
Hi Marty,
On Thu, 22 Sept 2022 at 00:47, Marty E. Plummer hanetzer@startmail.com wrote:
The meat of my problem. rk3399 has the ability to redirect uart2 to sdcard pins. This setup half works; I can push input into the uart, but not see output.
Signed-off-by: Marty E. Plummer hanetzer@startmail.com
arch/arm/dts/rk3399-gru.dtsi | 7 ++----- arch/arm/dts/rk3399.dtsi | 4 ++-- .../arm/include/asm/arch-rockchip/grf_rk3399.h | 3 +++ arch/arm/mach-rockchip/rk3399/rk3399.c | 18 +++++++++--------- 4 files changed, 16 insertions(+), 16 deletions(-)
Perhaps the C code could be behind a Kconfig, with a comment about how to change the DT?
Maybe if I do end up making this up for mainline inclusion, sure, but as of right now I just wanna get some console output to see why things aren't booting properly, so looking for dirty hax to work with for now.
Regards, Simon
participants (2)
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Marty E. Plummer -
Simon Glass