[U-Boot] [PATCH] Coldfire: I2C: Update I2CFDR frequency divider 0x0E value from 192 to 204
From 9a7a9dfb1ed367b275bc19f7c40c98b63de75fb2 Mon Sep 17 00:00:00 2001 From: Richard Retanubun RichardRetanubun@RuggedCom.com Date: Wed, 18 Mar 2009 12:52:35 -0400 Subject: [PATCH] Update I2CFDR frequency divider 0x0E value from 192 to 204.
This patch changes the divider factor of 14 for I2CFDR. Through empirical experiments on a M5271EVB with a 25MHz osc, multiplied to 75MHz system frequency, the divider 0x0E that is supposed to be div-by-192, results in i2c clock of ~376 KHz (which is ~div-by-204). Using the alternate divider for div-by-192 (49) results in an i2c clock of ~390 KHz, a better clock approximation.
Signed-off-by: Richard Retanubun RichardRetanubun@RuggedCom.com --- drivers/i2c/fsl_i2c.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index ce646fd..c61bf84 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -113,8 +113,8 @@ static const struct { {56, 41}, {64, 42}, {68, 7}, {72, 43}, {80, 8}, {80, 44}, {88, 9}, {96, 41}, {104, 10}, {112, 42}, {128, 11}, {128, 43}, - {144, 12}, {160, 13}, {160, 48}, {192, 14}, - {192, 49}, {224, 50}, {240, 15}, {256, 51}, + {144, 12}, {160, 13}, {160, 48}, {192, 49}, + {204, 14}, {224, 50}, {240, 15}, {256, 51}, {288, 16}, {320, 17}, {320, 52}, {384, 18}, {384, 53}, {448, 54}, {480, 19}, {512, 55}, {576, 20}, {640, 21}, {640, 56}, {768, 22},
On Mar 18, 2009, at 12:07 PM, Richard Retanubun wrote:
From 9a7a9dfb1ed367b275bc19f7c40c98b63de75fb2 Mon Sep 17 00:00:00 2001 From: Richard Retanubun RichardRetanubun@RuggedCom.com Date: Wed, 18 Mar 2009 12:52:35 -0400 Subject: [PATCH] Update I2CFDR frequency divider 0x0E value from 192 to 204.
This patch changes the divider factor of 14 for I2CFDR. Through empirical experiments on a M5271EVB with a 25MHz osc, multiplied to 75MHz system frequency, the divider 0x0E that is supposed to be div-by-192, results in i2c clock of ~376 KHz (which is ~div-by-204). Using the alternate divider for div-by-192 (49) results in an i2c clock of ~390 KHz, a better clock approximation.
Signed-off-by: Richard Retanubun RichardRetanubun@RuggedCom.com
drivers/i2c/fsl_i2c.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index ce646fd..c61bf84 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -113,8 +113,8 @@ static const struct { {56, 41}, {64, 42}, {68, 7}, {72, 43}, {80, 8}, {80, 44}, {88, 9}, {96, 41}, {104, 10}, {112, 42}, {128, 11}, {128, 43},
- {144, 12}, {160, 13}, {160, 48}, {192, 14},
- {192, 49}, {224, 50}, {240, 15}, {256, 51},
- {144, 12}, {160, 13}, {160, 48}, {192, 49},
- {204, 14}, {224, 50}, {240, 15}, {256, 51}, {288, 16}, {320, 17}, {320, 52}, {384, 18}, {384, 53}, {448, 54}, {480, 19}, {512, 55}, {576, 20}, {640, 21}, {640, 56}, {768, 22},
-- 1.5.6.5
I'm considered about the impact of this change on PPC boards since they share the driver. I believe Timur had some experience with this. Not sure if the change should be #ifdef M68K or not.
- k
On Mar 18, 2009, at 1:04 PM, Richard Retanubun wrote:
I'm considered about the impact of this change on PPC boards since they share the driver. I believe Timur had some experience with this. Not sure if the change should be #ifdef M68K or not.
it is already #ifdef M68k :)
than ignore me, clearly not enough context in the patch :)
- k
Hello Richard,
Richard Retanubun wrote:
From 9a7a9dfb1ed367b275bc19f7c40c98b63de75fb2 Mon Sep 17 00:00:00 2001 From: Richard Retanubun RichardRetanubun@RuggedCom.com Date: Wed, 18 Mar 2009 12:52:35 -0400 Subject: [PATCH] Update I2CFDR frequency divider 0x0E value from 192 to 204.
This patch changes the divider factor of 14 for I2CFDR. Through empirical experiments on a M5271EVB with a 25MHz osc, multiplied to 75MHz system frequency, the divider 0x0E that is supposed to be div-by-192, results in i2c clock of ~376 KHz (which is ~div-by-204). Using the alternate divider for div-by-192 (49) results in an i2c clock of ~390 KHz, a better clock approximation.
Signed-off-by: Richard Retanubun RichardRetanubun@RuggedCom.com
drivers/i2c/fsl_i2c.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index ce646fd..c61bf84 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -113,8 +113,8 @@ static const struct { {56, 41}, {64, 42}, {68, 7}, {72, 43}, {80, 8}, {80, 44}, {88, 9}, {96, 41}, {104, 10}, {112, 42}, {128, 11}, {128, 43},
- {144, 12}, {160, 13}, {160, 48}, {192, 14},
- {192, 49}, {224, 50}, {240, 15}, {256, 51},
- {144, 12}, {160, 13}, {160, 48}, {192, 49},
- {204, 14}, {224, 50}, {240, 15}, {256, 51}, {288, 16}, {320, 17}, {320, 52}, {384, 18}, {384, 53}, {448, 54}, {480, 19}, {512, 55}, {576, 20}, {640, 21}, {640, 56}, {768, 22},
Because I think this will go through the coldfire tree, you have my:
Acked-by: Heiko Schocher hs@denx.de
bye Heiko
Richard,
Nak.
The divider and fdr value are predefined in the 5271 reference manual.
The bus clock is 50Mhz and the CONFIG_SYS_I2C_SPEED is set to 80000.
divider = min(i2c_clk / speed, (unsigned short) -1); divider = 50000000 / 80000; = 625
if (fsl_i2c_speed_map[i].divider >= divider), here is looking for any divider that is larger or equal to 625. {640, 21} is the closer match.
Regards, TsiChung
On Thu, Mar 19, 2009 at 2:47 AM, Heiko Schocher hs@denx.de wrote:
Hello Richard,
Richard Retanubun wrote:
From 9a7a9dfb1ed367b275bc19f7c40c98b63de75fb2 Mon Sep 17 00:00:00 2001 From: Richard Retanubun RichardRetanubun@RuggedCom.com Date: Wed, 18 Mar 2009 12:52:35 -0400 Subject: [PATCH] Update I2CFDR frequency divider 0x0E value from 192 to 204.
This patch changes the divider factor of 14 for I2CFDR. Through empirical experiments on a M5271EVB with a 25MHz osc, multiplied to 75MHz system frequency, the divider 0x0E that is supposed to be div-by-192, results in i2c clock of ~376 KHz (which is ~div-by-204). Using the alternate divider for div-by-192 (49) results in an i2c clock of ~390 KHz, a better clock approximation.
Signed-off-by: Richard Retanubun RichardRetanubun@RuggedCom.com
drivers/i2c/fsl_i2c.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index ce646fd..c61bf84 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -113,8 +113,8 @@ static const struct { {56, 41}, {64, 42}, {68, 7}, {72, 43}, {80, 8}, {80, 44}, {88, 9}, {96, 41}, {104, 10}, {112, 42}, {128, 11}, {128, 43},
- {144, 12}, {160, 13}, {160, 48}, {192, 14},
- {192, 49}, {224, 50}, {240, 15}, {256, 51},
- {144, 12}, {160, 13}, {160, 48}, {192, 49},
- {204, 14}, {224, 50}, {240, 15}, {256, 51},
{288, 16}, {320, 17}, {320, 52}, {384, 18}, {384, 53}, {448, 54}, {480, 19}, {512, 55}, {576, 20}, {640, 21}, {640, 56}, {768, 22},
Because I think this will go through the coldfire tree, you have my:
Acked-by: Heiko Schocher hs@denx.de
bye Heiko
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Hi TC,
Richard,
Nak.
The divider and fdr value are predefined in the 5271 reference manual.
I know, that's why I said this is empirical evidence, not mathematical :)
The bus clock is 50Mhz and the CONFIG_SYS_I2C_SPEED is set to 80000.
This is the default for the M5271EVB, yes, but I've modded mine to have the bus clock at 75 MHz, and CONFIG_SYS_I2C_SPEED set to 4000000 (bus clock 75MHz being the Max speed supported by the M5271).
What I observed is that although there are two divider value that claims to divide by 192 (namely {192, 14} and {192, 49}, my empirical experiments shows that for the setup described above, 49 (listed after 14, and never picked) results in a closer approximation. So we have two options:
1. Reorder the table entry so that {192, 49} is listed before {192, 14} and hence picked. (this is confusing though) 2. Assign 14 to a value it is observed to divide by (div-by-204) in the setup I described above. 3. Remove the {192, 14} entry, so that {192, 49} is picked. (this does not match the documentation)
I opted for the 2nd option because having two identical divider entries and having only the first one listed picked seems redundant.
I am not claiming that the divider value that I assign from {192, 14} to {204, 14} will be true for ALL i2c controllers in all Coldfires, that depends if the same circuit and silicon is stamped on them, I was hoping that the freescale folks can help us with that :)
Regards,
- Richard
participants (4)
-
Heiko Schocher -
Kumar Gala -
Richard Retanubun -
TC Liew