[PATCH v2 01/15] firmware: zynqmp: Check if rx channel dev pointer is valid
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Check if rx channel dev pointer is valid and not if the address of the pointer is valid.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com ---
(no changes since v1)
drivers/firmware/firmware-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 0f0d2b07c0..341d7cf135 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -92,7 +92,7 @@ static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) res_maxlen > PMUFW_PAYLOAD_ARG_CNT) return -EINVAL;
- if (!(zynqmp_power.tx_chan.dev) || !(&zynqmp_power.rx_chan.dev)) + if (!(zynqmp_power.tx_chan.dev) || !(zynqmp_power.rx_chan.dev)) return -EINVAL;
debug("%s, Sending IPI message with ID: 0x%0x\n", __func__, req[0]);
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Probe the driver before use to ensure that the driver is always available and the global data are valid. Initialize the global data with zero and probe the driver if the global data are still zero. This allows a usage of the firmware functions from other drivers with arbitrary order between the drivers.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
---
Changes in v2: - Call probe only if drivers isn't initialized
drivers/firmware/firmware-zynqmp.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 341d7cf135..b0cd647aa5 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -26,7 +26,7 @@ struct zynqmp_power { struct mbox_chan tx_chan; struct mbox_chan rx_chan; -} zynqmp_power; +} zynqmp_power = {};
#define NODE_ID_LOCATION 5
@@ -79,6 +79,20 @@ int zynqmp_pmufw_node(u32 id) return 0; }
+static int do_pm_probe(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_FIRMWARE, + DM_DRIVER_GET(zynqmp_power), + &dev); + if (ret) + debug("%s: Probing device failed: %d\n", __func__, ret); + + return ret; +} + static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) { struct zynqmp_ipi_msg msg; @@ -92,8 +106,11 @@ static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) res_maxlen > PMUFW_PAYLOAD_ARG_CNT) return -EINVAL;
- if (!(zynqmp_power.tx_chan.dev) || !(zynqmp_power.rx_chan.dev)) - return -EINVAL; + if (!(zynqmp_power.tx_chan.dev) || !(zynqmp_power.rx_chan.dev)) { + ret = do_pm_probe(); + if (ret) + return ret; + }
debug("%s, Sending IPI message with ID: 0x%0x\n", __func__, req[0]); msg.buf = (u32 *)req;
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Replace strncat with strlcat to always produce a valid null-terminated string.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
---
Changes in v2: - New commit
board/xilinx/zynqmp/zynqmp.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index e311aa772c..9dfa4643fb 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -282,13 +282,13 @@ static char *zynqmp_get_silicon_idcode_name(void) */ switch (family) { case 0x00: - strncat(name, "ev", 2); + strlcat(name, "ev", sizeof(name)); break; case 0x10: - strncat(name, "eg", 2); + strlcat(name, "eg", sizeof(name)); break; case 0x11: - strncat(name, "cg", 2); + strlcat(name, "cg", sizeof(name)); break; default: /* Do not append family name*/ @@ -300,16 +300,17 @@ static char *zynqmp_get_silicon_idcode_name(void) * read. So, ignore the bit and just findout if it is CG * or EG/EV variant. */ - strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : - "e", 2); + strlcat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : + "e", sizeof(name)); } } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) { /* Devices with CG variant might be EG or CG family */ - strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2); + strlcat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", + sizeof(name)); } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) { - strncat(name, "eg", 2); + strlcat(name, "eg", sizeof(name)); } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) { - strncat(name, "dr", 2); + strlcat(name, "dr", sizeof(name)); } else { debug("Variant not identified\n"); }
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Add a macro for the device type mask of the id code.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
---
Changes in v2: - New commit
board/xilinx/zynqmp/zynqmp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 9dfa4643fb..1a7383d023 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -49,6 +49,7 @@ #define EFUSE_VCU_DIS_SHIFT 8 #define EFUSE_GPU_DIS_MASK 0x20 #define EFUSE_GPU_DIS_SHIFT 5 +#define IDCODE_DEV_TYPE_MASK GENMASK(27, 0) #define IDCODE2_PL_INIT_MASK 0x200 #define IDCODE2_PL_INIT_SHIFT 9
@@ -218,7 +219,7 @@ static char *zynqmp_detect_svd_name(u32 idcode) u32 i;
for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) { - if (zynqmp_svd_devices[i].id == (idcode & 0x0FFFFFFF)) + if (zynqmp_svd_devices[i].id == (idcode & IDCODE_DEV_TYPE_MASK)) return zynqmp_svd_devices[i].name; }
@@ -254,7 +255,7 @@ static char *zynqmp_get_silicon_idcode_name(void) idcode2);
for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { - if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF)) + if (zynqmp_devices[i].id == (idcode & IDCODE_DEV_TYPE_MASK)) break; }
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Reuse the shift macros to define the masks.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
---
Changes in v2: - New commit
board/xilinx/zynqmp/zynqmp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 1a7383d023..56bb01335d 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -45,13 +45,13 @@ #include "pm_cfg_obj.h"
#define ZYNQMP_VERSION_SIZE 7 -#define EFUSE_VCU_DIS_MASK 0x100 #define EFUSE_VCU_DIS_SHIFT 8 -#define EFUSE_GPU_DIS_MASK 0x20 +#define EFUSE_VCU_DIS_MASK BIT(EFUSE_VCU_DIS_SHIFT) #define EFUSE_GPU_DIS_SHIFT 5 +#define EFUSE_GPU_DIS_MASK BIT(EFUSE_GPU_DIS_SHIFT) #define IDCODE_DEV_TYPE_MASK GENMASK(27, 0) -#define IDCODE2_PL_INIT_MASK 0x200 #define IDCODE2_PL_INIT_SHIFT 9 +#define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT)
DECLARE_GLOBAL_DATA_PTR;
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Merge the svd / xck devices into to the common zynqmp device list.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
---
Changes in v2: - New commit
board/xilinx/zynqmp/zynqmp.c | 54 ++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 30 deletions(-)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 56bb01335d..1f18fb3473 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -65,11 +65,13 @@ enum { ZYNQMP_VARIANT_DR = BIT(3U), };
-static const struct { +struct zynqmp_device { u32 id; u8 device; u8 variants; -} zynqmp_devices[] = { +}; + +static const struct zynqmp_device zynqmp_devices[] = { { .id = 0x04688093, .device = 1, @@ -198,37 +200,33 @@ static const struct { .device = 67, .variants = ZYNQMP_VARIANT_DR, }, -}; - -static const struct { - u32 id; - char *name; -} zynqmp_svd_devices[] = { { .id = 0x04714093, - .name = "xck24" + .device = 24, + .variants = 0, }, { .id = 0x04724093, - .name = "xck26", + .device = 26, + .variants = 0, }, };
-static char *zynqmp_detect_svd_name(u32 idcode) +static const struct zynqmp_device *zynqmp_get_device(u32 idcode) { - u32 i; + idcode &= IDCODE_DEV_TYPE_MASK;
- for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) { - if (zynqmp_svd_devices[i].id == (idcode & IDCODE_DEV_TYPE_MASK)) - return zynqmp_svd_devices[i].name; + for (int i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { + if (zynqmp_devices[i].id == idcode) + return &zynqmp_devices[i]; }
- return "unknown"; + return NULL; }
static char *zynqmp_get_silicon_idcode_name(void) { - u32 i; + const struct zynqmp_device *device; u32 idcode, idcode2; char name[ZYNQMP_VERSION_SIZE]; u32 ret_payload[PAYLOAD_ARG_CNT]; @@ -254,21 +252,17 @@ static char *zynqmp_get_silicon_idcode_name(void) debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode, idcode2);
- for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { - if (zynqmp_devices[i].id == (idcode & IDCODE_DEV_TYPE_MASK)) - break; - } - - if (i >= ARRAY_SIZE(zynqmp_devices)) - return zynqmp_detect_svd_name(idcode); + device = zynqmp_get_device(idcode); + if (!device) + return "unknown";
/* Add device prefix to the name */ - ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d", - zynqmp_devices[i].device); + ret = snprintf(name, ZYNQMP_VERSION_SIZE, "%s%d", + device->variants ? "zu" : "xck", device->device); if (ret < 0) return "unknown";
- if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) { + if (device->variants & ZYNQMP_VARIANT_EV) { /* Devices with EV variant might be EG/CG/EV family */ if (idcode2 & IDCODE2_PL_INIT_MASK) { u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >> @@ -304,13 +298,13 @@ static char *zynqmp_get_silicon_idcode_name(void) strlcat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "e", sizeof(name)); } - } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) { + } else if (device->variants & ZYNQMP_VARIANT_CG) { /* Devices with CG variant might be EG or CG family */ strlcat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", sizeof(name)); - } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) { + } else if (device->variants & ZYNQMP_VARIANT_EG) { strlcat(name, "eg", sizeof(name)); - } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) { + } else if (device->variants & ZYNQMP_VARIANT_DR) { strlcat(name, "dr", sizeof(name)); } else { debug("Variant not identified\n");
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Remove the redundant SPL and CurrentEL checks for the zynqmp_mmio_read function call because the function itself runs the same checks.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
---
Changes in v2: - New commit
drivers/soc/soc_xilinx_zynqmp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index a71115b17c..563d93da24 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -54,8 +54,7 @@ static int soc_xilinx_zynqmp_probe(struct udevice *dev)
priv->family = zynqmp_family;
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3 || - !IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) + if (!IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) ret = zynqmp_mmio_read(ZYNQMP_PS_VERSION, &ret_payload[2]); else ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Add machine identification support based on the zynqmp_get_silicon_idcode_name function and use the soc_get_machine function of the soc uclass to get silicon idcode name for the fpga init.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
---
Changes in v2: - Move zynqmp_family to its old place - Remove empty line after zynqmp_get_device - Add const to zynqmp_devices - Merge with 'xilinx: zynqmp: Use soc machine function to get silicon idcode name' patch
board/xilinx/zynqmp/zynqmp.c | 283 ++------------------------------ drivers/soc/soc_xilinx_zynqmp.c | 283 ++++++++++++++++++++++++++++++++ 2 files changed, 298 insertions(+), 268 deletions(-)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 1f18fb3473..06f6dbab18 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -19,6 +19,7 @@ #include <sata.h> #include <ahci.h> #include <scsi.h> +#include <soc.h> #include <malloc.h> #include <memalign.h> #include <wdt.h> @@ -44,274 +45,10 @@
#include "pm_cfg_obj.h"
-#define ZYNQMP_VERSION_SIZE 7 -#define EFUSE_VCU_DIS_SHIFT 8 -#define EFUSE_VCU_DIS_MASK BIT(EFUSE_VCU_DIS_SHIFT) -#define EFUSE_GPU_DIS_SHIFT 5 -#define EFUSE_GPU_DIS_MASK BIT(EFUSE_GPU_DIS_SHIFT) -#define IDCODE_DEV_TYPE_MASK GENMASK(27, 0) -#define IDCODE2_PL_INIT_SHIFT 9 -#define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT) - DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; - -enum { - ZYNQMP_VARIANT_EG = BIT(0U), - ZYNQMP_VARIANT_EV = BIT(1U), - ZYNQMP_VARIANT_CG = BIT(2U), - ZYNQMP_VARIANT_DR = BIT(3U), -}; - -struct zynqmp_device { - u32 id; - u8 device; - u8 variants; -}; - -static const struct zynqmp_device zynqmp_devices[] = { - { - .id = 0x04688093, - .device = 1, - .variants = ZYNQMP_VARIANT_EG, - }, - { - .id = 0x04711093, - .device = 2, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, - }, - { - .id = 0x04710093, - .device = 3, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, - }, - { - .id = 0x04721093, - .device = 4, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | - ZYNQMP_VARIANT_EV, - }, - { - .id = 0x04720093, - .device = 5, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | - ZYNQMP_VARIANT_EV, - }, - { - .id = 0x04739093, - .device = 6, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, - }, - { - .id = 0x04730093, - .device = 7, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | - ZYNQMP_VARIANT_EV, - }, - { - .id = 0x04738093, - .device = 9, - .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, - }, - { - .id = 0x04740093, - .device = 11, - .variants = ZYNQMP_VARIANT_EG, - }, - { - .id = 0x04750093, - .device = 15, - .variants = ZYNQMP_VARIANT_EG, - }, - { - .id = 0x04759093, - .device = 17, - .variants = ZYNQMP_VARIANT_EG, - }, - { - .id = 0x04758093, - .device = 19, - .variants = ZYNQMP_VARIANT_EG, - }, - { - .id = 0x047E1093, - .device = 21, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E3093, - .device = 23, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E5093, - .device = 25, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E4093, - .device = 27, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E0093, - .device = 28, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E2093, - .device = 29, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047E6093, - .device = 39, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047FD093, - .device = 43, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047F8093, - .device = 46, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047FF093, - .device = 47, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047FB093, - .device = 48, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x047FE093, - .device = 49, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x046d0093, - .device = 67, - .variants = ZYNQMP_VARIANT_DR, - }, - { - .id = 0x04714093, - .device = 24, - .variants = 0, - }, - { - .id = 0x04724093, - .device = 26, - .variants = 0, - }, -}; - -static const struct zynqmp_device *zynqmp_get_device(u32 idcode) -{ - idcode &= IDCODE_DEV_TYPE_MASK; - - for (int i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { - if (zynqmp_devices[i].id == idcode) - return &zynqmp_devices[i]; - } - - return NULL; -} - -static char *zynqmp_get_silicon_idcode_name(void) -{ - const struct zynqmp_device *device; - u32 idcode, idcode2; - char name[ZYNQMP_VERSION_SIZE]; - u32 ret_payload[PAYLOAD_ARG_CNT]; - int ret; - - ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload); - if (ret) { - debug("%s: Getting chipid failed\n", __func__); - return "unknown"; - } - - /* - * Firmware returns: - * payload[0][31:0] = status of the operation - * payload[1]] = IDCODE - * payload[2][19:0] = Version - * payload[2][28:20] = EXTENDED_IDCODE - * payload[2][29] = PL_INIT - */ - - idcode = ret_payload[1]; - idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT; - debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode, - idcode2); - - device = zynqmp_get_device(idcode); - if (!device) - return "unknown"; - - /* Add device prefix to the name */ - ret = snprintf(name, ZYNQMP_VERSION_SIZE, "%s%d", - device->variants ? "zu" : "xck", device->device); - if (ret < 0) - return "unknown"; - - if (device->variants & ZYNQMP_VARIANT_EV) { - /* Devices with EV variant might be EG/CG/EV family */ - if (idcode2 & IDCODE2_PL_INIT_MASK) { - u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >> - EFUSE_VCU_DIS_SHIFT) << 1 | - ((idcode2 & EFUSE_GPU_DIS_MASK) >> - EFUSE_GPU_DIS_SHIFT); - - /* - * Get family name based on extended idcode values as - * determined on UG1087, EXTENDED_IDCODE register - * description - */ - switch (family) { - case 0x00: - strlcat(name, "ev", sizeof(name)); - break; - case 0x10: - strlcat(name, "eg", sizeof(name)); - break; - case 0x11: - strlcat(name, "cg", sizeof(name)); - break; - default: - /* Do not append family name*/ - break; - } - } else { - /* - * When PL powered down the VCU Disable efuse cannot be - * read. So, ignore the bit and just findout if it is CG - * or EG/EV variant. - */ - strlcat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : - "e", sizeof(name)); - } - } else if (device->variants & ZYNQMP_VARIANT_CG) { - /* Devices with CG variant might be EG or CG family */ - strlcat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", - sizeof(name)); - } else if (device->variants & ZYNQMP_VARIANT_EG) { - strlcat(name, "eg", sizeof(name)); - } else if (device->variants & ZYNQMP_VARIANT_DR) { - strlcat(name, "dr", sizeof(name)); - } else { - debug("Variant not identified\n"); - } - - return strdup(name); -} #endif
int __maybe_unused psu_uboot_init(void) @@ -402,6 +139,11 @@ static void print_secure_boot(void)
int board_init(void) { +#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) + struct udevice *soc; + char name[SOC_MAX_STR_SIZE]; + int ret; +#endif #if defined(CONFIG_ZYNQMP_FIRMWARE) struct udevice *dev;
@@ -428,10 +170,15 @@ int board_init(void) printf("EL Level:\tEL%d\n", current_el());
#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) - zynqmppl.name = zynqmp_get_silicon_idcode_name(); - printf("Chip ID:\t%s\n", zynqmppl.name); - fpga_init(); - fpga_add(fpga_xilinx, &zynqmppl); + ret = soc_get(&soc); + if (!ret) { + ret = soc_get_machine(soc, name, sizeof(name)); + if (ret >= 0) { + zynqmppl.name = strdup(name); + fpga_init(); + fpga_add(fpga_xilinx, &zynqmppl); + } + } #endif
/* display secure boot information */ diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index 563d93da24..c10fc7d444 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -3,10 +3,15 @@ * Xilinx ZynqMP SOC driver * * Copyright (C) 2021 Xilinx, Inc. + * Michal Simek michal.simek@xilinx.com + * + * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG + * Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com */
#include <common.h> #include <dm.h> +#include <dm/device_compat.h> #include <asm/cache.h> #include <soc.h> #include <zynqmp_firmware.h> @@ -22,11 +27,257 @@ */ static const char zynqmp_family[] = "ZynqMP";
+#define EFUSE_VCU_DIS_SHIFT 8 +#define EFUSE_VCU_DIS_MASK BIT(EFUSE_VCU_DIS_SHIFT) +#define EFUSE_GPU_DIS_SHIFT 5 +#define EFUSE_GPU_DIS_MASK BIT(EFUSE_GPU_DIS_SHIFT) +#define IDCODE_DEV_TYPE_MASK GENMASK(27, 0) +#define IDCODE2_PL_INIT_SHIFT 9 +#define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT) + +#define ZYNQMP_VERSION_SIZE 7 + +enum { + ZYNQMP_VARIANT_EG = BIT(0), + ZYNQMP_VARIANT_EV = BIT(1), + ZYNQMP_VARIANT_CG = BIT(2), + ZYNQMP_VARIANT_DR = BIT(3), +}; + +struct zynqmp_device { + u32 id; + u8 device; + u8 variants; +}; + struct soc_xilinx_zynqmp_priv { const char *family; + char machine[ZYNQMP_VERSION_SIZE]; char revision; };
+static const struct zynqmp_device zynqmp_devices[] = { + { + .id = 0x04688093, + .device = 1, + .variants = ZYNQMP_VARIANT_EG, + }, + { + .id = 0x04711093, + .device = 2, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, + }, + { + .id = 0x04710093, + .device = 3, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, + }, + { + .id = 0x04721093, + .device = 4, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | + ZYNQMP_VARIANT_EV, + }, + { + .id = 0x04720093, + .device = 5, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | + ZYNQMP_VARIANT_EV, + }, + { + .id = 0x04739093, + .device = 6, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, + }, + { + .id = 0x04730093, + .device = 7, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | + ZYNQMP_VARIANT_EV, + }, + { + .id = 0x04738093, + .device = 9, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, + }, + { + .id = 0x04740093, + .device = 11, + .variants = ZYNQMP_VARIANT_EG, + }, + { + .id = 0x04750093, + .device = 15, + .variants = ZYNQMP_VARIANT_EG, + }, + { + .id = 0x04759093, + .device = 17, + .variants = ZYNQMP_VARIANT_EG, + }, + { + .id = 0x04758093, + .device = 19, + .variants = ZYNQMP_VARIANT_EG, + }, + { + .id = 0x047E1093, + .device = 21, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E3093, + .device = 23, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E5093, + .device = 25, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E4093, + .device = 27, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E0093, + .device = 28, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E2093, + .device = 29, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047E6093, + .device = 39, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047FD093, + .device = 43, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047F8093, + .device = 46, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047FF093, + .device = 47, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047FB093, + .device = 48, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047FE093, + .device = 49, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x046d0093, + .device = 67, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x04714093, + .device = 24, + .variants = 0, + }, + { + .id = 0x04724093, + .device = 26, + .variants = 0, + }, +}; + +static const struct zynqmp_device *zynqmp_get_device(u32 idcode) +{ + idcode &= IDCODE_DEV_TYPE_MASK; + + for (int i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { + if (zynqmp_devices[i].id == idcode) + return &zynqmp_devices[i]; + } + + return NULL; +} + +static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode, + u32 idcode2) +{ + struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); + const struct zynqmp_device *device; + int ret; + + device = zynqmp_get_device(idcode); + if (!device) + return 0; + + /* Add device prefix to the name */ + ret = snprintf(priv->machine, sizeof(priv->machine), "%s%d", + device->variants ? "zu" : "xck", device->device); + if (ret < 0) + return ret; + + if (device->variants & ZYNQMP_VARIANT_EV) { + /* Devices with EV variant might be EG/CG/EV family */ + if (idcode2 & IDCODE2_PL_INIT_MASK) { + u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >> + EFUSE_VCU_DIS_SHIFT) << 1 | + ((idcode2 & EFUSE_GPU_DIS_MASK) >> + EFUSE_GPU_DIS_SHIFT); + + /* + * Get family name based on extended idcode values as + * determined on UG1087, EXTENDED_IDCODE register + * description + */ + switch (family) { + case 0x00: + strlcat(priv->machine, "ev", + sizeof(priv->machine)); + break; + case 0x10: + strlcat(priv->machine, "eg", + sizeof(priv->machine)); + break; + case 0x11: + strlcat(priv->machine, "cg", + sizeof(priv->machine)); + break; + default: + /* Do not append family name*/ + break; + } + } else { + /* + * When PL powered down the VCU Disable efuse cannot be + * read. So, ignore the bit and just findout if it is CG + * or EG/EV variant. + */ + strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ? + "cg" : "e", sizeof(priv->machine)); + } + } else if (device->variants & ZYNQMP_VARIANT_CG) { + /* Devices with CG variant might be EG or CG family */ + strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ? + "cg" : "eg", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_EG) { + strlcat(priv->machine, "eg", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_DR) { + strlcat(priv->machine, "dr", sizeof(priv->machine)); + } + + return 0; +} + static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size) { struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); @@ -34,6 +285,17 @@ static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size return snprintf(buf, size, "%s", priv->family); }
+int soc_xilinx_zynqmp_get_machine(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); + const char *machine = priv->machine; + + if (!machine[0]) + machine = "unknown"; + + return snprintf(buf, size, "%s", machine); +} + static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int size) { struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); @@ -44,6 +306,7 @@ static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int si static const struct soc_ops soc_xilinx_zynqmp_ops = { .get_family = soc_xilinx_zynqmp_get_family, .get_revision = soc_xilinx_zynqmp_get_revision, + .get_machine = soc_xilinx_zynqmp_get_machine, };
static int soc_xilinx_zynqmp_probe(struct udevice *dev) @@ -64,6 +327,26 @@ static int soc_xilinx_zynqmp_probe(struct udevice *dev)
priv->revision = ret_payload[2] & ZYNQMP_PS_VER_MASK;
+ if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + /* + * Firmware returns: + * payload[0][31:0] = status of the operation + * payload[1] = IDCODE + * payload[2][19:0] = Version + * payload[2][28:20] = EXTENDED_IDCODE + * payload[2][29] = PL_INIT + */ + u32 idcode = ret_payload[1]; + u32 idcode2 = ret_payload[2] >> + ZYNQMP_CSU_VERSION_EMPTY_SHIFT; + dev_dbg(dev, "IDCODE: 0x%0x, IDCODE2: 0x%0x\n", idcode, + idcode2); + + ret = soc_xilinx_zynqmp_detect_machine(dev, idcode, idcode2); + if (ret) + return ret; + } + return 0; }
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Print the soc machine in the print_cpuinfo function.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com ---
(no changes since v1)
board/xilinx/common/board.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 629a6ee036..402fa77006 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -506,6 +506,10 @@ int print_cpuinfo(void) if (ret) printf("Silicon: %s\n", name);
+ ret = soc_get_machine(soc, name, SOC_MAX_STR_SIZE); + if (ret) + printf("Chip: %s\n", name); + return 0; } #endif
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Move the print_cpuinfo function of CONFIG_DISPLAY_CPUINFO into its own source file to support reuse by other board vendors.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com ---
(no changes since v1)
board/xilinx/common/Makefile | 3 +++ board/xilinx/common/board.c | 29 ---------------------------- board/xilinx/common/cpu-info.c | 35 ++++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 29 deletions(-) create mode 100644 board/xilinx/common/cpu-info.c
diff --git a/board/xilinx/common/Makefile b/board/xilinx/common/Makefile index 212028478c..cdc3c96774 100644 --- a/board/xilinx/common/Makefile +++ b/board/xilinx/common/Makefile @@ -5,6 +5,9 @@ #
obj-y += board.o +ifndef CONFIG_ARCH_ZYNQ +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o +endif ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_FRU) += fru.o fru_ops.o endif diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 402fa77006..5f2afb9def 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -485,35 +485,6 @@ int __maybe_unused board_fit_config_name_match(const char *name) return -1; }
-#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_ARCH_ZYNQ) -int print_cpuinfo(void) -{ - struct udevice *soc; - char name[SOC_MAX_STR_SIZE]; - int ret; - - ret = soc_get(&soc); - if (ret) { - printf("CPU: UNKNOWN\n"); - return 0; - } - - ret = soc_get_family(soc, name, SOC_MAX_STR_SIZE); - if (ret) - printf("CPU: %s\n", name); - - ret = soc_get_revision(soc, name, SOC_MAX_STR_SIZE); - if (ret) - printf("Silicon: %s\n", name); - - ret = soc_get_machine(soc, name, SOC_MAX_STR_SIZE); - if (ret) - printf("Chip: %s\n", name); - - return 0; -} -#endif - #if CONFIG_IS_ENABLED(DTB_RESELECT) #define MAX_NAME_LENGTH 50
diff --git a/board/xilinx/common/cpu-info.c b/board/xilinx/common/cpu-info.c new file mode 100644 index 0000000000..4a863d00de --- /dev/null +++ b/board/xilinx/common/cpu-info.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2020 Xilinx, Inc. + * Michal Simek michal.simek@xilinx.com + */ + +#include <common.h> +#include <soc.h> + +int print_cpuinfo(void) +{ + struct udevice *soc; + char name[SOC_MAX_STR_SIZE]; + int ret; + + ret = soc_get(&soc); + if (ret) { + printf("CPU: UNKNOWN\n"); + return 0; + } + + ret = soc_get_family(soc, name, SOC_MAX_STR_SIZE); + if (ret) + printf("CPU: %s\n", name); + + ret = soc_get_revision(soc, name, SOC_MAX_STR_SIZE); + if (ret) + printf("Silicon: %s\n", name); + + ret = soc_get_machine(soc, name, SOC_MAX_STR_SIZE); + if (ret) + printf("Chip: %s\n", name); + + return 0; +}
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
The set_dfu_alt_info function use the CONFIG_SYS_SPI_U_BOOT_OFFS define to set the dfu_alt_info environment variable for qspi boot mode. Guard the usage of CONFIG_SYS_SPI_U_BOOT_OFFS to make spi flash support optional.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com ---
(no changes since v1)
board/xilinx/zynqmp/zynqmp.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 06f6dbab18..106c3953e1 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -667,6 +667,7 @@ void set_dfu_alt_info(char *interface, char *devstr) bootseq, multiboot, bootseq, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq); break; +#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: snprintf(buf, DFU_ALT_BUF_LEN, @@ -675,6 +676,7 @@ void set_dfu_alt_info(char *interface, char *devstr) multiboot * SZ_32K, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, CONFIG_SYS_SPI_U_BOOT_OFFS); break; +#endif default: return; }
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
There is no reason to do serial initialization. Uart driver does it already based on DT. Good effect is that it is clear which interface is console. The resulting change was done in past by commit 84d2bbf082fa ("arm64: zynqmp: Remove low level UART setting").
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com ---
(no changes since v1)
tools/zynqmp_psu_init_minimize.sh | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh index 4ee418f07e..31fbeac327 100755 --- a/tools/zynqmp_psu_init_minimize.sh +++ b/tools/zynqmp_psu_init_minimize.sh @@ -2,6 +2,8 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (C) 2018 Michal Simek michal.simek@xilinx.com # Copyright (C) 2019 Luca Ceresoli luca@lucaceresoli.net +# Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG +# Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
usage() { @@ -144,4 +146,19 @@ sed -i -r 's|((._code .= [x[:xdigit:]]+))|\1|g' ${TMP} # Convert back newlines tr "\r" "\n" <${TMP} >${OUT}
+# Remove unnecessary settings +# - Low level UART +SETTINGS_TO_REMOVE="0xFF000000 +0xFF000004 +0xFF000018 +0xFF000034 +0xFF010000 +0xFF010004 +0xFF010018 +0xFF010034 +" +for i in $SETTINGS_TO_REMOVE; do +sed -i "/^\tpsu_mask_write($i,.*$/d" ${OUT} +done + rm ${TMP}
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Use carriage return instead of line feed to support mangling across lines.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
---
Changes in v2: - New commit
tools/zynqmp_psu_init_minimize.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh index 31fbeac327..c0a7a89465 100755 --- a/tools/zynqmp_psu_init_minimize.sh +++ b/tools/zynqmp_psu_init_minimize.sh @@ -121,7 +121,7 @@ tr "\n" "\r" <${OUT} >${TMP} # | | ==> |while (e)| # | } | | ; | # | | -sed -i -r 's| {\r+(\t*)}\r\r|\n\1\t;\n|g' ${TMP} +sed -i -r 's| {\r+(\t*)}\r\r|\r\1\t;\r|g' ${TMP}
# Remove empty line between variable declaration sed -i -r 's|\r(\r\t(unsigned )?int )|\1|g' ${TMP}
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Move helper functions below header includes to avoid forward declarations.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
---
Changes in v2: - Remove forward declarations and move functions instead
tools/zynqmp_psu_init_minimize.sh | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh index c0a7a89465..16c622f6ce 100755 --- a/tools/zynqmp_psu_init_minimize.sh +++ b/tools/zynqmp_psu_init_minimize.sh @@ -143,6 +143,14 @@ sed -i -r 's| {(\r[^\r]*;)\r\t*}|\1|g' ${TMP} # if ((p_code >= 0x26) && ...) -> if (p_code >= 0x26 && ...) sed -i -r 's|((._code .= [x[:xdigit:]]+))|\1|g' ${TMP}
+# Move helper functions below header includes +TARGET="#include <xil_io.h>" +START="static int serdes_rst_seq" +END="static int serdes_enb_coarse_saturation" + +sed -i -e "s|(${TARGET}\r\r)(.*)(${START}(.*)(${END}()|\1\3\2\4|g" \ + ${TMP} + # Convert back newlines tr "\r" "\n" <${TMP} >${OUT}
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Move helper functions in psu_init files below header includes to avoid forward declarations.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
---
Changes in v2: - New commit
.../zynqmp-e-a2197-00-revA/psu_init_gpl.c | 3478 ++++++++--------- .../zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c | 3231 ++++++++------- .../zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c | 3231 ++++++++------- 3 files changed, 4961 insertions(+), 4979 deletions(-)
diff --git a/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c index 40d9279378..5ec327134b 100644 --- a/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c @@ -6,1866 +6,1858 @@ #include <asm/arch/psu_init_gpl.h> #include <xil_io.h>
-static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate); - -static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, - int d_lock_cnt, int d_lfhf, int d_cp, int d_res); - -static unsigned long psu_pll_init_data(void) +static int serdes_rst_seq(u32 pllsel, u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) { - psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000002U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); - psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); - psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); - psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); - psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000002U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); - psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000004U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); + Xil_Out32(0xFD410098, 0x00000000); + Xil_Out32(0xFD401010, 0x00000040); + Xil_Out32(0xFD405010, 0x00000040); + Xil_Out32(0xFD409010, 0x00000040); + Xil_Out32(0xFD40D010, 0x00000040); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + Xil_Out32(0xFD410098, 0x00000004); + mask_delay(50); + if (lane0_rate == 1) + Xil_Out32(0xFD410098, 0x0000000E); + Xil_Out32(0xFD410098, 0x00000006); + if (lane0_rate == 1) { + Xil_Out32(0xFD40000C, 0x00000004); + Xil_Out32(0xFD40400C, 0x00000004); + Xil_Out32(0xFD40800C, 0x00000004); + Xil_Out32(0xFD40C00C, 0x00000004); + Xil_Out32(0xFD410098, 0x00000007); + mask_delay(400); + Xil_Out32(0xFD40000C, 0x0000000C); + Xil_Out32(0xFD40400C, 0x0000000C); + Xil_Out32(0xFD40800C, 0x0000000C); + Xil_Out32(0xFD40C00C, 0x0000000C); + mask_delay(15); + Xil_Out32(0xFD410098, 0x0000000F); + mask_delay(100); + } + if (pllsel == 0) + mask_poll(0xFD4023E4, 0x00000010U); + if (pllsel == 1) + mask_poll(0xFD4063E4, 0x00000010U); + if (pllsel == 2) + mask_poll(0xFD40A3E4, 0x00000010U); + if (pllsel == 3) + mask_poll(0xFD40E3E4, 0x00000010U); + mask_delay(50); + Xil_Out32(0xFD401010, 0x000000C0); + Xil_Out32(0xFD405010, 0x000000C0); + Xil_Out32(0xFD409010, 0x000000C0); + Xil_Out32(0xFD40D010, 0x000000C0); + Xil_Out32(0xFD401010, 0x00000080); + Xil_Out32(0xFD405010, 0x00000080); + Xil_Out32(0xFD409010, 0x00000080); + Xil_Out32(0xFD40D010, 0x00000080);
+ Xil_Out32(0xFD402084, 0x000000C0); + Xil_Out32(0xFD406084, 0x000000C0); + Xil_Out32(0xFD40A084, 0x000000C0); + Xil_Out32(0xFD40E084, 0x000000C0); + mask_delay(50); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + mask_delay(50); + Xil_Out32(0xFD401010, 0x00000000); + Xil_Out32(0xFD405010, 0x00000000); + Xil_Out32(0xFD409010, 0x00000000); + Xil_Out32(0xFD40D010, 0x00000000); + Xil_Out32(0xFD402084, 0x00000000); + Xil_Out32(0xFD406084, 0x00000000); + Xil_Out32(0xFD40A084, 0x00000000); + Xil_Out32(0xFD40E084, 0x00000000); + mask_delay(500); return 1; }
-static unsigned long psu_clock_init_data(void) +static int serdes_bist_static_settings(u32 lane_active) { - psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U); - psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U); - psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U); - psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); - psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); - psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); - psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); - psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); - psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); - psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); - psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); - psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); - psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); - psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); - psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); - psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); - psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); - psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + if (lane_active == 0) { + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + Xil_Out32(0xFD403068, 0x1); + Xil_Out32(0xFD40306C, 0x1); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403008, 0x0); + Xil_Out32(0xFD40300C, 0xF4); + Xil_Out32(0xFD403010, 0x0); + Xil_Out32(0xFD403014, 0x0); + Xil_Out32(0xFD403018, 0x00); + Xil_Out32(0xFD40301C, 0xFB); + Xil_Out32(0xFD403020, 0xFF); + Xil_Out32(0xFD403024, 0x0); + Xil_Out32(0xFD403028, 0x00); + Xil_Out32(0xFD40302C, 0x00); + Xil_Out32(0xFD403030, 0x4A); + Xil_Out32(0xFD403034, 0x4A); + Xil_Out32(0xFD403038, 0x4A); + Xil_Out32(0xFD40303C, 0x4A); + Xil_Out32(0xFD403040, 0x0); + Xil_Out32(0xFD403044, 0x14); + Xil_Out32(0xFD403048, 0x02); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + } + if (lane_active == 1) { + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + Xil_Out32(0xFD407068, 0x1); + Xil_Out32(0xFD40706C, 0x1); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407008, 0x0); + Xil_Out32(0xFD40700C, 0xF4); + Xil_Out32(0xFD407010, 0x0); + Xil_Out32(0xFD407014, 0x0); + Xil_Out32(0xFD407018, 0x00); + Xil_Out32(0xFD40701C, 0xFB); + Xil_Out32(0xFD407020, 0xFF); + Xil_Out32(0xFD407024, 0x0); + Xil_Out32(0xFD407028, 0x00); + Xil_Out32(0xFD40702C, 0x00); + Xil_Out32(0xFD407030, 0x4A); + Xil_Out32(0xFD407034, 0x4A); + Xil_Out32(0xFD407038, 0x4A); + Xil_Out32(0xFD40703C, 0x4A); + Xil_Out32(0xFD407040, 0x0); + Xil_Out32(0xFD407044, 0x14); + Xil_Out32(0xFD407048, 0x02); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + }
- return 1; -} - -static unsigned long psu_ddr_init_data(void) -{ - psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U); - psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); - psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U); - psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U); - psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); - psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); - psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); - psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); - psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); - psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U); - psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); - psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); - psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); - psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U); - psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U); - psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); - psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U); - psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U); - psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); - psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); - psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); - psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU); - psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U); - psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U); - psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1A10U); - psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U); - psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU); - psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U); - psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U); - psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U); - psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U); - psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); - psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); - psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); - psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U); - psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U); - psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU); - psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); - psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); - psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); - psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U); - psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); - psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U); - psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U); - psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); - psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); - psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U); - psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); - psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U); - psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U); - psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U); - psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); - psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U); - psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U); - psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U); - psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U); - psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U); - psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); - psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); - psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); - psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); - psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); - psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); - psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); - psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); - psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); - psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); - psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); - psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U); - psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U); - psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); - psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); - psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); - psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); - psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); - psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U); - psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU); - psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U); - psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0711U); - psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U); - psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U); - psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU); - psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU); - psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U); - psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); - psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); - psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U); - psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U); - psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U); - psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U); - psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U); - psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U); - psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); - psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U); - psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U); - psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); - psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); - psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); - psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); - psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); - psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU); - psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); - psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U); - psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U); - psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); - psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); - psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U); - psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU); - psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); - psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); - psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU); - psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU); - psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU); - psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U); - psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U); - psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U); - psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U); - psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U); - psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U); - psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U); - psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U); - psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U); - psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U); - psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U); - psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U); - psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U); - psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U); - psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U); - psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U); - psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); - psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U); - psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); - - return 1; -} - -static unsigned long psu_ddr_qos_init_data(void) -{ - psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + if (lane_active == 2) { + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40B068, 0x1); + Xil_Out32(0xFD40B06C, 0x1); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B008, 0x0); + Xil_Out32(0xFD40B00C, 0xF4); + Xil_Out32(0xFD40B010, 0x0); + Xil_Out32(0xFD40B014, 0x0); + Xil_Out32(0xFD40B018, 0x00); + Xil_Out32(0xFD40B01C, 0xFB); + Xil_Out32(0xFD40B020, 0xFF); + Xil_Out32(0xFD40B024, 0x0); + Xil_Out32(0xFD40B028, 0x00); + Xil_Out32(0xFD40B02C, 0x00); + Xil_Out32(0xFD40B030, 0x4A); + Xil_Out32(0xFD40B034, 0x4A); + Xil_Out32(0xFD40B038, 0x4A); + Xil_Out32(0xFD40B03C, 0x4A); + Xil_Out32(0xFD40B040, 0x0); + Xil_Out32(0xFD40B044, 0x14); + Xil_Out32(0xFD40B048, 0x02); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + }
+ if (lane_active == 3) { + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40F068, 0x1); + Xil_Out32(0xFD40F06C, 0x1); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F008, 0x0); + Xil_Out32(0xFD40F00C, 0xF4); + Xil_Out32(0xFD40F010, 0x0); + Xil_Out32(0xFD40F014, 0x0); + Xil_Out32(0xFD40F018, 0x00); + Xil_Out32(0xFD40F01C, 0xFB); + Xil_Out32(0xFD40F020, 0xFF); + Xil_Out32(0xFD40F024, 0x0); + Xil_Out32(0xFD40F028, 0x00); + Xil_Out32(0xFD40F02C, 0x00); + Xil_Out32(0xFD40F030, 0x4A); + Xil_Out32(0xFD40F034, 0x4A); + Xil_Out32(0xFD40F038, 0x4A); + Xil_Out32(0xFD40F03C, 0x4A); + Xil_Out32(0xFD40F040, 0x0); + Xil_Out32(0xFD40F044, 0x14); + Xil_Out32(0xFD40F048, 0x02); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + } return 1; }
-static unsigned long psu_mio_init_data(void) +static int serdes_bist_run(u32 lane_active) { - psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180128, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U); - psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00002040U); - psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U); - psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); - + if (lane_active == 0) { + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); + } + if (lane_active == 1) { + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); + } + if (lane_active == 2) { + psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + } + if (lane_active == 3) { + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + } + mask_delay(100); return 1; }
-static unsigned long psu_peripherals_pre_init_data(void) +static int serdes_bist_result(u32 lane_active) { - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0;
+ if (lane_active == 0) { + pkt_cnt_l0 = Xil_In32(0xFD40304C); + pkt_cnt_h0 = Xil_In32(0xFD403050); + err_cnt_l0 = Xil_In32(0xFD403054); + err_cnt_h0 = Xil_In32(0xFD403058); + } + if (lane_active == 1) { + pkt_cnt_l0 = Xil_In32(0xFD40704C); + pkt_cnt_h0 = Xil_In32(0xFD407050); + err_cnt_l0 = Xil_In32(0xFD407054); + err_cnt_h0 = Xil_In32(0xFD407058); + } + if (lane_active == 2) { + pkt_cnt_l0 = Xil_In32(0xFD40B04C); + pkt_cnt_h0 = Xil_In32(0xFD40B050); + err_cnt_l0 = Xil_In32(0xFD40B054); + err_cnt_h0 = Xil_In32(0xFD40B058); + } + if (lane_active == 3) { + pkt_cnt_l0 = Xil_In32(0xFD40F04C); + pkt_cnt_h0 = Xil_In32(0xFD40F050); + err_cnt_l0 = Xil_In32(0xFD40F054); + err_cnt_h0 = Xil_In32(0xFD40F058); + } + if (lane_active == 0) + Xil_Out32(0xFD403004, 0x0); + if (lane_active == 1) + Xil_Out32(0xFD407004, 0x0); + if (lane_active == 2) + Xil_Out32(0xFD40B004, 0x0); + if (lane_active == 3) + Xil_Out32(0xFD40F004, 0x0); + if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || + (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) + return 0; return 1; }
-static unsigned long psu_peripherals_init_data(void) +static int serdes_illcalib_pcie_gen1(u32 pllsel, u32 lane3_protocol, + u32 lane3_rate, u32 lane2_protocol, + u32 lane2_rate, u32 lane1_protocol, + u32 lane1_rate, u32 lane0_protocol, + u32 lane0_rate, u32 gen2_calib) { - psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33840000U, 0x00800000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); - psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); - psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); - psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); - psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); - psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - return 1; -} + u64 tempbistresult; + u32 currbistresult[4]; + u32 prevbistresult[4]; + u32 itercount = 0; + u32 ill12_val[4], ill1_val[4]; + u32 loop = 0; + u32 iterresult[8]; + u32 meancount[4]; + u32 bistpasscount[4]; + u32 meancountalt[4]; + u32 meancountalt_bistpasscount[4]; + u32 lane0_active; + u32 lane1_active; + u32 lane2_active; + u32 lane3_active;
-static unsigned long psu_serdes_init_data(void) -{ - psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU); - psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU); - psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU); - psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U); - psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); - psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + lane0_active = (lane0_protocol == 1); + lane1_active = (lane1_protocol == 1); + lane2_active = (lane2_protocol == 1); + lane3_active = (lane3_protocol == 1); + for (loop = 0; loop <= 3; loop++) { + iterresult[loop] = 0; + iterresult[loop + 4] = 0; + meancountalt[loop] = 0; + meancountalt_bistpasscount[loop] = 0; + meancount[loop] = 0; + prevbistresult[loop] = 0; + bistpasscount[loop] = 0; + } + itercount = 0; + if (lane0_active) + serdes_bist_static_settings(0); + if (lane1_active) + serdes_bist_static_settings(1); + if (lane2_active) + serdes_bist_static_settings(2); + if (lane3_active) + serdes_bist_static_settings(3); + do { + if (gen2_calib != 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x04 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane1_active == 1) + ill1_val[1] = ((0x04 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane2_active == 1) + ill1_val[2] = ((0x04 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) + ill1_val[3] = ((0x04 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, + ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x104 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane1_active == 1) + ill1_val[1] = ((0x104 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane2_active == 1) + ill1_val[2] = ((0x104 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane3_active == 1) + ill1_val[3] = ((0x104 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, + ill12_val[3]); + }
- serdes_illcalib(0, 0, 0, 0, 0, 0, 5, 0); - psu_mask_write(0xFD410010, 0x00000007U, 0x00000005U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); + if (lane0_active == 1) + currbistresult[0] = 0; + if (lane1_active == 1) + currbistresult[1] = 0; + if (lane2_active == 1) + currbistresult[2] = 0; + if (lane3_active == 1) + currbistresult[3] = 0; + serdes_rst_seq(pllsel, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, lane1_protocol, + lane1_rate, lane0_protocol, lane0_rate); + if (lane3_active == 1) + serdes_bist_run(3); + if (lane2_active == 1) + serdes_bist_run(2); + if (lane1_active == 1) + serdes_bist_run(1); + if (lane0_active == 1) + serdes_bist_run(0); + tempbistresult = 0; + if (lane3_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(3); + tempbistresult = tempbistresult << 1; + if (lane2_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(2); + tempbistresult = tempbistresult << 1; + if (lane1_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(1); + tempbistresult = tempbistresult << 1; + if (lane0_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(0); + Xil_Out32(0xFD410098, 0x0); + Xil_Out32(0xFD410098, 0x2);
- return 1; -} + if (itercount < 32) { + iterresult[0] = + ((iterresult[0] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[1] = + ((iterresult[1] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[2] = + ((iterresult[2] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[3] = + ((iterresult[3] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } else { + iterresult[4] = + ((iterresult[4] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[5] = + ((iterresult[5] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[6] = + ((iterresult[6] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[7] = + ((iterresult[7] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } + currbistresult[0] = + currbistresult[0] | ((tempbistresult & 0x1) == 1); + currbistresult[1] = + currbistresult[1] | ((tempbistresult & 0x2) == 0x2); + currbistresult[2] = + currbistresult[2] | ((tempbistresult & 0x4) == 0x4); + currbistresult[3] = + currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
-static unsigned long psu_resetout_init_data(void) -{ - psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); - psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); - mask_poll(0xFD4023E4, 0x00000010U); + for (loop = 0; loop <= 3; loop++) { + if (currbistresult[loop] == 1 && + prevbistresult[loop] == 1) + bistpasscount[loop] = bistpasscount[loop] + 1; + if (bistpasscount[loop] < 4 && + currbistresult[loop] == 0 && itercount > 2) { + if (meancountalt_bistpasscount[loop] < + bistpasscount[loop]) { + meancountalt_bistpasscount[loop] = + bistpasscount[loop]; + meancountalt[loop] = + ((itercount - 1) - + ((bistpasscount[loop] + 1) / 2)); + } + bistpasscount[loop] = 0; + } + if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && + (currbistresult[loop] == 0 || itercount == 63) && + prevbistresult[loop] == 1) + meancount[loop] = + itercount - 1 - + ((bistpasscount[loop] + 1) / 2); + prevbistresult[loop] = currbistresult[loop]; + } + } while (++itercount < 64);
- return 1; -} + for (loop = 0; loop <= 3; loop++) { + if (lane0_active == 0 && loop == 0) + continue; + if (lane1_active == 0 && loop == 1) + continue; + if (lane2_active == 0 && loop == 2) + continue; + if (lane3_active == 0 && loop == 3) + continue;
-static unsigned long psu_resetin_init_data(void) -{ - psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U); + if (meancount[loop] == 0) + meancount[loop] = meancountalt[loop];
- return 1; -} + if (gen2_calib != 1) { + ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x04 + meancount[loop] * 8) >= + 0x100) ? 0x10 : 0x00; + } + if (gen2_calib == 1) { + ill1_val[loop] = + ((0x104 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x104 + meancount[loop] * 8) >= + 0x200) ? 0x02 : 0x01; + } + } + if (gen2_calib != 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); + }
-static unsigned long psu_afi_config(void) -{ - psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); - psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U); + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
+ Xil_Out32(0xFD410098, 0); + if (lane0_active == 1) { + Xil_Out32(0xFD403004, 0); + Xil_Out32(0xFD403008, 0); + Xil_Out32(0xFD40300C, 0); + Xil_Out32(0xFD403010, 0); + Xil_Out32(0xFD403014, 0); + Xil_Out32(0xFD403018, 0); + Xil_Out32(0xFD40301C, 0); + Xil_Out32(0xFD403020, 0); + Xil_Out32(0xFD403024, 0); + Xil_Out32(0xFD403028, 0); + Xil_Out32(0xFD40302C, 0); + Xil_Out32(0xFD403030, 0); + Xil_Out32(0xFD403034, 0); + Xil_Out32(0xFD403038, 0); + Xil_Out32(0xFD40303C, 0); + Xil_Out32(0xFD403040, 0); + Xil_Out32(0xFD403044, 0); + Xil_Out32(0xFD403048, 0); + Xil_Out32(0xFD40304C, 0); + Xil_Out32(0xFD403050, 0); + Xil_Out32(0xFD403054, 0); + Xil_Out32(0xFD403058, 0); + Xil_Out32(0xFD403068, 1); + Xil_Out32(0xFD40306C, 0); + Xil_Out32(0xFD4010AC, 0); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); + } + if (lane1_active == 1) { + Xil_Out32(0xFD407004, 0); + Xil_Out32(0xFD407008, 0); + Xil_Out32(0xFD40700C, 0); + Xil_Out32(0xFD407010, 0); + Xil_Out32(0xFD407014, 0); + Xil_Out32(0xFD407018, 0); + Xil_Out32(0xFD40701C, 0); + Xil_Out32(0xFD407020, 0); + Xil_Out32(0xFD407024, 0); + Xil_Out32(0xFD407028, 0); + Xil_Out32(0xFD40702C, 0); + Xil_Out32(0xFD407030, 0); + Xil_Out32(0xFD407034, 0); + Xil_Out32(0xFD407038, 0); + Xil_Out32(0xFD40703C, 0); + Xil_Out32(0xFD407040, 0); + Xil_Out32(0xFD407044, 0); + Xil_Out32(0xFD407048, 0); + Xil_Out32(0xFD40704C, 0); + Xil_Out32(0xFD407050, 0); + Xil_Out32(0xFD407054, 0); + Xil_Out32(0xFD407058, 0); + Xil_Out32(0xFD407068, 1); + Xil_Out32(0xFD40706C, 0); + Xil_Out32(0xFD4050AC, 0); + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); + } + if (lane2_active == 1) { + Xil_Out32(0xFD40B004, 0); + Xil_Out32(0xFD40B008, 0); + Xil_Out32(0xFD40B00C, 0); + Xil_Out32(0xFD40B010, 0); + Xil_Out32(0xFD40B014, 0); + Xil_Out32(0xFD40B018, 0); + Xil_Out32(0xFD40B01C, 0); + Xil_Out32(0xFD40B020, 0); + Xil_Out32(0xFD40B024, 0); + Xil_Out32(0xFD40B028, 0); + Xil_Out32(0xFD40B02C, 0); + Xil_Out32(0xFD40B030, 0); + Xil_Out32(0xFD40B034, 0); + Xil_Out32(0xFD40B038, 0); + Xil_Out32(0xFD40B03C, 0); + Xil_Out32(0xFD40B040, 0); + Xil_Out32(0xFD40B044, 0); + Xil_Out32(0xFD40B048, 0); + Xil_Out32(0xFD40B04C, 0); + Xil_Out32(0xFD40B050, 0); + Xil_Out32(0xFD40B054, 0); + Xil_Out32(0xFD40B058, 0); + Xil_Out32(0xFD40B068, 1); + Xil_Out32(0xFD40B06C, 0); + Xil_Out32(0xFD4090AC, 0); + psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); + } + if (lane3_active == 1) { + Xil_Out32(0xFD40F004, 0); + Xil_Out32(0xFD40F008, 0); + Xil_Out32(0xFD40F00C, 0); + Xil_Out32(0xFD40F010, 0); + Xil_Out32(0xFD40F014, 0); + Xil_Out32(0xFD40F018, 0); + Xil_Out32(0xFD40F01C, 0); + Xil_Out32(0xFD40F020, 0); + Xil_Out32(0xFD40F024, 0); + Xil_Out32(0xFD40F028, 0); + Xil_Out32(0xFD40F02C, 0); + Xil_Out32(0xFD40F030, 0); + Xil_Out32(0xFD40F034, 0); + Xil_Out32(0xFD40F038, 0); + Xil_Out32(0xFD40F03C, 0); + Xil_Out32(0xFD40F040, 0); + Xil_Out32(0xFD40F044, 0); + Xil_Out32(0xFD40F048, 0); + Xil_Out32(0xFD40F04C, 0); + Xil_Out32(0xFD40F050, 0); + Xil_Out32(0xFD40F054, 0); + Xil_Out32(0xFD40F058, 0); + Xil_Out32(0xFD40F068, 1); + Xil_Out32(0xFD40F06C, 0); + Xil_Out32(0xFD40D0AC, 0); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); + } return 1; }
-static unsigned long psu_ddr_phybringup_data(void) +static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) { - unsigned int regval = 0; - - for (int tp = 0; tp < 20; tp++) - regval = Xil_In32(0xFD070018); - int cur_PLLCR0; - - cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SL0PLLCR0; - - cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SL1PLLCR0; - - cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SL2PLLCR0; - - cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SL3PLLCR0; - - cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SL4PLLCR0; - - cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U; - int cur_DX8SLBPLLCR0; - - cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U; - Xil_Out32(0xFD080068, 0x02120000); - Xil_Out32(0xFD081404, 0x02120000); - Xil_Out32(0xFD081444, 0x02120000); - Xil_Out32(0xFD081484, 0x02120000); - Xil_Out32(0xFD0814C4, 0x02120000); - Xil_Out32(0xFD081504, 0x02120000); - Xil_Out32(0xFD0817C4, 0x02120000); - int cur_div2; - - cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U; - int cur_fbdiv; - - cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U; - dpll_prog(1, 49, 63, 625, 3, 3, 2); - for (int tp = 0; tp < 20; tp++) - regval = Xil_In32(0xFD070018); - unsigned int pll_retry = 10; - unsigned int pll_locked = 0; - - while ((pll_retry > 0) && (!pll_locked)) { - Xil_Out32(0xFD080004, 0x00040010); - Xil_Out32(0xFD080004, 0x00040011); + unsigned int rdata = 0; + unsigned int sata_gen2 = 1; + unsigned int temp_ill12 = 0; + unsigned int temp_PLL_REF_SEL_OFFSET; + unsigned int temp_TM_IQ_ILL1; + unsigned int temp_TM_E_ILL1; + unsigned int temp_tx_dig_tm_61; + unsigned int temp_tm_dig_6; + unsigned int temp_pll_fbdiv_frac_3_msb_offset;
- while ((Xil_In32(0xFD080030) & 0x1) != 1) - ; - pll_locked = (Xil_In32(0xFD080030) & 0x80000000) - >> 31; - pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; - pll_retry--; + if (lane0_protocol == 2 || lane0_protocol == 1) { + Xil_Out32(0xFD401910, 0xF3); + Xil_Out32(0xFD40193C, 0xF3); + Xil_Out32(0xFD401914, 0xF3); + Xil_Out32(0xFD401940, 0xF3); + } + if (lane1_protocol == 2 || lane1_protocol == 1) { + Xil_Out32(0xFD405910, 0xF3); + Xil_Out32(0xFD40593C, 0xF3); + Xil_Out32(0xFD405914, 0xF3); + Xil_Out32(0xFD405940, 0xF3); + } + if (lane2_protocol == 2 || lane2_protocol == 1) { + Xil_Out32(0xFD409910, 0xF3); + Xil_Out32(0xFD40993C, 0xF3); + Xil_Out32(0xFD409914, 0xF3); + Xil_Out32(0xFD409940, 0xF3); + } + if (lane3_protocol == 2 || lane3_protocol == 1) { + Xil_Out32(0xFD40D910, 0xF3); + Xil_Out32(0xFD40D93C, 0xF3); + Xil_Out32(0xFD40D914, 0xF3); + Xil_Out32(0xFD40D940, 0xF3); } - Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); - if (!pll_locked) - return 0; - - Xil_Out32(0xFD080004U, 0x00040063U); - Xil_Out32(0xFD0800C0U, 0x00000001U); - - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) - ; - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) - ; - Xil_Out32(0xFD070010U, 0x80000018U); - Xil_Out32(0xFD0701B0U, 0x00000005U); - regval = Xil_In32(0xFD070018); - while ((regval & 0x1) != 0x0) - regval = Xil_In32(0xFD070018); - - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - Xil_Out32(0xFD070014U, 0x00000331U); - Xil_Out32(0xFD070010U, 0x80000018U); - regval = Xil_In32(0xFD070018); - while ((regval & 0x1) != 0x0) - regval = Xil_In32(0xFD070018);
- regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - Xil_Out32(0xFD070014U, 0x00000B36U); - Xil_Out32(0xFD070010U, 0x80000018U); - regval = Xil_In32(0xFD070018); - while ((regval & 0x1) != 0x0) - regval = Xil_In32(0xFD070018); + if (sata_gen2 == 1) { + if (lane0_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); + Xil_Out32(0xFD402360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); + temp_TM_E_ILL1 = Xil_In32(0xFD401924); + Xil_Out32(0xFD4018F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); + temp_tm_dig_6 = Xil_In32(0xFD40106C); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD401990) & 0xF0;
- regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - Xil_Out32(0xFD070014U, 0x00000C56U); - Xil_Out32(0xFD070010U, 0x80000018U); - regval = Xil_In32(0xFD070018); - while ((regval & 0x1) != 0x0) - regval = Xil_In32(0xFD070018); + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 0, 1, 0, 0);
- regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - Xil_Out32(0xFD070014U, 0x00000E19U); - Xil_Out32(0xFD070010U, 0x80000018U); - regval = Xil_In32(0xFD070018); - while ((regval & 0x1) != 0x0) - regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD410000, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40106C, temp_tm_dig_6); + Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); + Xil_Out32(0xFD401990, temp_ill12); + Xil_Out32(0xFD401924, temp_TM_E_ILL1); + } + if (lane1_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); + Xil_Out32(0xFD406360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); + temp_TM_E_ILL1 = Xil_In32(0xFD405924); + Xil_Out32(0xFD4058F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); + temp_tm_dig_6 = Xil_In32(0xFD40506C); + psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD405990) & 0xF0;
- regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - regval = Xil_In32(0xFD070018); - Xil_Out32(0xFD070014U, 0x00001616U); - Xil_Out32(0xFD070010U, 0x80000018U); - Xil_Out32(0xFD070010U, 0x80000010U); - Xil_Out32(0xFD0701B0U, 0x00000005U); - Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) - ; - prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U); - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); - prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U); - prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); - prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); - prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U); - prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); - for (int tp = 0; tp < 20; tp++) - regval = Xil_In32(0xFD070018); + serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 1, 0, 0, 0, 0);
- Xil_Out32(0xFD080068, cur_PLLCR0); - Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0); - Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0); - Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0); - Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0); - Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0); - Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0); - for (int tp = 0; tp < 20; tp++) - regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD410004, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40506C, temp_tm_dig_6); + Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); + Xil_Out32(0xFD405990, temp_ill12); + Xil_Out32(0xFD405924, temp_TM_E_ILL1); + } + if (lane2_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); + Xil_Out32(0xFD40A360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); + psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); + temp_TM_E_ILL1 = Xil_In32(0xFD409924); + Xil_Out32(0xFD4098F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); + temp_tm_dig_6 = Xil_In32(0xFD40906C); + psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD409990) & 0xF0;
- dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2); - for (int tp = 0; tp < 2000; tp++) - regval = Xil_In32(0xFD070018); + serdes_illcalib_pcie_gen1(2, 0, 0, 1, 0, 0, 0, 0, 0, 0);
- prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U); - prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U); - prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U); - prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U); - prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U); - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD410008, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40906C, temp_tm_dig_6); + Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); + Xil_Out32(0xFD409990, temp_ill12); + Xil_Out32(0xFD409924, temp_TM_E_ILL1); + } + if (lane3_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); + Xil_Out32(0xFD40E360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); + temp_TM_E_ILL1 = Xil_In32(0xFD40D924); + Xil_Out32(0xFD40D8F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); + temp_tm_dig_6 = Xil_In32(0xFD40D06C); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD40D990) & 0xF0;
- while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) - ; - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + serdes_illcalib_pcie_gen1(3, 1, 0, 0, 0, 0, 0, 0, 0, 0);
- while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) - ; - for (int tp = 0; tp < 2000; tp++) - regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40D06C, temp_tm_dig_6); + Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); + Xil_Out32(0xFD40D990, temp_ill12); + Xil_Out32(0xFD40D924, temp_TM_E_ILL1); + } + rdata = Xil_In32(0xFD410098); + rdata = (rdata & 0xDF); + Xil_Out32(0xFD410098, rdata); + }
- prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U); - prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); - prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); - prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U); - prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); - for (int tp = 0; tp < 2000; tp++) - regval = Xil_In32(0xFD070018); + if (lane0_protocol == 2 && lane0_rate == 3) { + psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); + } + if (lane1_protocol == 2 && lane1_rate == 3) { + psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); + } + if (lane2_protocol == 2 && lane2_rate == 3) { + psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); + } + if (lane3_protocol == 2 && lane3_rate == 3) { + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); + }
- prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0014FE01); + if (lane0_protocol == 1) { + if (lane0_rate == 0) { + serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + } else { + serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate, + 1); + } + }
- regval = Xil_In32(0xFD080030); - while (regval != 0x8000007E) - regval = Xil_In32(0xFD080030); + if (lane0_protocol == 3) + Xil_Out32(0xFD401914, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401940, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401990, 0x20); + if (lane0_protocol == 3) + Xil_Out32(0xFD401924, 0x37);
- Xil_Out32(0xFD080200U, 0x000091C7U); - regval = Xil_In32(0xFD080030); - while (regval != 0x80008FFF) - regval = Xil_In32(0xFD080030); + if (lane1_protocol == 3) + Xil_Out32(0xFD405914, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405940, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405990, 0x20); + if (lane1_protocol == 3) + Xil_Out32(0xFD405924, 0x37);
- Xil_Out32(0xFD080200U, 0x800091C7U); - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U); - prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U); - prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U); - prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U); - Xil_Out32(0xFD070180U, 0x02160010U); - Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); - for (int tp = 0; tp < 4000; tp++) - regval = Xil_In32(0xFD070018); + if (lane2_protocol == 3) + Xil_Out32(0xFD409914, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409940, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409990, 0x20); + if (lane2_protocol == 3) + Xil_Out32(0xFD409924, 0x37);
- prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U); - prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U); - prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U); - prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U); - prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U); - prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U); - prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U); - prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U); - prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U); - prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U); - prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U); - prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U); - prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U); - prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U); - prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U); - prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU); - prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D914, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D940, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D990, 0x20); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D924, 0x37);
return 1; }
-static int serdes_rst_seq(u32 pllsel, u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, + int d_lock_cnt, int d_lfhf, int d_cp, int d_res) { - Xil_Out32(0xFD410098, 0x00000000); - Xil_Out32(0xFD401010, 0x00000040); - Xil_Out32(0xFD405010, 0x00000040); - Xil_Out32(0xFD409010, 0x00000040); - Xil_Out32(0xFD40D010, 0x00000040); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - Xil_Out32(0xFD410098, 0x00000004); - mask_delay(50); - if (lane0_rate == 1) - Xil_Out32(0xFD410098, 0x0000000E); - Xil_Out32(0xFD410098, 0x00000006); - if (lane0_rate == 1) { - Xil_Out32(0xFD40000C, 0x00000004); - Xil_Out32(0xFD40400C, 0x00000004); - Xil_Out32(0xFD40800C, 0x00000004); - Xil_Out32(0xFD40C00C, 0x00000004); - Xil_Out32(0xFD410098, 0x00000007); - mask_delay(400); - Xil_Out32(0xFD40000C, 0x0000000C); - Xil_Out32(0xFD40400C, 0x0000000C); - Xil_Out32(0xFD40800C, 0x0000000C); - Xil_Out32(0xFD40C00C, 0x0000000C); - mask_delay(15); - Xil_Out32(0xFD410098, 0x0000000F); - mask_delay(100); - } - if (pllsel == 0) - mask_poll(0xFD4023E4, 0x00000010U); - if (pllsel == 1) - mask_poll(0xFD4063E4, 0x00000010U); - if (pllsel == 2) - mask_poll(0xFD40A3E4, 0x00000010U); - if (pllsel == 3) - mask_poll(0xFD40E3E4, 0x00000010U); - mask_delay(50); - Xil_Out32(0xFD401010, 0x000000C0); - Xil_Out32(0xFD405010, 0x000000C0); - Xil_Out32(0xFD409010, 0x000000C0); - Xil_Out32(0xFD40D010, 0x000000C0); - Xil_Out32(0xFD401010, 0x00000080); - Xil_Out32(0xFD405010, 0x00000080); - Xil_Out32(0xFD409010, 0x00000080); - Xil_Out32(0xFD40D010, 0x00000080); + unsigned int pll_ctrl_regval; + unsigned int pll_status_regval;
- Xil_Out32(0xFD402084, 0x000000C0); - Xil_Out32(0xFD406084, 0x000000C0); - Xil_Out32(0xFD40A084, 0x000000C0); - Xil_Out32(0xFD40E084, 0x000000C0); - mask_delay(50); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - mask_delay(50); - Xil_Out32(0xFD401010, 0x00000000); - Xil_Out32(0xFD405010, 0x00000000); - Xil_Out32(0xFD409010, 0x00000000); - Xil_Out32(0xFD40D010, 0x00000000); - Xil_Out32(0xFD402084, 0x00000000); - Xil_Out32(0xFD406084, 0x00000000); - Xil_Out32(0xFD40A084, 0x00000000); - Xil_Out32(0xFD40E084, 0x00000000); - mask_delay(500); - return 1; -} + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U); + pll_ctrl_regval = pll_ctrl_regval | (div2 << 16); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
-static int serdes_bist_static_settings(u32 lane_active) -{ - if (lane_active == 0) { - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - Xil_Out32(0xFD403068, 0x1); - Xil_Out32(0xFD40306C, 0x1); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403008, 0x0); - Xil_Out32(0xFD40300C, 0xF4); - Xil_Out32(0xFD403010, 0x0); - Xil_Out32(0xFD403014, 0x0); - Xil_Out32(0xFD403018, 0x00); - Xil_Out32(0xFD40301C, 0xFB); - Xil_Out32(0xFD403020, 0xFF); - Xil_Out32(0xFD403024, 0x0); - Xil_Out32(0xFD403028, 0x00); - Xil_Out32(0xFD40302C, 0x00); - Xil_Out32(0xFD403030, 0x4A); - Xil_Out32(0xFD403034, 0x4A); - Xil_Out32(0xFD403038, 0x4A); - Xil_Out32(0xFD40303C, 0x4A); - Xil_Out32(0xFD403040, 0x0); - Xil_Out32(0xFD403044, 0x14); - Xil_Out32(0xFD403048, 0x02); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - } - if (lane_active == 1) { - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - Xil_Out32(0xFD407068, 0x1); - Xil_Out32(0xFD40706C, 0x1); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407008, 0x0); - Xil_Out32(0xFD40700C, 0xF4); - Xil_Out32(0xFD407010, 0x0); - Xil_Out32(0xFD407014, 0x0); - Xil_Out32(0xFD407018, 0x00); - Xil_Out32(0xFD40701C, 0xFB); - Xil_Out32(0xFD407020, 0xFF); - Xil_Out32(0xFD407024, 0x0); - Xil_Out32(0xFD407028, 0x00); - Xil_Out32(0xFD40702C, 0x00); - Xil_Out32(0xFD407030, 0x4A); - Xil_Out32(0xFD407034, 0x4A); - Xil_Out32(0xFD407038, 0x4A); - Xil_Out32(0xFD40703C, 0x4A); - Xil_Out32(0xFD407040, 0x0); - Xil_Out32(0xFD407044, 0x14); - Xil_Out32(0xFD407048, 0x02); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - } + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U); + pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
- if (lane_active == 2) { - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40B068, 0x1); - Xil_Out32(0xFD40B06C, 0x1); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B008, 0x0); - Xil_Out32(0xFD40B00C, 0xF4); - Xil_Out32(0xFD40B010, 0x0); - Xil_Out32(0xFD40B014, 0x0); - Xil_Out32(0xFD40B018, 0x00); - Xil_Out32(0xFD40B01C, 0xFB); - Xil_Out32(0xFD40B020, 0xFF); - Xil_Out32(0xFD40B024, 0x0); - Xil_Out32(0xFD40B028, 0x00); - Xil_Out32(0xFD40B02C, 0x00); - Xil_Out32(0xFD40B030, 0x4A); - Xil_Out32(0xFD40B034, 0x4A); - Xil_Out32(0xFD40B038, 0x4A); - Xil_Out32(0xFD40B03C, 0x4A); - Xil_Out32(0xFD40B040, 0x0); - Xil_Out32(0xFD40B044, 0x14); - Xil_Out32(0xFD40B048, 0x02); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - } + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U); + pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U); + pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U); + pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU); + pll_ctrl_regval = pll_ctrl_regval | (d_res << 0); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U); + pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 3); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 0); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); + pll_ctrl_regval = pll_ctrl_regval | (0 << 0); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_status_regval = 0x00000000; + while ((pll_status_regval & 0x00000002U) != 0x00000002U) + pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044)); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); + pll_ctrl_regval = pll_ctrl_regval | (0 << 3); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); +} + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
- if (lane_active == 3) { - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40F068, 0x1); - Xil_Out32(0xFD40F06C, 0x1); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F008, 0x0); - Xil_Out32(0xFD40F00C, 0xF4); - Xil_Out32(0xFD40F010, 0x0); - Xil_Out32(0xFD40F014, 0x0); - Xil_Out32(0xFD40F018, 0x00); - Xil_Out32(0xFD40F01C, 0xFB); - Xil_Out32(0xFD40F020, 0xFF); - Xil_Out32(0xFD40F024, 0x0); - Xil_Out32(0xFD40F028, 0x00); - Xil_Out32(0xFD40F02C, 0x00); - Xil_Out32(0xFD40F030, 0x4A); - Xil_Out32(0xFD40F034, 0x4A); - Xil_Out32(0xFD40F038, 0x4A); - Xil_Out32(0xFD40F03C, 0x4A); - Xil_Out32(0xFD40F040, 0x0); - Xil_Out32(0xFD40F044, 0x14); - Xil_Out32(0xFD40F048, 0x02); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - } return 1; }
-static int serdes_bist_run(u32 lane_active) +static unsigned long psu_clock_init_data(void) { - if (lane_active == 0) { - psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); - } - if (lane_active == 1) { - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); - } - if (lane_active == 2) { - psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); - } - if (lane_active == 3) { - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); - } - mask_delay(100); + psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U); + psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + return 1; }
-static int serdes_bist_result(u32 lane_active) +static unsigned long psu_ddr_init_data(void) { - u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1A10U); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0711U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
- if (lane_active == 0) { - pkt_cnt_l0 = Xil_In32(0xFD40304C); - pkt_cnt_h0 = Xil_In32(0xFD403050); - err_cnt_l0 = Xil_In32(0xFD403054); - err_cnt_h0 = Xil_In32(0xFD403058); - } - if (lane_active == 1) { - pkt_cnt_l0 = Xil_In32(0xFD40704C); - pkt_cnt_h0 = Xil_In32(0xFD407050); - err_cnt_l0 = Xil_In32(0xFD407054); - err_cnt_h0 = Xil_In32(0xFD407058); - } - if (lane_active == 2) { - pkt_cnt_l0 = Xil_In32(0xFD40B04C); - pkt_cnt_h0 = Xil_In32(0xFD40B050); - err_cnt_l0 = Xil_In32(0xFD40B054); - err_cnt_h0 = Xil_In32(0xFD40B058); - } - if (lane_active == 3) { - pkt_cnt_l0 = Xil_In32(0xFD40F04C); - pkt_cnt_h0 = Xil_In32(0xFD40F050); - err_cnt_l0 = Xil_In32(0xFD40F054); - err_cnt_h0 = Xil_In32(0xFD40F058); - } - if (lane_active == 0) - Xil_Out32(0xFD403004, 0x0); - if (lane_active == 1) - Xil_Out32(0xFD407004, 0x0); - if (lane_active == 2) - Xil_Out32(0xFD40B004, 0x0); - if (lane_active == 3) - Xil_Out32(0xFD40F004, 0x0); - if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || - (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) - return 0; return 1; }
-static int serdes_illcalib_pcie_gen1(u32 pllsel, u32 lane3_protocol, - u32 lane3_rate, u32 lane2_protocol, - u32 lane2_rate, u32 lane1_protocol, - u32 lane1_rate, u32 lane0_protocol, - u32 lane0_rate, u32 gen2_calib) +static unsigned long psu_ddr_qos_init_data(void) { - u64 tempbistresult; - u32 currbistresult[4]; - u32 prevbistresult[4]; - u32 itercount = 0; - u32 ill12_val[4], ill1_val[4]; - u32 loop = 0; - u32 iterresult[8]; - u32 meancount[4]; - u32 bistpasscount[4]; - u32 meancountalt[4]; - u32 meancountalt_bistpasscount[4]; - u32 lane0_active; - u32 lane1_active; - u32 lane2_active; - u32 lane3_active; - - lane0_active = (lane0_protocol == 1); - lane1_active = (lane1_protocol == 1); - lane2_active = (lane2_protocol == 1); - lane3_active = (lane3_protocol == 1); - for (loop = 0; loop <= 3; loop++) { - iterresult[loop] = 0; - iterresult[loop + 4] = 0; - meancountalt[loop] = 0; - meancountalt_bistpasscount[loop] = 0; - meancount[loop] = 0; - prevbistresult[loop] = 0; - bistpasscount[loop] = 0; - } - itercount = 0; - if (lane0_active) - serdes_bist_static_settings(0); - if (lane1_active) - serdes_bist_static_settings(1); - if (lane2_active) - serdes_bist_static_settings(2); - if (lane3_active) - serdes_bist_static_settings(3); - do { - if (gen2_calib != 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x04 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane1_active == 1) - ill1_val[1] = ((0x04 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane2_active == 1) - ill1_val[2] = ((0x04 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane3_active == 1) - ill1_val[3] = ((0x04 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - - if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, - ill12_val[3]); - } - if (gen2_calib == 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x104 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane1_active == 1) - ill1_val[1] = ((0x104 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane2_active == 1) - ill1_val[2] = ((0x104 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane3_active == 1) - ill1_val[3] = ((0x104 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
- if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, - ill12_val[3]); - } + return 1; +}
- if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); - if (lane0_active == 1) - currbistresult[0] = 0; - if (lane1_active == 1) - currbistresult[1] = 0; - if (lane2_active == 1) - currbistresult[2] = 0; - if (lane3_active == 1) - currbistresult[3] = 0; - serdes_rst_seq(pllsel, lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, lane1_protocol, - lane1_rate, lane0_protocol, lane0_rate); - if (lane3_active == 1) - serdes_bist_run(3); - if (lane2_active == 1) - serdes_bist_run(2); - if (lane1_active == 1) - serdes_bist_run(1); - if (lane0_active == 1) - serdes_bist_run(0); - tempbistresult = 0; - if (lane3_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(3); - tempbistresult = tempbistresult << 1; - if (lane2_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(2); - tempbistresult = tempbistresult << 1; - if (lane1_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(1); - tempbistresult = tempbistresult << 1; - if (lane0_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(0); - Xil_Out32(0xFD410098, 0x0); - Xil_Out32(0xFD410098, 0x2); +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00002040U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
- if (itercount < 32) { - iterresult[0] = - ((iterresult[0] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[1] = - ((iterresult[1] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[2] = - ((iterresult[2] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[3] = - ((iterresult[3] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } else { - iterresult[4] = - ((iterresult[4] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[5] = - ((iterresult[5] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[6] = - ((iterresult[6] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[7] = - ((iterresult[7] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } - currbistresult[0] = - currbistresult[0] | ((tempbistresult & 0x1) == 1); - currbistresult[1] = - currbistresult[1] | ((tempbistresult & 0x2) == 0x2); - currbistresult[2] = - currbistresult[2] | ((tempbistresult & 0x4) == 0x4); - currbistresult[3] = - currbistresult[3] | ((tempbistresult & 0x8) == 0x8); + return 1; +}
- for (loop = 0; loop <= 3; loop++) { - if (currbistresult[loop] == 1 && - prevbistresult[loop] == 1) - bistpasscount[loop] = bistpasscount[loop] + 1; - if (bistpasscount[loop] < 4 && - currbistresult[loop] == 0 && itercount > 2) { - if (meancountalt_bistpasscount[loop] < - bistpasscount[loop]) { - meancountalt_bistpasscount[loop] = - bistpasscount[loop]; - meancountalt[loop] = - ((itercount - 1) - - ((bistpasscount[loop] + 1) / 2)); - } - bistpasscount[loop] = 0; - } - if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && - (currbistresult[loop] == 0 || itercount == 63) && - prevbistresult[loop] == 1) - meancount[loop] = - itercount - 1 - - ((bistpasscount[loop] + 1) / 2); - prevbistresult[loop] = currbistresult[loop]; - } - } while (++itercount < 64); +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
- for (loop = 0; loop <= 3; loop++) { - if (lane0_active == 0 && loop == 0) - continue; - if (lane1_active == 0 && loop == 1) - continue; - if (lane2_active == 0 && loop == 2) - continue; - if (lane3_active == 0 && loop == 3) - continue; + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x00800000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + return 1; +}
- if (meancount[loop] == 0) - meancount[loop] = meancountalt[loop]; +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
- if (gen2_calib != 1) { - ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x04 + meancount[loop] * 8) >= - 0x100) ? 0x10 : 0x00; - } - if (gen2_calib == 1) { - ill1_val[loop] = - ((0x104 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x104 + meancount[loop] * 8) >= - 0x200) ? 0x02 : 0x01; - } - } - if (gen2_calib != 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); - } - if (gen2_calib == 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); - } + serdes_illcalib(0, 0, 0, 0, 0, 0, 5, 0); + psu_mask_write(0xFD410010, 0x00000007U, 0x00000005U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
- if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4023E4, 0x00000010U);
- Xil_Out32(0xFD410098, 0); - if (lane0_active == 1) { - Xil_Out32(0xFD403004, 0); - Xil_Out32(0xFD403008, 0); - Xil_Out32(0xFD40300C, 0); - Xil_Out32(0xFD403010, 0); - Xil_Out32(0xFD403014, 0); - Xil_Out32(0xFD403018, 0); - Xil_Out32(0xFD40301C, 0); - Xil_Out32(0xFD403020, 0); - Xil_Out32(0xFD403024, 0); - Xil_Out32(0xFD403028, 0); - Xil_Out32(0xFD40302C, 0); - Xil_Out32(0xFD403030, 0); - Xil_Out32(0xFD403034, 0); - Xil_Out32(0xFD403038, 0); - Xil_Out32(0xFD40303C, 0); - Xil_Out32(0xFD403040, 0); - Xil_Out32(0xFD403044, 0); - Xil_Out32(0xFD403048, 0); - Xil_Out32(0xFD40304C, 0); - Xil_Out32(0xFD403050, 0); - Xil_Out32(0xFD403054, 0); - Xil_Out32(0xFD403058, 0); - Xil_Out32(0xFD403068, 1); - Xil_Out32(0xFD40306C, 0); - Xil_Out32(0xFD4010AC, 0); - psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); - } - if (lane1_active == 1) { - Xil_Out32(0xFD407004, 0); - Xil_Out32(0xFD407008, 0); - Xil_Out32(0xFD40700C, 0); - Xil_Out32(0xFD407010, 0); - Xil_Out32(0xFD407014, 0); - Xil_Out32(0xFD407018, 0); - Xil_Out32(0xFD40701C, 0); - Xil_Out32(0xFD407020, 0); - Xil_Out32(0xFD407024, 0); - Xil_Out32(0xFD407028, 0); - Xil_Out32(0xFD40702C, 0); - Xil_Out32(0xFD407030, 0); - Xil_Out32(0xFD407034, 0); - Xil_Out32(0xFD407038, 0); - Xil_Out32(0xFD40703C, 0); - Xil_Out32(0xFD407040, 0); - Xil_Out32(0xFD407044, 0); - Xil_Out32(0xFD407048, 0); - Xil_Out32(0xFD40704C, 0); - Xil_Out32(0xFD407050, 0); - Xil_Out32(0xFD407054, 0); - Xil_Out32(0xFD407058, 0); - Xil_Out32(0xFD407068, 1); - Xil_Out32(0xFD40706C, 0); - Xil_Out32(0xFD4050AC, 0); - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); - } - if (lane2_active == 1) { - Xil_Out32(0xFD40B004, 0); - Xil_Out32(0xFD40B008, 0); - Xil_Out32(0xFD40B00C, 0); - Xil_Out32(0xFD40B010, 0); - Xil_Out32(0xFD40B014, 0); - Xil_Out32(0xFD40B018, 0); - Xil_Out32(0xFD40B01C, 0); - Xil_Out32(0xFD40B020, 0); - Xil_Out32(0xFD40B024, 0); - Xil_Out32(0xFD40B028, 0); - Xil_Out32(0xFD40B02C, 0); - Xil_Out32(0xFD40B030, 0); - Xil_Out32(0xFD40B034, 0); - Xil_Out32(0xFD40B038, 0); - Xil_Out32(0xFD40B03C, 0); - Xil_Out32(0xFD40B040, 0); - Xil_Out32(0xFD40B044, 0); - Xil_Out32(0xFD40B048, 0); - Xil_Out32(0xFD40B04C, 0); - Xil_Out32(0xFD40B050, 0); - Xil_Out32(0xFD40B054, 0); - Xil_Out32(0xFD40B058, 0); - Xil_Out32(0xFD40B068, 1); - Xil_Out32(0xFD40B06C, 0); - Xil_Out32(0xFD4090AC, 0); - psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); - } - if (lane3_active == 1) { - Xil_Out32(0xFD40F004, 0); - Xil_Out32(0xFD40F008, 0); - Xil_Out32(0xFD40F00C, 0); - Xil_Out32(0xFD40F010, 0); - Xil_Out32(0xFD40F014, 0); - Xil_Out32(0xFD40F018, 0); - Xil_Out32(0xFD40F01C, 0); - Xil_Out32(0xFD40F020, 0); - Xil_Out32(0xFD40F024, 0); - Xil_Out32(0xFD40F028, 0); - Xil_Out32(0xFD40F02C, 0); - Xil_Out32(0xFD40F030, 0); - Xil_Out32(0xFD40F034, 0); - Xil_Out32(0xFD40F038, 0); - Xil_Out32(0xFD40F03C, 0); - Xil_Out32(0xFD40F040, 0); - Xil_Out32(0xFD40F044, 0); - Xil_Out32(0xFD40F048, 0); - Xil_Out32(0xFD40F04C, 0); - Xil_Out32(0xFD40F050, 0); - Xil_Out32(0xFD40F054, 0); - Xil_Out32(0xFD40F058, 0); - Xil_Out32(0xFD40F068, 1); - Xil_Out32(0xFD40F06C, 0); - Xil_Out32(0xFD40D0AC, 0); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); - } return 1; }
-static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static unsigned long psu_resetin_init_data(void) { - unsigned int rdata = 0; - unsigned int sata_gen2 = 1; - unsigned int temp_ill12 = 0; - unsigned int temp_PLL_REF_SEL_OFFSET; - unsigned int temp_TM_IQ_ILL1; - unsigned int temp_TM_E_ILL1; - unsigned int temp_tx_dig_tm_61; - unsigned int temp_tm_dig_6; - unsigned int temp_pll_fbdiv_frac_3_msb_offset; + psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
- if (lane0_protocol == 2 || lane0_protocol == 1) { - Xil_Out32(0xFD401910, 0xF3); - Xil_Out32(0xFD40193C, 0xF3); - Xil_Out32(0xFD401914, 0xF3); - Xil_Out32(0xFD401940, 0xF3); - } - if (lane1_protocol == 2 || lane1_protocol == 1) { - Xil_Out32(0xFD405910, 0xF3); - Xil_Out32(0xFD40593C, 0xF3); - Xil_Out32(0xFD405914, 0xF3); - Xil_Out32(0xFD405940, 0xF3); - } - if (lane2_protocol == 2 || lane2_protocol == 1) { - Xil_Out32(0xFD409910, 0xF3); - Xil_Out32(0xFD40993C, 0xF3); - Xil_Out32(0xFD409914, 0xF3); - Xil_Out32(0xFD409940, 0xF3); - } - if (lane3_protocol == 2 || lane3_protocol == 1) { - Xil_Out32(0xFD40D910, 0xF3); - Xil_Out32(0xFD40D93C, 0xF3); - Xil_Out32(0xFD40D914, 0xF3); - Xil_Out32(0xFD40D940, 0xF3); - } + return 1; +}
- if (sata_gen2 == 1) { - if (lane0_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); - Xil_Out32(0xFD402360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); - psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); - temp_TM_E_ILL1 = Xil_In32(0xFD401924); - Xil_Out32(0xFD4018F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); - temp_tm_dig_6 = Xil_In32(0xFD40106C); - psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD401990) & 0xF0; +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
- serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 0, 1, 0, 0); + return 1; +}
- Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD410000, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40106C, temp_tm_dig_6); - Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); - Xil_Out32(0xFD401990, temp_ill12); - Xil_Out32(0xFD401924, temp_TM_E_ILL1); - } - if (lane1_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); - Xil_Out32(0xFD406360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); - psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); - temp_TM_E_ILL1 = Xil_In32(0xFD405924); - Xil_Out32(0xFD4058F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); - temp_tm_dig_6 = Xil_In32(0xFD40506C); - psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD405990) & 0xF0; +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0;
- serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 1, 0, 0, 0, 0); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + int cur_PLLCR0;
- Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD410004, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40506C, temp_tm_dig_6); - Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); - Xil_Out32(0xFD405990, temp_ill12); - Xil_Out32(0xFD405924, temp_TM_E_ILL1); - } - if (lane2_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); - Xil_Out32(0xFD40A360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); - psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); - temp_TM_E_ILL1 = Xil_In32(0xFD409924); - Xil_Out32(0xFD4098F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); - temp_tm_dig_6 = Xil_In32(0xFD40906C); - psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD409990) & 0xF0; + cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL0PLLCR0;
- serdes_illcalib_pcie_gen1(2, 0, 0, 1, 0, 0, 0, 0, 0, 0); + cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL1PLLCR0;
- Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD410008, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40906C, temp_tm_dig_6); - Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); - Xil_Out32(0xFD409990, temp_ill12); - Xil_Out32(0xFD409924, temp_TM_E_ILL1); - } - if (lane3_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); - Xil_Out32(0xFD40E360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); - psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); - temp_TM_E_ILL1 = Xil_In32(0xFD40D924); - Xil_Out32(0xFD40D8F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); - temp_tm_dig_6 = Xil_In32(0xFD40D06C); - psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; + cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL2PLLCR0;
- serdes_illcalib_pcie_gen1(3, 1, 0, 0, 0, 0, 0, 0, 0, 0); + cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL3PLLCR0;
- Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40D06C, temp_tm_dig_6); - Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); - Xil_Out32(0xFD40D990, temp_ill12); - Xil_Out32(0xFD40D924, temp_TM_E_ILL1); - } - rdata = Xil_In32(0xFD410098); - rdata = (rdata & 0xDF); - Xil_Out32(0xFD410098, rdata); - } + cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL4PLLCR0;
- if (lane0_protocol == 2 && lane0_rate == 3) { - psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); - } - if (lane1_protocol == 2 && lane1_rate == 3) { - psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); - } - if (lane2_protocol == 2 && lane2_rate == 3) { - psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); - } - if (lane3_protocol == 2 && lane3_rate == 3) { - psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); - } + cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SLBPLLCR0;
- if (lane0_protocol == 1) { - if (lane0_rate == 0) { - serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - } else { - serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, lane0_rate, - 1); - } + cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U; + Xil_Out32(0xFD080068, 0x02120000); + Xil_Out32(0xFD081404, 0x02120000); + Xil_Out32(0xFD081444, 0x02120000); + Xil_Out32(0xFD081484, 0x02120000); + Xil_Out32(0xFD0814C4, 0x02120000); + Xil_Out32(0xFD081504, 0x02120000); + Xil_Out32(0xFD0817C4, 0x02120000); + int cur_div2; + + cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U; + int cur_fbdiv; + + cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U; + dpll_prog(1, 49, 63, 625, 3, 3, 2); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_retry--; } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0;
- if (lane0_protocol == 3) - Xil_Out32(0xFD401914, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401940, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401990, 0x20); - if (lane0_protocol == 3) - Xil_Out32(0xFD401924, 0x37); + Xil_Out32(0xFD080004U, 0x00040063U); + Xil_Out32(0xFD0800C0U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
- if (lane1_protocol == 3) - Xil_Out32(0xFD405914, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405940, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405990, 0x20); - if (lane1_protocol == 3) - Xil_Out32(0xFD405924, 0x37); + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD070010U, 0x80000018U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018);
- if (lane2_protocol == 3) - Xil_Out32(0xFD409914, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409940, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409990, 0x20); - if (lane2_protocol == 3) - Xil_Out32(0xFD409924, 0x37); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000331U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018);
- if (lane3_protocol == 3) - Xil_Out32(0xFD40D914, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D940, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D990, 0x20); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D924, 0x37); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000B36U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018);
- return 1; -} + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000C56U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018);
-static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, - int d_lock_cnt, int d_lfhf, int d_cp, int d_res) -{ - unsigned int pll_ctrl_regval; - unsigned int pll_status_regval; + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000E19U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U); - pll_ctrl_regval = pll_ctrl_regval | (div2 << 16); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00001616U); + Xil_Out32(0xFD070010U, 0x80000018U); + Xil_Out32(0xFD070010U, 0x80000010U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U); + prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); + prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U); + prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); - pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U); - pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25); - Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + Xil_Out32(0xFD080068, cur_PLLCR0); + Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0); + Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0); + Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0); + Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0); + Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0); + Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); - pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U); - pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13); - Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2); + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U); - pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10); - Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U); + prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); - pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U); - pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5); - Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); - pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU); - pll_ctrl_regval = pll_ctrl_regval | (d_res << 0); - Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U); - pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); + prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U); + prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); - pll_ctrl_regval = pll_ctrl_regval | (1 << 3); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0014FE01);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); - pll_ctrl_regval = pll_ctrl_regval | (1 << 0); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + regval = Xil_In32(0xFD080030); + while (regval != 0x8000007E) + regval = Xil_In32(0xFD080030);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); - pll_ctrl_regval = pll_ctrl_regval | (0 << 0); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + Xil_Out32(0xFD080200U, 0x000091C7U); + regval = Xil_In32(0xFD080030); + while (regval != 0x80008FFF) + regval = Xil_In32(0xFD080030);
- pll_status_regval = 0x00000000; - while ((pll_status_regval & 0x00000002U) != 0x00000002U) - pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044)); + Xil_Out32(0xFD080200U, 0x800091C7U); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U); + prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U); + Xil_Out32(0xFD070180U, 0x02160010U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + for (int tp = 0; tp < 4000; tp++) + regval = Xil_In32(0xFD070018);
- pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); - pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); - pll_ctrl_regval = pll_ctrl_regval | (0 << 3); - Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U); + prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U); + prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U); + prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U); + prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U); + prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U); + prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U); + prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U); + prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU); + prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U); + + return 1; }
static int serdes_enb_coarse_saturation(void) diff --git a/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c index 2adcad04d8..f98ad8af82 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c @@ -6,1692 +6,1687 @@ #include <asm/arch/psu_init_gpl.h> #include <xil_io.h>
-static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate); - -static unsigned long psu_pll_init_data(void) +static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) { - psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000002U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); - psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000002U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); - psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000004U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + Xil_Out32(0xFD410098, 0x00000000); + Xil_Out32(0xFD401010, 0x00000040); + Xil_Out32(0xFD405010, 0x00000040); + Xil_Out32(0xFD409010, 0x00000040); + Xil_Out32(0xFD40D010, 0x00000040); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + Xil_Out32(0xFD410098, 0x00000004); + mask_delay(50); + if (lane0_rate == 1) + Xil_Out32(0xFD410098, 0x0000000E); + Xil_Out32(0xFD410098, 0x00000006); + if (lane0_rate == 1) { + Xil_Out32(0xFD40000C, 0x00000004); + Xil_Out32(0xFD40400C, 0x00000004); + Xil_Out32(0xFD40800C, 0x00000004); + Xil_Out32(0xFD40C00C, 0x00000004); + Xil_Out32(0xFD410098, 0x00000007); + mask_delay(400); + Xil_Out32(0xFD40000C, 0x0000000C); + Xil_Out32(0xFD40400C, 0x0000000C); + Xil_Out32(0xFD40800C, 0x0000000C); + Xil_Out32(0xFD40C00C, 0x0000000C); + mask_delay(15); + Xil_Out32(0xFD410098, 0x0000000F); + mask_delay(100); + } + if (lane0_protocol != 0) + mask_poll(0xFD4023E4, 0x00000010U); + if (lane1_protocol != 0) + mask_poll(0xFD4063E4, 0x00000010U); + if (lane2_protocol != 0) + mask_poll(0xFD40A3E4, 0x00000010U); + if (lane3_protocol != 0) + mask_poll(0xFD40E3E4, 0x00000010U); + mask_delay(50); + Xil_Out32(0xFD401010, 0x000000C0); + Xil_Out32(0xFD405010, 0x000000C0); + Xil_Out32(0xFD409010, 0x000000C0); + Xil_Out32(0xFD40D010, 0x000000C0); + Xil_Out32(0xFD401010, 0x00000080); + Xil_Out32(0xFD405010, 0x00000080); + Xil_Out32(0xFD409010, 0x00000080); + Xil_Out32(0xFD40D010, 0x00000080);
+ Xil_Out32(0xFD402084, 0x000000C0); + Xil_Out32(0xFD406084, 0x000000C0); + Xil_Out32(0xFD40A084, 0x000000C0); + Xil_Out32(0xFD40E084, 0x000000C0); + mask_delay(50); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + mask_delay(50); + Xil_Out32(0xFD401010, 0x00000000); + Xil_Out32(0xFD405010, 0x00000000); + Xil_Out32(0xFD409010, 0x00000000); + Xil_Out32(0xFD40D010, 0x00000000); + Xil_Out32(0xFD402084, 0x00000000); + Xil_Out32(0xFD406084, 0x00000000); + Xil_Out32(0xFD40A084, 0x00000000); + Xil_Out32(0xFD40E084, 0x00000000); + mask_delay(500); return 1; }
-static unsigned long psu_clock_init_data(void) +static int serdes_bist_static_settings(u32 lane_active) { - psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); - psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); - psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); - psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); - psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); - psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); - psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); - psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); - psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); - psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); - psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); - psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); - psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); - psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); - psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); - psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + if (lane_active == 0) { + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + Xil_Out32(0xFD403068, 0x1); + Xil_Out32(0xFD40306C, 0x1); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403008, 0x0); + Xil_Out32(0xFD40300C, 0xF4); + Xil_Out32(0xFD403010, 0x0); + Xil_Out32(0xFD403014, 0x0); + Xil_Out32(0xFD403018, 0x00); + Xil_Out32(0xFD40301C, 0xFB); + Xil_Out32(0xFD403020, 0xFF); + Xil_Out32(0xFD403024, 0x0); + Xil_Out32(0xFD403028, 0x00); + Xil_Out32(0xFD40302C, 0x00); + Xil_Out32(0xFD403030, 0x4A); + Xil_Out32(0xFD403034, 0x4A); + Xil_Out32(0xFD403038, 0x4A); + Xil_Out32(0xFD40303C, 0x4A); + Xil_Out32(0xFD403040, 0x0); + Xil_Out32(0xFD403044, 0x14); + Xil_Out32(0xFD403048, 0x02); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + } + if (lane_active == 1) { + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + Xil_Out32(0xFD407068, 0x1); + Xil_Out32(0xFD40706C, 0x1); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407008, 0x0); + Xil_Out32(0xFD40700C, 0xF4); + Xil_Out32(0xFD407010, 0x0); + Xil_Out32(0xFD407014, 0x0); + Xil_Out32(0xFD407018, 0x00); + Xil_Out32(0xFD40701C, 0xFB); + Xil_Out32(0xFD407020, 0xFF); + Xil_Out32(0xFD407024, 0x0); + Xil_Out32(0xFD407028, 0x00); + Xil_Out32(0xFD40702C, 0x00); + Xil_Out32(0xFD407030, 0x4A); + Xil_Out32(0xFD407034, 0x4A); + Xil_Out32(0xFD407038, 0x4A); + Xil_Out32(0xFD40703C, 0x4A); + Xil_Out32(0xFD407040, 0x0); + Xil_Out32(0xFD407044, 0x14); + Xil_Out32(0xFD407048, 0x02); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + } + + if (lane_active == 2) { + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40B068, 0x1); + Xil_Out32(0xFD40B06C, 0x1); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B008, 0x0); + Xil_Out32(0xFD40B00C, 0xF4); + Xil_Out32(0xFD40B010, 0x0); + Xil_Out32(0xFD40B014, 0x0); + Xil_Out32(0xFD40B018, 0x00); + Xil_Out32(0xFD40B01C, 0xFB); + Xil_Out32(0xFD40B020, 0xFF); + Xil_Out32(0xFD40B024, 0x0); + Xil_Out32(0xFD40B028, 0x00); + Xil_Out32(0xFD40B02C, 0x00); + Xil_Out32(0xFD40B030, 0x4A); + Xil_Out32(0xFD40B034, 0x4A); + Xil_Out32(0xFD40B038, 0x4A); + Xil_Out32(0xFD40B03C, 0x4A); + Xil_Out32(0xFD40B040, 0x0); + Xil_Out32(0xFD40B044, 0x14); + Xil_Out32(0xFD40B048, 0x02); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + }
+ if (lane_active == 3) { + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40F068, 0x1); + Xil_Out32(0xFD40F06C, 0x1); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F008, 0x0); + Xil_Out32(0xFD40F00C, 0xF4); + Xil_Out32(0xFD40F010, 0x0); + Xil_Out32(0xFD40F014, 0x0); + Xil_Out32(0xFD40F018, 0x00); + Xil_Out32(0xFD40F01C, 0xFB); + Xil_Out32(0xFD40F020, 0xFF); + Xil_Out32(0xFD40F024, 0x0); + Xil_Out32(0xFD40F028, 0x00); + Xil_Out32(0xFD40F02C, 0x00); + Xil_Out32(0xFD40F030, 0x4A); + Xil_Out32(0xFD40F034, 0x4A); + Xil_Out32(0xFD40F038, 0x4A); + Xil_Out32(0xFD40F03C, 0x4A); + Xil_Out32(0xFD40F040, 0x0); + Xil_Out32(0xFD40F044, 0x14); + Xil_Out32(0xFD40F048, 0x02); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + } return 1; }
-static unsigned long psu_ddr_init_data(void) +static int serdes_bist_run(u32 lane_active) { - psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); - psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); - psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); - psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); - psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); - psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U); - psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); - psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); - psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); - psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U); - psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); - psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); - psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); - psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U); - psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); - psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U); - psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); - psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U); - psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); - psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); - psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); - psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); - psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); - psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U); - psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); - psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU); - psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); - psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); - psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); - psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); - psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); - psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); - psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U); - psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); - psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); - psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); - psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU); - psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U); - psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); - psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); - psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); - psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); - psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); - psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); - psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); - psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); - psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); - psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); - psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); - psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); - psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); - psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); - psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); - psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU); - psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); - psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); - psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); - psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); - psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); - psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); - psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); - psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); - psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); - psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); - psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); - psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); - psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); - psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U); - psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); - psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); - psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U); - psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U); - psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); - psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); - psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); - psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U); - psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); - psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); - psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); - psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U); - psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U); - psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU); - psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); - psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); - psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); - psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); - psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); - psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U); - psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); - psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); - psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); - psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); - psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); - psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); - psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); - psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); - psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); - psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); - psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); - psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); - psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); - psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); - psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); - psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); - psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); - psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); - psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); - psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U); - psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); - psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); - psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); - psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); - psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); - psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); - psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); - - return 1; -} - -static unsigned long psu_ddr_qos_init_data(void) -{ - psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); - - return 1; -} - -static unsigned long psu_mio_init_data(void) -{ - psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U); - psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); - psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); - psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); - - return 1; -} - -static unsigned long psu_peripherals_pre_init_data(void) -{ - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); - psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); - - return 1; -} - -static unsigned long psu_peripherals_init_data(void) -{ - psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); - psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); - psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); - psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); - psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); - psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); - - mask_delay(1); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); - - mask_delay(5); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); - - return 1; -} - -static unsigned long psu_serdes_init_data(void) -{ - psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); - psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); - psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); - psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); - psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); - psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); - psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); - psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); - psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); - psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); - psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); - psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); - psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); - psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); - psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); - psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); - psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); - psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); - psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); - psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); - - serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0); - psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); - psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); - psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); - psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); - psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); - psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); - - return 1; -} - -static unsigned long psu_resetout_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); - psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); - psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); - psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); - psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); - psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); - mask_poll(0xFD40A3E4, 0x00000010U); - mask_poll(0xFD40E3E4, 0x00000010U); - psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); - psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); - psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); - psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); - - return 1; -} - -static unsigned long psu_resetin_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); - - return 1; -} - -static unsigned long psu_afi_config(void) -{ - psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); - psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); - psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U); - - return 1; -} - -static unsigned long psu_ddr_phybringup_data(void) -{ - unsigned int regval = 0; - unsigned int pll_retry = 10; - unsigned int pll_locked = 0; - int cur_R006_tREFPRD; - - while ((pll_retry > 0) && (!pll_locked)) { - Xil_Out32(0xFD080004, 0x00040010); - Xil_Out32(0xFD080004, 0x00040011); - - while ((Xil_In32(0xFD080030) & 0x1) != 1) - ; - pll_locked = (Xil_In32(0xFD080030) & 0x80000000) - >> 31; - pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; - pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) - >> 16; - pll_retry--; + if (lane_active == 0) { + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); } - Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); - if (!pll_locked) - return 0; - - Xil_Out32(0xFD080004U, 0x00040063U); - - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) - ; - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) - ; - Xil_Out32(0xFD0701B0U, 0x00000001U); - Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) - ; - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0004FE01); - regval = Xil_In32(0xFD080030); - while (regval != 0x80000FFF) - regval = Xil_In32(0xFD080030); - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - - Xil_Out32(0xFD080200U, 0x100091C7U); - - cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; - prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - - prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); - prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); - - Xil_Out32(0xFD080004, 0x00060001); - regval = Xil_In32(0xFD080030); - while ((regval & 0x80004001) != 0x80004001) - regval = Xil_In32(0xFD080030); - - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - - prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); - prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); - - Xil_Out32(0xFD080200U, 0x800091C7U); - prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - - Xil_Out32(0xFD080004, 0x0000C001); - regval = Xil_In32(0xFD080030); - while ((regval & 0x80000C01) != 0x80000C01) - regval = Xil_In32(0xFD080030); + if (lane_active == 1) { + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); + } + if (lane_active == 2) { + psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + } + if (lane_active == 3) { + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + } + mask_delay(100); + return 1; +}
- Xil_Out32(0xFD070180U, 0x01000040U); - Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); +static int serdes_bist_result(u32 lane_active) +{ + u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0;
+ if (lane_active == 0) { + pkt_cnt_l0 = Xil_In32(0xFD40304C); + pkt_cnt_h0 = Xil_In32(0xFD403050); + err_cnt_l0 = Xil_In32(0xFD403054); + err_cnt_h0 = Xil_In32(0xFD403058); + } + if (lane_active == 1) { + pkt_cnt_l0 = Xil_In32(0xFD40704C); + pkt_cnt_h0 = Xil_In32(0xFD407050); + err_cnt_l0 = Xil_In32(0xFD407054); + err_cnt_h0 = Xil_In32(0xFD407058); + } + if (lane_active == 2) { + pkt_cnt_l0 = Xil_In32(0xFD40B04C); + pkt_cnt_h0 = Xil_In32(0xFD40B050); + err_cnt_l0 = Xil_In32(0xFD40B054); + err_cnt_h0 = Xil_In32(0xFD40B058); + } + if (lane_active == 3) { + pkt_cnt_l0 = Xil_In32(0xFD40F04C); + pkt_cnt_h0 = Xil_In32(0xFD40F050); + err_cnt_l0 = Xil_In32(0xFD40F054); + err_cnt_h0 = Xil_In32(0xFD40F058); + } + if (lane_active == 0) + Xil_Out32(0xFD403004, 0x0); + if (lane_active == 1) + Xil_Out32(0xFD407004, 0x0); + if (lane_active == 2) + Xil_Out32(0xFD40B004, 0x0); + if (lane_active == 3) + Xil_Out32(0xFD40F004, 0x0); + if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || + (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) + return 0; return 1; }
-static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate, + u32 gen2_calib) { - Xil_Out32(0xFD410098, 0x00000000); - Xil_Out32(0xFD401010, 0x00000040); - Xil_Out32(0xFD405010, 0x00000040); - Xil_Out32(0xFD409010, 0x00000040); - Xil_Out32(0xFD40D010, 0x00000040); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - Xil_Out32(0xFD410098, 0x00000004); - mask_delay(50); - if (lane0_rate == 1) - Xil_Out32(0xFD410098, 0x0000000E); - Xil_Out32(0xFD410098, 0x00000006); - if (lane0_rate == 1) { - Xil_Out32(0xFD40000C, 0x00000004); - Xil_Out32(0xFD40400C, 0x00000004); - Xil_Out32(0xFD40800C, 0x00000004); - Xil_Out32(0xFD40C00C, 0x00000004); - Xil_Out32(0xFD410098, 0x00000007); - mask_delay(400); - Xil_Out32(0xFD40000C, 0x0000000C); - Xil_Out32(0xFD40400C, 0x0000000C); - Xil_Out32(0xFD40800C, 0x0000000C); - Xil_Out32(0xFD40C00C, 0x0000000C); - mask_delay(15); - Xil_Out32(0xFD410098, 0x0000000F); - mask_delay(100); + u64 tempbistresult; + u32 currbistresult[4]; + u32 prevbistresult[4]; + u32 itercount = 0; + u32 ill12_val[4], ill1_val[4]; + u32 loop = 0; + u32 iterresult[8]; + u32 meancount[4]; + u32 bistpasscount[4]; + u32 meancountalt[4]; + u32 meancountalt_bistpasscount[4]; + u32 lane0_active; + u32 lane1_active; + u32 lane2_active; + u32 lane3_active; + + lane0_active = (lane0_protocol == 1); + lane1_active = (lane1_protocol == 1); + lane2_active = (lane2_protocol == 1); + lane3_active = (lane3_protocol == 1); + for (loop = 0; loop <= 3; loop++) { + iterresult[loop] = 0; + iterresult[loop + 4] = 0; + meancountalt[loop] = 0; + meancountalt_bistpasscount[loop] = 0; + meancount[loop] = 0; + prevbistresult[loop] = 0; + bistpasscount[loop] = 0; } - if (lane0_protocol != 0) - mask_poll(0xFD4023E4, 0x00000010U); - if (lane1_protocol != 0) - mask_poll(0xFD4063E4, 0x00000010U); - if (lane2_protocol != 0) - mask_poll(0xFD40A3E4, 0x00000010U); - if (lane3_protocol != 0) - mask_poll(0xFD40E3E4, 0x00000010U); - mask_delay(50); - Xil_Out32(0xFD401010, 0x000000C0); - Xil_Out32(0xFD405010, 0x000000C0); - Xil_Out32(0xFD409010, 0x000000C0); - Xil_Out32(0xFD40D010, 0x000000C0); - Xil_Out32(0xFD401010, 0x00000080); - Xil_Out32(0xFD405010, 0x00000080); - Xil_Out32(0xFD409010, 0x00000080); - Xil_Out32(0xFD40D010, 0x00000080); + itercount = 0; + if (lane0_active) + serdes_bist_static_settings(0); + if (lane1_active) + serdes_bist_static_settings(1); + if (lane2_active) + serdes_bist_static_settings(2); + if (lane3_active) + serdes_bist_static_settings(3); + do { + if (gen2_calib != 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x04 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane1_active == 1) + ill1_val[1] = ((0x04 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane2_active == 1) + ill1_val[2] = ((0x04 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) + ill1_val[3] = ((0x04 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, + ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x104 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane1_active == 1) + ill1_val[1] = ((0x104 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane2_active == 1) + ill1_val[2] = ((0x104 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane3_active == 1) + ill1_val[3] = ((0x104 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, + ill12_val[3]); + } + + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); + if (lane0_active == 1) + currbistresult[0] = 0; + if (lane1_active == 1) + currbistresult[1] = 0; + if (lane2_active == 1) + currbistresult[2] = 0; + if (lane3_active == 1) + currbistresult[3] = 0; + serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol, + lane2_rate, lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate); + if (lane3_active == 1) + serdes_bist_run(3); + if (lane2_active == 1) + serdes_bist_run(2); + if (lane1_active == 1) + serdes_bist_run(1); + if (lane0_active == 1) + serdes_bist_run(0); + tempbistresult = 0; + if (lane3_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(3); + tempbistresult = tempbistresult << 1; + if (lane2_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(2); + tempbistresult = tempbistresult << 1; + if (lane1_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(1); + tempbistresult = tempbistresult << 1; + if (lane0_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(0); + Xil_Out32(0xFD410098, 0x0); + Xil_Out32(0xFD410098, 0x2);
- Xil_Out32(0xFD402084, 0x000000C0); - Xil_Out32(0xFD406084, 0x000000C0); - Xil_Out32(0xFD40A084, 0x000000C0); - Xil_Out32(0xFD40E084, 0x000000C0); - mask_delay(50); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - mask_delay(50); - Xil_Out32(0xFD401010, 0x00000000); - Xil_Out32(0xFD405010, 0x00000000); - Xil_Out32(0xFD409010, 0x00000000); - Xil_Out32(0xFD40D010, 0x00000000); - Xil_Out32(0xFD402084, 0x00000000); - Xil_Out32(0xFD406084, 0x00000000); - Xil_Out32(0xFD40A084, 0x00000000); - Xil_Out32(0xFD40E084, 0x00000000); - mask_delay(500); - return 1; -} + if (itercount < 32) { + iterresult[0] = + ((iterresult[0] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[1] = + ((iterresult[1] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[2] = + ((iterresult[2] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[3] = + ((iterresult[3] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } else { + iterresult[4] = + ((iterresult[4] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[5] = + ((iterresult[5] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[6] = + ((iterresult[6] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[7] = + ((iterresult[7] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } + currbistresult[0] = + currbistresult[0] | ((tempbistresult & 0x1) == 1); + currbistresult[1] = + currbistresult[1] | ((tempbistresult & 0x2) == 0x2); + currbistresult[2] = + currbistresult[2] | ((tempbistresult & 0x4) == 0x4); + currbistresult[3] = + currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
-static int serdes_bist_static_settings(u32 lane_active) -{ - if (lane_active == 0) { - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - Xil_Out32(0xFD403068, 0x1); - Xil_Out32(0xFD40306C, 0x1); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403008, 0x0); - Xil_Out32(0xFD40300C, 0xF4); - Xil_Out32(0xFD403010, 0x0); - Xil_Out32(0xFD403014, 0x0); - Xil_Out32(0xFD403018, 0x00); - Xil_Out32(0xFD40301C, 0xFB); - Xil_Out32(0xFD403020, 0xFF); - Xil_Out32(0xFD403024, 0x0); - Xil_Out32(0xFD403028, 0x00); - Xil_Out32(0xFD40302C, 0x00); - Xil_Out32(0xFD403030, 0x4A); - Xil_Out32(0xFD403034, 0x4A); - Xil_Out32(0xFD403038, 0x4A); - Xil_Out32(0xFD40303C, 0x4A); - Xil_Out32(0xFD403040, 0x0); - Xil_Out32(0xFD403044, 0x14); - Xil_Out32(0xFD403048, 0x02); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - } - if (lane_active == 1) { - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - Xil_Out32(0xFD407068, 0x1); - Xil_Out32(0xFD40706C, 0x1); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407008, 0x0); - Xil_Out32(0xFD40700C, 0xF4); - Xil_Out32(0xFD407010, 0x0); - Xil_Out32(0xFD407014, 0x0); - Xil_Out32(0xFD407018, 0x00); - Xil_Out32(0xFD40701C, 0xFB); - Xil_Out32(0xFD407020, 0xFF); - Xil_Out32(0xFD407024, 0x0); - Xil_Out32(0xFD407028, 0x00); - Xil_Out32(0xFD40702C, 0x00); - Xil_Out32(0xFD407030, 0x4A); - Xil_Out32(0xFD407034, 0x4A); - Xil_Out32(0xFD407038, 0x4A); - Xil_Out32(0xFD40703C, 0x4A); - Xil_Out32(0xFD407040, 0x0); - Xil_Out32(0xFD407044, 0x14); - Xil_Out32(0xFD407048, 0x02); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - } + for (loop = 0; loop <= 3; loop++) { + if (currbistresult[loop] == 1 && prevbistresult[loop] == 1) + bistpasscount[loop] = bistpasscount[loop] + 1; + if (bistpasscount[loop] < 4 && + currbistresult[loop] == 0 && itercount > 2) { + if (meancountalt_bistpasscount[loop] < + bistpasscount[loop]) { + meancountalt_bistpasscount[loop] = + bistpasscount[loop]; + meancountalt[loop] = + ((itercount - 1) - + ((bistpasscount[loop] + 1) / 2)); + } + bistpasscount[loop] = 0; + } + if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && + (currbistresult[loop] == 0 || itercount == 63) && + prevbistresult[loop] == 1) + meancount[loop] = + (itercount - 1) - + ((bistpasscount[loop] + 1) / 2); + prevbistresult[loop] = currbistresult[loop]; + } + } while (++itercount < 64);
- if (lane_active == 2) { - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40B068, 0x1); - Xil_Out32(0xFD40B06C, 0x1); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B008, 0x0); - Xil_Out32(0xFD40B00C, 0xF4); - Xil_Out32(0xFD40B010, 0x0); - Xil_Out32(0xFD40B014, 0x0); - Xil_Out32(0xFD40B018, 0x00); - Xil_Out32(0xFD40B01C, 0xFB); - Xil_Out32(0xFD40B020, 0xFF); - Xil_Out32(0xFD40B024, 0x0); - Xil_Out32(0xFD40B028, 0x00); - Xil_Out32(0xFD40B02C, 0x00); - Xil_Out32(0xFD40B030, 0x4A); - Xil_Out32(0xFD40B034, 0x4A); - Xil_Out32(0xFD40B038, 0x4A); - Xil_Out32(0xFD40B03C, 0x4A); - Xil_Out32(0xFD40B040, 0x0); - Xil_Out32(0xFD40B044, 0x14); - Xil_Out32(0xFD40B048, 0x02); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - } + for (loop = 0; loop <= 3; loop++) { + if (lane0_active == 0 && loop == 0) + continue; + if (lane1_active == 0 && loop == 1) + continue; + if (lane2_active == 0 && loop == 2) + continue; + if (lane3_active == 0 && loop == 3) + continue;
- if (lane_active == 3) { - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40F068, 0x1); - Xil_Out32(0xFD40F06C, 0x1); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F008, 0x0); - Xil_Out32(0xFD40F00C, 0xF4); - Xil_Out32(0xFD40F010, 0x0); - Xil_Out32(0xFD40F014, 0x0); - Xil_Out32(0xFD40F018, 0x00); - Xil_Out32(0xFD40F01C, 0xFB); - Xil_Out32(0xFD40F020, 0xFF); - Xil_Out32(0xFD40F024, 0x0); - Xil_Out32(0xFD40F028, 0x00); - Xil_Out32(0xFD40F02C, 0x00); - Xil_Out32(0xFD40F030, 0x4A); - Xil_Out32(0xFD40F034, 0x4A); - Xil_Out32(0xFD40F038, 0x4A); - Xil_Out32(0xFD40F03C, 0x4A); - Xil_Out32(0xFD40F040, 0x0); - Xil_Out32(0xFD40F044, 0x14); - Xil_Out32(0xFD40F048, 0x02); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - } - return 1; -} + if (meancount[loop] == 0) + meancount[loop] = meancountalt[loop];
-static int serdes_bist_run(u32 lane_active) -{ - if (lane_active == 0) { - psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); - } - if (lane_active == 1) { - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); - } - if (lane_active == 2) { - psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + if (gen2_calib != 1) { + ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x04 + meancount[loop] * 8) >= + 0x100) ? 0x10 : 0x00; + Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]); + Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]); + Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]); + Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]); + } + if (gen2_calib == 1) { + ill1_val[loop] = + ((0x104 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x104 + meancount[loop] * 8) >= + 0x200) ? 0x02 : 0x01; + Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]); + Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]); + Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]); + Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]); + } } - if (lane_active == 3) { - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + if (gen2_calib != 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); } - mask_delay(100); - return 1; -}
-static int serdes_bist_result(u32 lane_active) -{ - u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
- if (lane_active == 0) { - pkt_cnt_l0 = Xil_In32(0xFD40304C); - pkt_cnt_h0 = Xil_In32(0xFD403050); - err_cnt_l0 = Xil_In32(0xFD403054); - err_cnt_h0 = Xil_In32(0xFD403058); - } - if (lane_active == 1) { - pkt_cnt_l0 = Xil_In32(0xFD40704C); - pkt_cnt_h0 = Xil_In32(0xFD407050); - err_cnt_l0 = Xil_In32(0xFD407054); - err_cnt_h0 = Xil_In32(0xFD407058); - } - if (lane_active == 2) { - pkt_cnt_l0 = Xil_In32(0xFD40B04C); - pkt_cnt_h0 = Xil_In32(0xFD40B050); - err_cnt_l0 = Xil_In32(0xFD40B054); - err_cnt_h0 = Xil_In32(0xFD40B058); + Xil_Out32(0xFD410098, 0); + if (lane0_active == 1) { + Xil_Out32(0xFD403004, 0); + Xil_Out32(0xFD403008, 0); + Xil_Out32(0xFD40300C, 0); + Xil_Out32(0xFD403010, 0); + Xil_Out32(0xFD403014, 0); + Xil_Out32(0xFD403018, 0); + Xil_Out32(0xFD40301C, 0); + Xil_Out32(0xFD403020, 0); + Xil_Out32(0xFD403024, 0); + Xil_Out32(0xFD403028, 0); + Xil_Out32(0xFD40302C, 0); + Xil_Out32(0xFD403030, 0); + Xil_Out32(0xFD403034, 0); + Xil_Out32(0xFD403038, 0); + Xil_Out32(0xFD40303C, 0); + Xil_Out32(0xFD403040, 0); + Xil_Out32(0xFD403044, 0); + Xil_Out32(0xFD403048, 0); + Xil_Out32(0xFD40304C, 0); + Xil_Out32(0xFD403050, 0); + Xil_Out32(0xFD403054, 0); + Xil_Out32(0xFD403058, 0); + Xil_Out32(0xFD403068, 1); + Xil_Out32(0xFD40306C, 0); + Xil_Out32(0xFD4010AC, 0); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); } - if (lane_active == 3) { - pkt_cnt_l0 = Xil_In32(0xFD40F04C); - pkt_cnt_h0 = Xil_In32(0xFD40F050); - err_cnt_l0 = Xil_In32(0xFD40F054); - err_cnt_h0 = Xil_In32(0xFD40F058); + if (lane1_active == 1) { + Xil_Out32(0xFD407004, 0); + Xil_Out32(0xFD407008, 0); + Xil_Out32(0xFD40700C, 0); + Xil_Out32(0xFD407010, 0); + Xil_Out32(0xFD407014, 0); + Xil_Out32(0xFD407018, 0); + Xil_Out32(0xFD40701C, 0); + Xil_Out32(0xFD407020, 0); + Xil_Out32(0xFD407024, 0); + Xil_Out32(0xFD407028, 0); + Xil_Out32(0xFD40702C, 0); + Xil_Out32(0xFD407030, 0); + Xil_Out32(0xFD407034, 0); + Xil_Out32(0xFD407038, 0); + Xil_Out32(0xFD40703C, 0); + Xil_Out32(0xFD407040, 0); + Xil_Out32(0xFD407044, 0); + Xil_Out32(0xFD407048, 0); + Xil_Out32(0xFD40704C, 0); + Xil_Out32(0xFD407050, 0); + Xil_Out32(0xFD407054, 0); + Xil_Out32(0xFD407058, 0); + Xil_Out32(0xFD407068, 1); + Xil_Out32(0xFD40706C, 0); + Xil_Out32(0xFD4050AC, 0); + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); } - if (lane_active == 0) - Xil_Out32(0xFD403004, 0x0); - if (lane_active == 1) - Xil_Out32(0xFD407004, 0x0); - if (lane_active == 2) - Xil_Out32(0xFD40B004, 0x0); - if (lane_active == 3) - Xil_Out32(0xFD40F004, 0x0); - if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || - (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) - return 0; - return 1; -} - -static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate, - u32 gen2_calib) -{ - u64 tempbistresult; - u32 currbistresult[4]; - u32 prevbistresult[4]; - u32 itercount = 0; - u32 ill12_val[4], ill1_val[4]; - u32 loop = 0; - u32 iterresult[8]; - u32 meancount[4]; - u32 bistpasscount[4]; - u32 meancountalt[4]; - u32 meancountalt_bistpasscount[4]; - u32 lane0_active; - u32 lane1_active; - u32 lane2_active; - u32 lane3_active; - - lane0_active = (lane0_protocol == 1); - lane1_active = (lane1_protocol == 1); - lane2_active = (lane2_protocol == 1); - lane3_active = (lane3_protocol == 1); - for (loop = 0; loop <= 3; loop++) { - iterresult[loop] = 0; - iterresult[loop + 4] = 0; - meancountalt[loop] = 0; - meancountalt_bistpasscount[loop] = 0; - meancount[loop] = 0; - prevbistresult[loop] = 0; - bistpasscount[loop] = 0; + if (lane2_active == 1) { + Xil_Out32(0xFD40B004, 0); + Xil_Out32(0xFD40B008, 0); + Xil_Out32(0xFD40B00C, 0); + Xil_Out32(0xFD40B010, 0); + Xil_Out32(0xFD40B014, 0); + Xil_Out32(0xFD40B018, 0); + Xil_Out32(0xFD40B01C, 0); + Xil_Out32(0xFD40B020, 0); + Xil_Out32(0xFD40B024, 0); + Xil_Out32(0xFD40B028, 0); + Xil_Out32(0xFD40B02C, 0); + Xil_Out32(0xFD40B030, 0); + Xil_Out32(0xFD40B034, 0); + Xil_Out32(0xFD40B038, 0); + Xil_Out32(0xFD40B03C, 0); + Xil_Out32(0xFD40B040, 0); + Xil_Out32(0xFD40B044, 0); + Xil_Out32(0xFD40B048, 0); + Xil_Out32(0xFD40B04C, 0); + Xil_Out32(0xFD40B050, 0); + Xil_Out32(0xFD40B054, 0); + Xil_Out32(0xFD40B058, 0); + Xil_Out32(0xFD40B068, 1); + Xil_Out32(0xFD40B06C, 0); + Xil_Out32(0xFD4090AC, 0); + psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); } - itercount = 0; - if (lane0_active) - serdes_bist_static_settings(0); - if (lane1_active) - serdes_bist_static_settings(1); - if (lane2_active) - serdes_bist_static_settings(2); - if (lane3_active) - serdes_bist_static_settings(3); - do { - if (gen2_calib != 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x04 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane1_active == 1) - ill1_val[1] = ((0x04 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane2_active == 1) - ill1_val[2] = ((0x04 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane3_active == 1) - ill1_val[3] = ((0x04 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) { + Xil_Out32(0xFD40F004, 0); + Xil_Out32(0xFD40F008, 0); + Xil_Out32(0xFD40F00C, 0); + Xil_Out32(0xFD40F010, 0); + Xil_Out32(0xFD40F014, 0); + Xil_Out32(0xFD40F018, 0); + Xil_Out32(0xFD40F01C, 0); + Xil_Out32(0xFD40F020, 0); + Xil_Out32(0xFD40F024, 0); + Xil_Out32(0xFD40F028, 0); + Xil_Out32(0xFD40F02C, 0); + Xil_Out32(0xFD40F030, 0); + Xil_Out32(0xFD40F034, 0); + Xil_Out32(0xFD40F038, 0); + Xil_Out32(0xFD40F03C, 0); + Xil_Out32(0xFD40F040, 0); + Xil_Out32(0xFD40F044, 0); + Xil_Out32(0xFD40F048, 0); + Xil_Out32(0xFD40F04C, 0); + Xil_Out32(0xFD40F050, 0); + Xil_Out32(0xFD40F054, 0); + Xil_Out32(0xFD40F058, 0); + Xil_Out32(0xFD40F068, 1); + Xil_Out32(0xFD40F06C, 0); + Xil_Out32(0xFD40D0AC, 0); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); + } + return 1; +}
- if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, - ill12_val[3]); - } - if (gen2_calib == 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x104 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane1_active == 1) - ill1_val[1] = ((0x104 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane2_active == 1) - ill1_val[2] = ((0x104 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane3_active == 1) - ill1_val[3] = ((0x104 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; +static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) +{ + unsigned int rdata = 0; + unsigned int sata_gen2 = 1; + unsigned int temp_ill12 = 0; + unsigned int temp_PLL_REF_SEL_OFFSET; + unsigned int temp_TM_IQ_ILL1; + unsigned int temp_TM_E_ILL1; + unsigned int temp_tx_dig_tm_61; + unsigned int temp_tm_dig_6; + unsigned int temp_pll_fbdiv_frac_3_msb_offset;
- if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, - ill12_val[3]); - } + if (lane0_protocol == 2 || lane0_protocol == 1) { + Xil_Out32(0xFD401910, 0xF3); + Xil_Out32(0xFD40193C, 0xF3); + Xil_Out32(0xFD401914, 0xF3); + Xil_Out32(0xFD401940, 0xF3); + } + if (lane1_protocol == 2 || lane1_protocol == 1) { + Xil_Out32(0xFD405910, 0xF3); + Xil_Out32(0xFD40593C, 0xF3); + Xil_Out32(0xFD405914, 0xF3); + Xil_Out32(0xFD405940, 0xF3); + } + if (lane2_protocol == 2 || lane2_protocol == 1) { + Xil_Out32(0xFD409910, 0xF3); + Xil_Out32(0xFD40993C, 0xF3); + Xil_Out32(0xFD409914, 0xF3); + Xil_Out32(0xFD409940, 0xF3); + } + if (lane3_protocol == 2 || lane3_protocol == 1) { + Xil_Out32(0xFD40D910, 0xF3); + Xil_Out32(0xFD40D93C, 0xF3); + Xil_Out32(0xFD40D914, 0xF3); + Xil_Out32(0xFD40D940, 0xF3); + }
- if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); - if (lane0_active == 1) - currbistresult[0] = 0; - if (lane1_active == 1) - currbistresult[1] = 0; - if (lane2_active == 1) - currbistresult[2] = 0; - if (lane3_active == 1) - currbistresult[3] = 0; - serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol, - lane2_rate, lane1_protocol, lane1_rate, - lane0_protocol, lane0_rate); - if (lane3_active == 1) - serdes_bist_run(3); - if (lane2_active == 1) - serdes_bist_run(2); - if (lane1_active == 1) - serdes_bist_run(1); - if (lane0_active == 1) - serdes_bist_run(0); - tempbistresult = 0; - if (lane3_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(3); - tempbistresult = tempbistresult << 1; - if (lane2_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(2); - tempbistresult = tempbistresult << 1; - if (lane1_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(1); - tempbistresult = tempbistresult << 1; - if (lane0_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(0); - Xil_Out32(0xFD410098, 0x0); - Xil_Out32(0xFD410098, 0x2); + if (sata_gen2 == 1) { + if (lane0_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); + Xil_Out32(0xFD402360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); + temp_TM_E_ILL1 = Xil_In32(0xFD401924); + Xil_Out32(0xFD4018F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); + temp_tm_dig_6 = Xil_In32(0xFD40106C); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD401990) & 0xF0;
- if (itercount < 32) { - iterresult[0] = - ((iterresult[0] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[1] = - ((iterresult[1] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[2] = - ((iterresult[2] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[3] = - ((iterresult[3] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } else { - iterresult[4] = - ((iterresult[4] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[5] = - ((iterresult[5] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[6] = - ((iterresult[6] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[7] = - ((iterresult[7] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } - currbistresult[0] = - currbistresult[0] | ((tempbistresult & 0x1) == 1); - currbistresult[1] = - currbistresult[1] | ((tempbistresult & 0x2) == 0x2); - currbistresult[2] = - currbistresult[2] | ((tempbistresult & 0x4) == 0x4); - currbistresult[3] = - currbistresult[3] | ((tempbistresult & 0x8) == 0x8); + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0);
- for (loop = 0; loop <= 3; loop++) { - if (currbistresult[loop] == 1 && prevbistresult[loop] == 1) - bistpasscount[loop] = bistpasscount[loop] + 1; - if (bistpasscount[loop] < 4 && - currbistresult[loop] == 0 && itercount > 2) { - if (meancountalt_bistpasscount[loop] < - bistpasscount[loop]) { - meancountalt_bistpasscount[loop] = - bistpasscount[loop]; - meancountalt[loop] = - ((itercount - 1) - - ((bistpasscount[loop] + 1) / 2)); - } - bistpasscount[loop] = 0; - } - if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && - (currbistresult[loop] == 0 || itercount == 63) && - prevbistresult[loop] == 1) - meancount[loop] = - (itercount - 1) - - ((bistpasscount[loop] + 1) / 2); - prevbistresult[loop] = currbistresult[loop]; + Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40106C, temp_tm_dig_6); + Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); + Xil_Out32(0xFD401990, temp_ill12); + Xil_Out32(0xFD401924, temp_TM_E_ILL1); } - } while (++itercount < 64); + if (lane1_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); + Xil_Out32(0xFD406360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); + temp_TM_E_ILL1 = Xil_In32(0xFD405924); + Xil_Out32(0xFD4058F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); + temp_tm_dig_6 = Xil_In32(0xFD40506C); + psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD405990) & 0xF0;
- for (loop = 0; loop <= 3; loop++) { - if (lane0_active == 0 && loop == 0) - continue; - if (lane1_active == 0 && loop == 1) - continue; - if (lane2_active == 0 && loop == 2) - continue; - if (lane3_active == 0 && loop == 3) - continue; + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0);
- if (meancount[loop] == 0) - meancount[loop] = meancountalt[loop]; + Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40506C, temp_tm_dig_6); + Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); + Xil_Out32(0xFD405990, temp_ill12); + Xil_Out32(0xFD405924, temp_TM_E_ILL1); + } + if (lane2_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); + Xil_Out32(0xFD40A360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); + psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); + temp_TM_E_ILL1 = Xil_In32(0xFD409924); + Xil_Out32(0xFD4098F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); + temp_tm_dig_6 = Xil_In32(0xFD40906C); + psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD409990) & 0xF0;
- if (gen2_calib != 1) { - ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x04 + meancount[loop] * 8) >= - 0x100) ? 0x10 : 0x00; - Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]); - Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]); - Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]); - Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]); + serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0); + + Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40906C, temp_tm_dig_6); + Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); + Xil_Out32(0xFD409990, temp_ill12); + Xil_Out32(0xFD409924, temp_TM_E_ILL1); } - if (gen2_calib == 1) { - ill1_val[loop] = - ((0x104 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x104 + meancount[loop] * 8) >= - 0x200) ? 0x02 : 0x01; - Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]); - Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]); - Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]); - Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]); + if (lane3_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); + Xil_Out32(0xFD40E360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); + temp_TM_E_ILL1 = Xil_In32(0xFD40D924); + Xil_Out32(0xFD40D8F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); + temp_tm_dig_6 = Xil_In32(0xFD40D06C); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; + + serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0); + + Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40D06C, temp_tm_dig_6); + Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); + Xil_Out32(0xFD40D990, temp_ill12); + Xil_Out32(0xFD40D924, temp_TM_E_ILL1); } + rdata = Xil_In32(0xFD410098); + rdata = (rdata & 0xDF); + Xil_Out32(0xFD410098, rdata); } - if (gen2_calib != 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + + if (lane0_protocol == 2 && lane0_rate == 3) { + psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); } - if (gen2_calib == 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); + if (lane1_protocol == 2 && lane1_rate == 3) { + psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); + } + if (lane2_protocol == 2 && lane2_rate == 3) { + psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); + } + if (lane3_protocol == 2 && lane3_rate == 3) { + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); + } + + if (lane0_protocol == 1) { + if (lane0_rate == 0) { + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + } else { + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate, + 1); + } }
- if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); + if (lane0_protocol == 3) + Xil_Out32(0xFD401914, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401940, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401990, 0x20); + if (lane0_protocol == 3) + Xil_Out32(0xFD401924, 0x37); + + if (lane1_protocol == 3) + Xil_Out32(0xFD405914, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405940, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405990, 0x20); + if (lane1_protocol == 3) + Xil_Out32(0xFD405924, 0x37); + + if (lane2_protocol == 3) + Xil_Out32(0xFD409914, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409940, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409990, 0x20); + if (lane2_protocol == 3) + Xil_Out32(0xFD409924, 0x37); + + if (lane3_protocol == 3) + Xil_Out32(0xFD40D914, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D940, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D990, 0x20); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D924, 0x37); + + return 1; +} + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
- Xil_Out32(0xFD410098, 0); - if (lane0_active == 1) { - Xil_Out32(0xFD403004, 0); - Xil_Out32(0xFD403008, 0); - Xil_Out32(0xFD40300C, 0); - Xil_Out32(0xFD403010, 0); - Xil_Out32(0xFD403014, 0); - Xil_Out32(0xFD403018, 0); - Xil_Out32(0xFD40301C, 0); - Xil_Out32(0xFD403020, 0); - Xil_Out32(0xFD403024, 0); - Xil_Out32(0xFD403028, 0); - Xil_Out32(0xFD40302C, 0); - Xil_Out32(0xFD403030, 0); - Xil_Out32(0xFD403034, 0); - Xil_Out32(0xFD403038, 0); - Xil_Out32(0xFD40303C, 0); - Xil_Out32(0xFD403040, 0); - Xil_Out32(0xFD403044, 0); - Xil_Out32(0xFD403048, 0); - Xil_Out32(0xFD40304C, 0); - Xil_Out32(0xFD403050, 0); - Xil_Out32(0xFD403054, 0); - Xil_Out32(0xFD403058, 0); - Xil_Out32(0xFD403068, 1); - Xil_Out32(0xFD40306C, 0); - Xil_Out32(0xFD4010AC, 0); - psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); - } - if (lane1_active == 1) { - Xil_Out32(0xFD407004, 0); - Xil_Out32(0xFD407008, 0); - Xil_Out32(0xFD40700C, 0); - Xil_Out32(0xFD407010, 0); - Xil_Out32(0xFD407014, 0); - Xil_Out32(0xFD407018, 0); - Xil_Out32(0xFD40701C, 0); - Xil_Out32(0xFD407020, 0); - Xil_Out32(0xFD407024, 0); - Xil_Out32(0xFD407028, 0); - Xil_Out32(0xFD40702C, 0); - Xil_Out32(0xFD407030, 0); - Xil_Out32(0xFD407034, 0); - Xil_Out32(0xFD407038, 0); - Xil_Out32(0xFD40703C, 0); - Xil_Out32(0xFD407040, 0); - Xil_Out32(0xFD407044, 0); - Xil_Out32(0xFD407048, 0); - Xil_Out32(0xFD40704C, 0); - Xil_Out32(0xFD407050, 0); - Xil_Out32(0xFD407054, 0); - Xil_Out32(0xFD407058, 0); - Xil_Out32(0xFD407068, 1); - Xil_Out32(0xFD40706C, 0); - Xil_Out32(0xFD4050AC, 0); - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); - } - if (lane2_active == 1) { - Xil_Out32(0xFD40B004, 0); - Xil_Out32(0xFD40B008, 0); - Xil_Out32(0xFD40B00C, 0); - Xil_Out32(0xFD40B010, 0); - Xil_Out32(0xFD40B014, 0); - Xil_Out32(0xFD40B018, 0); - Xil_Out32(0xFD40B01C, 0); - Xil_Out32(0xFD40B020, 0); - Xil_Out32(0xFD40B024, 0); - Xil_Out32(0xFD40B028, 0); - Xil_Out32(0xFD40B02C, 0); - Xil_Out32(0xFD40B030, 0); - Xil_Out32(0xFD40B034, 0); - Xil_Out32(0xFD40B038, 0); - Xil_Out32(0xFD40B03C, 0); - Xil_Out32(0xFD40B040, 0); - Xil_Out32(0xFD40B044, 0); - Xil_Out32(0xFD40B048, 0); - Xil_Out32(0xFD40B04C, 0); - Xil_Out32(0xFD40B050, 0); - Xil_Out32(0xFD40B054, 0); - Xil_Out32(0xFD40B058, 0); - Xil_Out32(0xFD40B068, 1); - Xil_Out32(0xFD40B06C, 0); - Xil_Out32(0xFD4090AC, 0); - psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); - } - if (lane3_active == 1) { - Xil_Out32(0xFD40F004, 0); - Xil_Out32(0xFD40F008, 0); - Xil_Out32(0xFD40F00C, 0); - Xil_Out32(0xFD40F010, 0); - Xil_Out32(0xFD40F014, 0); - Xil_Out32(0xFD40F018, 0); - Xil_Out32(0xFD40F01C, 0); - Xil_Out32(0xFD40F020, 0); - Xil_Out32(0xFD40F024, 0); - Xil_Out32(0xFD40F028, 0); - Xil_Out32(0xFD40F02C, 0); - Xil_Out32(0xFD40F030, 0); - Xil_Out32(0xFD40F034, 0); - Xil_Out32(0xFD40F038, 0); - Xil_Out32(0xFD40F03C, 0); - Xil_Out32(0xFD40F040, 0); - Xil_Out32(0xFD40F044, 0); - Xil_Out32(0xFD40F048, 0); - Xil_Out32(0xFD40F04C, 0); - Xil_Out32(0xFD40F050, 0); - Xil_Out32(0xFD40F054, 0); - Xil_Out32(0xFD40F058, 0); - Xil_Out32(0xFD40F068, 1); - Xil_Out32(0xFD40F06C, 0); - Xil_Out32(0xFD40D0AC, 0); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); - } return 1; }
-static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static unsigned long psu_peripherals_pre_init_data(void) { - unsigned int rdata = 0; - unsigned int sata_gen2 = 1; - unsigned int temp_ill12 = 0; - unsigned int temp_PLL_REF_SEL_OFFSET; - unsigned int temp_TM_IQ_ILL1; - unsigned int temp_TM_E_ILL1; - unsigned int temp_tx_dig_tm_61; - unsigned int temp_tm_dig_6; - unsigned int temp_pll_fbdiv_frac_3_msb_offset; + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
- if (lane0_protocol == 2 || lane0_protocol == 1) { - Xil_Out32(0xFD401910, 0xF3); - Xil_Out32(0xFD40193C, 0xF3); - Xil_Out32(0xFD401914, 0xF3); - Xil_Out32(0xFD401940, 0xF3); - } - if (lane1_protocol == 2 || lane1_protocol == 1) { - Xil_Out32(0xFD405910, 0xF3); - Xil_Out32(0xFD40593C, 0xF3); - Xil_Out32(0xFD405914, 0xF3); - Xil_Out32(0xFD405940, 0xF3); - } - if (lane2_protocol == 2 || lane2_protocol == 1) { - Xil_Out32(0xFD409910, 0xF3); - Xil_Out32(0xFD40993C, 0xF3); - Xil_Out32(0xFD409914, 0xF3); - Xil_Out32(0xFD409940, 0xF3); - } - if (lane3_protocol == 2 || lane3_protocol == 1) { - Xil_Out32(0xFD40D910, 0xF3); - Xil_Out32(0xFD40D93C, 0xF3); - Xil_Out32(0xFD40D914, 0xF3); - Xil_Out32(0xFD40D940, 0xF3); - } + return 1; +}
- if (sata_gen2 == 1) { - if (lane0_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); - Xil_Out32(0xFD402360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); - psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); - temp_TM_E_ILL1 = Xil_In32(0xFD401924); - Xil_Out32(0xFD4018F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); - temp_tm_dig_6 = Xil_In32(0xFD40106C); - psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD401990) & 0xF0; +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + + serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); + psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
- serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0); + return 1; +}
- Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40106C, temp_tm_dig_6); - Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); - Xil_Out32(0xFD401990, temp_ill12); - Xil_Out32(0xFD401924, temp_TM_E_ILL1); - } - if (lane1_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); - Xil_Out32(0xFD406360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); - psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); - temp_TM_E_ILL1 = Xil_In32(0xFD405924); - Xil_Out32(0xFD4058F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); - temp_tm_dig_6 = Xil_In32(0xFD40506C); - psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD405990) & 0xF0; +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
- serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0); + return 1; +}
- Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40506C, temp_tm_dig_6); - Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); - Xil_Out32(0xFD405990, temp_ill12); - Xil_Out32(0xFD405924, temp_TM_E_ILL1); - } - if (lane2_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); - Xil_Out32(0xFD40A360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); - psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); - temp_TM_E_ILL1 = Xil_In32(0xFD409924); - Xil_Out32(0xFD4098F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); - temp_tm_dig_6 = Xil_In32(0xFD40906C); - psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD409990) & 0xF0; +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); + psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
- serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0); + return 1; +}
- Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40906C, temp_tm_dig_6); - Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); - Xil_Out32(0xFD409990, temp_ill12); - Xil_Out32(0xFD409924, temp_TM_E_ILL1); - } - if (lane3_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); - Xil_Out32(0xFD40E360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); - psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); - temp_TM_E_ILL1 = Xil_In32(0xFD40D924); - Xil_Out32(0xFD40D8F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); - temp_tm_dig_6 = Xil_In32(0xFD40D06C); - psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + int cur_R006_tREFPRD;
- serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0); + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011);
- Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40D06C, temp_tm_dig_6); - Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); - Xil_Out32(0xFD40D990, temp_ill12); - Xil_Out32(0xFD40D924, temp_TM_E_ILL1); - } - rdata = Xil_In32(0xFD410098); - rdata = (rdata & 0xDF); - Xil_Out32(0xFD410098, rdata); + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0;
- if (lane0_protocol == 2 && lane0_rate == 3) { - psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); - } - if (lane1_protocol == 2 && lane1_rate == 3) { - psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); - } - if (lane2_protocol == 2 && lane2_rate == 3) { - psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); - } - if (lane3_protocol == 2 && lane3_rate == 3) { - psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); - } + Xil_Out32(0xFD080004U, 0x00040063U);
- if (lane0_protocol == 1) { - if (lane0_rate == 0) { - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - } else { - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, lane0_rate, - 1); - } - } + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
- if (lane0_protocol == 3) - Xil_Out32(0xFD401914, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401940, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401990, 0x20); - if (lane0_protocol == 3) - Xil_Out32(0xFD401924, 0x37); + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0;
- if (lane1_protocol == 3) - Xil_Out32(0xFD405914, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405940, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405990, 0x20); - if (lane1_protocol == 3) - Xil_Out32(0xFD405924, 0x37); + Xil_Out32(0xFD080200U, 0x100091C7U);
- if (lane2_protocol == 3) - Xil_Out32(0xFD409914, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409940, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409990, 0x20); - if (lane2_protocol == 3) - Xil_Out32(0xFD409924, 0x37); + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
- if (lane3_protocol == 3) - Xil_Out32(0xFD40D914, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D940, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D990, 0x20); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D924, 0x37); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
return 1; } diff --git a/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c index bd316872eb..5d47cd1abc 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c @@ -6,1692 +6,1687 @@ #include <asm/arch/psu_init_gpl.h> #include <xil_io.h>
-static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate); - -static unsigned long psu_pll_init_data(void) +static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) { - psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000002U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); - psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000002U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); - psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000004U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + Xil_Out32(0xFD410098, 0x00000000); + Xil_Out32(0xFD401010, 0x00000040); + Xil_Out32(0xFD405010, 0x00000040); + Xil_Out32(0xFD409010, 0x00000040); + Xil_Out32(0xFD40D010, 0x00000040); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + Xil_Out32(0xFD410098, 0x00000004); + mask_delay(50); + if (lane0_rate == 1) + Xil_Out32(0xFD410098, 0x0000000E); + Xil_Out32(0xFD410098, 0x00000006); + if (lane0_rate == 1) { + Xil_Out32(0xFD40000C, 0x00000004); + Xil_Out32(0xFD40400C, 0x00000004); + Xil_Out32(0xFD40800C, 0x00000004); + Xil_Out32(0xFD40C00C, 0x00000004); + Xil_Out32(0xFD410098, 0x00000007); + mask_delay(400); + Xil_Out32(0xFD40000C, 0x0000000C); + Xil_Out32(0xFD40400C, 0x0000000C); + Xil_Out32(0xFD40800C, 0x0000000C); + Xil_Out32(0xFD40C00C, 0x0000000C); + mask_delay(15); + Xil_Out32(0xFD410098, 0x0000000F); + mask_delay(100); + } + if (lane0_protocol != 0) + mask_poll(0xFD4023E4, 0x00000010U); + if (lane1_protocol != 0) + mask_poll(0xFD4063E4, 0x00000010U); + if (lane2_protocol != 0) + mask_poll(0xFD40A3E4, 0x00000010U); + if (lane3_protocol != 0) + mask_poll(0xFD40E3E4, 0x00000010U); + mask_delay(50); + Xil_Out32(0xFD401010, 0x000000C0); + Xil_Out32(0xFD405010, 0x000000C0); + Xil_Out32(0xFD409010, 0x000000C0); + Xil_Out32(0xFD40D010, 0x000000C0); + Xil_Out32(0xFD401010, 0x00000080); + Xil_Out32(0xFD405010, 0x00000080); + Xil_Out32(0xFD409010, 0x00000080); + Xil_Out32(0xFD40D010, 0x00000080);
+ Xil_Out32(0xFD402084, 0x000000C0); + Xil_Out32(0xFD406084, 0x000000C0); + Xil_Out32(0xFD40A084, 0x000000C0); + Xil_Out32(0xFD40E084, 0x000000C0); + mask_delay(50); + Xil_Out32(0xFD402084, 0x00000080); + Xil_Out32(0xFD406084, 0x00000080); + Xil_Out32(0xFD40A084, 0x00000080); + Xil_Out32(0xFD40E084, 0x00000080); + mask_delay(50); + Xil_Out32(0xFD401010, 0x00000000); + Xil_Out32(0xFD405010, 0x00000000); + Xil_Out32(0xFD409010, 0x00000000); + Xil_Out32(0xFD40D010, 0x00000000); + Xil_Out32(0xFD402084, 0x00000000); + Xil_Out32(0xFD406084, 0x00000000); + Xil_Out32(0xFD40A084, 0x00000000); + Xil_Out32(0xFD40E084, 0x00000000); + mask_delay(500); return 1; }
-static unsigned long psu_clock_init_data(void) +static int serdes_bist_static_settings(u32 lane_active) { - psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); - psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); - psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); - psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); - psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); - psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); - psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); - psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); - psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); - psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); - psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); - psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); - psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); - psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); - psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); - psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + if (lane_active == 0) { + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + Xil_Out32(0xFD403068, 0x1); + Xil_Out32(0xFD40306C, 0x1); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403008, 0x0); + Xil_Out32(0xFD40300C, 0xF4); + Xil_Out32(0xFD403010, 0x0); + Xil_Out32(0xFD403014, 0x0); + Xil_Out32(0xFD403018, 0x00); + Xil_Out32(0xFD40301C, 0xFB); + Xil_Out32(0xFD403020, 0xFF); + Xil_Out32(0xFD403024, 0x0); + Xil_Out32(0xFD403028, 0x00); + Xil_Out32(0xFD40302C, 0x00); + Xil_Out32(0xFD403030, 0x4A); + Xil_Out32(0xFD403034, 0x4A); + Xil_Out32(0xFD403038, 0x4A); + Xil_Out32(0xFD40303C, 0x4A); + Xil_Out32(0xFD403040, 0x0); + Xil_Out32(0xFD403044, 0x14); + Xil_Out32(0xFD403048, 0x02); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); + } + if (lane_active == 1) { + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + Xil_Out32(0xFD407068, 0x1); + Xil_Out32(0xFD40706C, 0x1); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407008, 0x0); + Xil_Out32(0xFD40700C, 0xF4); + Xil_Out32(0xFD407010, 0x0); + Xil_Out32(0xFD407014, 0x0); + Xil_Out32(0xFD407018, 0x00); + Xil_Out32(0xFD40701C, 0xFB); + Xil_Out32(0xFD407020, 0xFF); + Xil_Out32(0xFD407024, 0x0); + Xil_Out32(0xFD407028, 0x00); + Xil_Out32(0xFD40702C, 0x00); + Xil_Out32(0xFD407030, 0x4A); + Xil_Out32(0xFD407034, 0x4A); + Xil_Out32(0xFD407038, 0x4A); + Xil_Out32(0xFD40703C, 0x4A); + Xil_Out32(0xFD407040, 0x0); + Xil_Out32(0xFD407044, 0x14); + Xil_Out32(0xFD407048, 0x02); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); + } + + if (lane_active == 2) { + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40B068, 0x1); + Xil_Out32(0xFD40B06C, 0x1); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B008, 0x0); + Xil_Out32(0xFD40B00C, 0xF4); + Xil_Out32(0xFD40B010, 0x0); + Xil_Out32(0xFD40B014, 0x0); + Xil_Out32(0xFD40B018, 0x00); + Xil_Out32(0xFD40B01C, 0xFB); + Xil_Out32(0xFD40B020, 0xFF); + Xil_Out32(0xFD40B024, 0x0); + Xil_Out32(0xFD40B028, 0x00); + Xil_Out32(0xFD40B02C, 0x00); + Xil_Out32(0xFD40B030, 0x4A); + Xil_Out32(0xFD40B034, 0x4A); + Xil_Out32(0xFD40B038, 0x4A); + Xil_Out32(0xFD40B03C, 0x4A); + Xil_Out32(0xFD40B040, 0x0); + Xil_Out32(0xFD40B044, 0x14); + Xil_Out32(0xFD40B048, 0x02); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); + }
+ if (lane_active == 3) { + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + Xil_Out32(0xFD40F068, 0x1); + Xil_Out32(0xFD40F06C, 0x1); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F008, 0x0); + Xil_Out32(0xFD40F00C, 0xF4); + Xil_Out32(0xFD40F010, 0x0); + Xil_Out32(0xFD40F014, 0x0); + Xil_Out32(0xFD40F018, 0x00); + Xil_Out32(0xFD40F01C, 0xFB); + Xil_Out32(0xFD40F020, 0xFF); + Xil_Out32(0xFD40F024, 0x0); + Xil_Out32(0xFD40F028, 0x00); + Xil_Out32(0xFD40F02C, 0x00); + Xil_Out32(0xFD40F030, 0x4A); + Xil_Out32(0xFD40F034, 0x4A); + Xil_Out32(0xFD40F038, 0x4A); + Xil_Out32(0xFD40F03C, 0x4A); + Xil_Out32(0xFD40F040, 0x0); + Xil_Out32(0xFD40F044, 0x14); + Xil_Out32(0xFD40F048, 0x02); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); + } return 1; }
-static unsigned long psu_ddr_init_data(void) +static int serdes_bist_run(u32 lane_active) { - psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); - psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); - psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); - psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); - psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); - psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U); - psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); - psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); - psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); - psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U); - psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); - psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); - psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); - psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U); - psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); - psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U); - psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); - psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U); - psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); - psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); - psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); - psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); - psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); - psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U); - psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); - psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU); - psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); - psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); - psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); - psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); - psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); - psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); - psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U); - psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); - psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); - psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); - psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU); - psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U); - psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); - psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); - psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); - psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); - psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); - psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); - psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); - psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); - psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); - psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); - psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); - psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); - psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); - psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); - psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); - psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU); - psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); - psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); - psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); - psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); - psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); - psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); - psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); - psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); - psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); - psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); - psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); - psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); - psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); - psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U); - psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); - psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); - psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U); - psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U); - psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); - psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); - psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); - psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U); - psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); - psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); - psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); - psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U); - psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U); - psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU); - psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); - psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); - psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); - psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); - psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); - psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U); - psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); - psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); - psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); - psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); - psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); - psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); - psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); - psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); - psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); - psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); - psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); - psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); - psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); - psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); - psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); - psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); - psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); - psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); - psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); - psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U); - psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); - psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); - psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); - psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); - psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); - psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); - psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); - psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); - psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); - - return 1; -} - -static unsigned long psu_ddr_qos_init_data(void) -{ - psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); - psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); - - return 1; -} - -static unsigned long psu_mio_init_data(void) -{ - psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U); - psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); - psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); - psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); - - return 1; -} - -static unsigned long psu_peripherals_pre_init_data(void) -{ - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); - psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); - - return 1; -} - -static unsigned long psu_peripherals_init_data(void) -{ - psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); - psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); - psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); - psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); - psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); - psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); - - mask_delay(1); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); - - mask_delay(5); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); - - return 1; -} - -static unsigned long psu_serdes_init_data(void) -{ - psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); - psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); - psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); - psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); - psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); - psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); - psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); - psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); - psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); - psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); - psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); - psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); - psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); - psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); - psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); - psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); - psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); - psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); - psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); - psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); - psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); - psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); - psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); - psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); - psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); - psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); - - serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0); - psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); - psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); - psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); - psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); - psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); - psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); - - return 1; -} - -static unsigned long psu_resetout_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); - psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); - psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); - psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); - psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); - psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); - psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); - mask_poll(0xFD40A3E4, 0x00000010U); - mask_poll(0xFD40E3E4, 0x00000010U); - psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); - psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); - psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); - psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); - - return 1; -} - -static unsigned long psu_resetin_init_data(void) -{ - psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); - - return 1; -} - -static unsigned long psu_afi_config(void) -{ - psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); - psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); - psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U); - psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U); - - return 1; -} - -static unsigned long psu_ddr_phybringup_data(void) -{ - unsigned int regval = 0; - unsigned int pll_retry = 10; - unsigned int pll_locked = 0; - int cur_R006_tREFPRD; - - while ((pll_retry > 0) && (!pll_locked)) { - Xil_Out32(0xFD080004, 0x00040010); - Xil_Out32(0xFD080004, 0x00040011); - - while ((Xil_In32(0xFD080030) & 0x1) != 1) - ; - pll_locked = (Xil_In32(0xFD080030) & 0x80000000) - >> 31; - pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; - pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) - >> 16; - pll_retry--; + if (lane_active == 0) { + psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4010AC, 0x0020); + Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); } - Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); - if (!pll_locked) - return 0; - - Xil_Out32(0xFD080004U, 0x00040063U); - - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) - ; - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) - ; - Xil_Out32(0xFD0701B0U, 0x00000001U); - Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) - ; - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0004FE01); - regval = Xil_In32(0xFD080030); - while (regval != 0x80000FFF) - regval = Xil_In32(0xFD080030); - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - - Xil_Out32(0xFD080200U, 0x100091C7U); - - cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; - prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - - prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); - prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); - - Xil_Out32(0xFD080004, 0x00060001); - regval = Xil_In32(0xFD080030); - while ((regval & 0x80004001) != 0x80004001) - regval = Xil_In32(0xFD080030); - - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - - prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); - prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); - - Xil_Out32(0xFD080200U, 0x800091C7U); - prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - - Xil_Out32(0xFD080004, 0x0000C001); - regval = Xil_In32(0xFD080030); - while ((regval & 0x80000C01) != 0x80000C01) - regval = Xil_In32(0xFD080030); + if (lane_active == 1) { + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD4050AC, 0x0020); + Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); + } + if (lane_active == 2) { + psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); + Xil_Out32(0xFD4090AC, 0x0020); + Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + } + if (lane_active == 3) { + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); + Xil_Out32(0xFD40D0AC, 0x0020); + Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + } + mask_delay(100); + return 1; +}
- Xil_Out32(0xFD070180U, 0x01000040U); - Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); +static int serdes_bist_result(u32 lane_active) +{ + u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0;
+ if (lane_active == 0) { + pkt_cnt_l0 = Xil_In32(0xFD40304C); + pkt_cnt_h0 = Xil_In32(0xFD403050); + err_cnt_l0 = Xil_In32(0xFD403054); + err_cnt_h0 = Xil_In32(0xFD403058); + } + if (lane_active == 1) { + pkt_cnt_l0 = Xil_In32(0xFD40704C); + pkt_cnt_h0 = Xil_In32(0xFD407050); + err_cnt_l0 = Xil_In32(0xFD407054); + err_cnt_h0 = Xil_In32(0xFD407058); + } + if (lane_active == 2) { + pkt_cnt_l0 = Xil_In32(0xFD40B04C); + pkt_cnt_h0 = Xil_In32(0xFD40B050); + err_cnt_l0 = Xil_In32(0xFD40B054); + err_cnt_h0 = Xil_In32(0xFD40B058); + } + if (lane_active == 3) { + pkt_cnt_l0 = Xil_In32(0xFD40F04C); + pkt_cnt_h0 = Xil_In32(0xFD40F050); + err_cnt_l0 = Xil_In32(0xFD40F054); + err_cnt_h0 = Xil_In32(0xFD40F058); + } + if (lane_active == 0) + Xil_Out32(0xFD403004, 0x0); + if (lane_active == 1) + Xil_Out32(0xFD407004, 0x0); + if (lane_active == 2) + Xil_Out32(0xFD40B004, 0x0); + if (lane_active == 3) + Xil_Out32(0xFD40F004, 0x0); + if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || + (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) + return 0; return 1; }
-static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate, + u32 gen2_calib) { - Xil_Out32(0xFD410098, 0x00000000); - Xil_Out32(0xFD401010, 0x00000040); - Xil_Out32(0xFD405010, 0x00000040); - Xil_Out32(0xFD409010, 0x00000040); - Xil_Out32(0xFD40D010, 0x00000040); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - Xil_Out32(0xFD410098, 0x00000004); - mask_delay(50); - if (lane0_rate == 1) - Xil_Out32(0xFD410098, 0x0000000E); - Xil_Out32(0xFD410098, 0x00000006); - if (lane0_rate == 1) { - Xil_Out32(0xFD40000C, 0x00000004); - Xil_Out32(0xFD40400C, 0x00000004); - Xil_Out32(0xFD40800C, 0x00000004); - Xil_Out32(0xFD40C00C, 0x00000004); - Xil_Out32(0xFD410098, 0x00000007); - mask_delay(400); - Xil_Out32(0xFD40000C, 0x0000000C); - Xil_Out32(0xFD40400C, 0x0000000C); - Xil_Out32(0xFD40800C, 0x0000000C); - Xil_Out32(0xFD40C00C, 0x0000000C); - mask_delay(15); - Xil_Out32(0xFD410098, 0x0000000F); - mask_delay(100); + u64 tempbistresult; + u32 currbistresult[4]; + u32 prevbistresult[4]; + u32 itercount = 0; + u32 ill12_val[4], ill1_val[4]; + u32 loop = 0; + u32 iterresult[8]; + u32 meancount[4]; + u32 bistpasscount[4]; + u32 meancountalt[4]; + u32 meancountalt_bistpasscount[4]; + u32 lane0_active; + u32 lane1_active; + u32 lane2_active; + u32 lane3_active; + + lane0_active = (lane0_protocol == 1); + lane1_active = (lane1_protocol == 1); + lane2_active = (lane2_protocol == 1); + lane3_active = (lane3_protocol == 1); + for (loop = 0; loop <= 3; loop++) { + iterresult[loop] = 0; + iterresult[loop + 4] = 0; + meancountalt[loop] = 0; + meancountalt_bistpasscount[loop] = 0; + meancount[loop] = 0; + prevbistresult[loop] = 0; + bistpasscount[loop] = 0; } - if (lane0_protocol != 0) - mask_poll(0xFD4023E4, 0x00000010U); - if (lane1_protocol != 0) - mask_poll(0xFD4063E4, 0x00000010U); - if (lane2_protocol != 0) - mask_poll(0xFD40A3E4, 0x00000010U); - if (lane3_protocol != 0) - mask_poll(0xFD40E3E4, 0x00000010U); - mask_delay(50); - Xil_Out32(0xFD401010, 0x000000C0); - Xil_Out32(0xFD405010, 0x000000C0); - Xil_Out32(0xFD409010, 0x000000C0); - Xil_Out32(0xFD40D010, 0x000000C0); - Xil_Out32(0xFD401010, 0x00000080); - Xil_Out32(0xFD405010, 0x00000080); - Xil_Out32(0xFD409010, 0x00000080); - Xil_Out32(0xFD40D010, 0x00000080); + itercount = 0; + if (lane0_active) + serdes_bist_static_settings(0); + if (lane1_active) + serdes_bist_static_settings(1); + if (lane2_active) + serdes_bist_static_settings(2); + if (lane3_active) + serdes_bist_static_settings(3); + do { + if (gen2_calib != 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x04 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane1_active == 1) + ill1_val[1] = ((0x04 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane2_active == 1) + ill1_val[2] = ((0x04 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) + ill1_val[3] = ((0x04 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x04 + itercount * 8) >= + 0x100) ? 0x10 : 0x00; + + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, + ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + ill1_val[0] = ((0x104 + itercount * 8) % 0x100); + if (lane0_active == 1) + ill12_val[0] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane1_active == 1) + ill1_val[1] = ((0x104 + itercount * 8) % 0x100); + if (lane1_active == 1) + ill12_val[1] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane2_active == 1) + ill1_val[2] = ((0x104 + itercount * 8) % 0x100); + if (lane2_active == 1) + ill12_val[2] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + if (lane3_active == 1) + ill1_val[3] = ((0x104 + itercount * 8) % 0x100); + if (lane3_active == 1) + ill12_val[3] = + ((0x104 + itercount * 8) >= + 0x200) ? 0x02 : 0x01; + + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, + ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, + ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, + ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, + ill12_val[3]); + } + + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); + if (lane0_active == 1) + currbistresult[0] = 0; + if (lane1_active == 1) + currbistresult[1] = 0; + if (lane2_active == 1) + currbistresult[2] = 0; + if (lane3_active == 1) + currbistresult[3] = 0; + serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol, + lane2_rate, lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate); + if (lane3_active == 1) + serdes_bist_run(3); + if (lane2_active == 1) + serdes_bist_run(2); + if (lane1_active == 1) + serdes_bist_run(1); + if (lane0_active == 1) + serdes_bist_run(0); + tempbistresult = 0; + if (lane3_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(3); + tempbistresult = tempbistresult << 1; + if (lane2_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(2); + tempbistresult = tempbistresult << 1; + if (lane1_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(1); + tempbistresult = tempbistresult << 1; + if (lane0_active == 1) + tempbistresult = tempbistresult | serdes_bist_result(0); + Xil_Out32(0xFD410098, 0x0); + Xil_Out32(0xFD410098, 0x2);
- Xil_Out32(0xFD402084, 0x000000C0); - Xil_Out32(0xFD406084, 0x000000C0); - Xil_Out32(0xFD40A084, 0x000000C0); - Xil_Out32(0xFD40E084, 0x000000C0); - mask_delay(50); - Xil_Out32(0xFD402084, 0x00000080); - Xil_Out32(0xFD406084, 0x00000080); - Xil_Out32(0xFD40A084, 0x00000080); - Xil_Out32(0xFD40E084, 0x00000080); - mask_delay(50); - Xil_Out32(0xFD401010, 0x00000000); - Xil_Out32(0xFD405010, 0x00000000); - Xil_Out32(0xFD409010, 0x00000000); - Xil_Out32(0xFD40D010, 0x00000000); - Xil_Out32(0xFD402084, 0x00000000); - Xil_Out32(0xFD406084, 0x00000000); - Xil_Out32(0xFD40A084, 0x00000000); - Xil_Out32(0xFD40E084, 0x00000000); - mask_delay(500); - return 1; -} + if (itercount < 32) { + iterresult[0] = + ((iterresult[0] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[1] = + ((iterresult[1] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[2] = + ((iterresult[2] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[3] = + ((iterresult[3] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } else { + iterresult[4] = + ((iterresult[4] << 1) | + ((tempbistresult & 0x1) == 0x1)); + iterresult[5] = + ((iterresult[5] << 1) | + ((tempbistresult & 0x2) == 0x2)); + iterresult[6] = + ((iterresult[6] << 1) | + ((tempbistresult & 0x4) == 0x4)); + iterresult[7] = + ((iterresult[7] << 1) | + ((tempbistresult & 0x8) == 0x8)); + } + currbistresult[0] = + currbistresult[0] | ((tempbistresult & 0x1) == 1); + currbistresult[1] = + currbistresult[1] | ((tempbistresult & 0x2) == 0x2); + currbistresult[2] = + currbistresult[2] | ((tempbistresult & 0x4) == 0x4); + currbistresult[3] = + currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
-static int serdes_bist_static_settings(u32 lane_active) -{ - if (lane_active == 0) { - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - Xil_Out32(0xFD403068, 0x1); - Xil_Out32(0xFD40306C, 0x1); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403008, 0x0); - Xil_Out32(0xFD40300C, 0xF4); - Xil_Out32(0xFD403010, 0x0); - Xil_Out32(0xFD403014, 0x0); - Xil_Out32(0xFD403018, 0x00); - Xil_Out32(0xFD40301C, 0xFB); - Xil_Out32(0xFD403020, 0xFF); - Xil_Out32(0xFD403024, 0x0); - Xil_Out32(0xFD403028, 0x00); - Xil_Out32(0xFD40302C, 0x00); - Xil_Out32(0xFD403030, 0x4A); - Xil_Out32(0xFD403034, 0x4A); - Xil_Out32(0xFD403038, 0x4A); - Xil_Out32(0xFD40303C, 0x4A); - Xil_Out32(0xFD403040, 0x0); - Xil_Out32(0xFD403044, 0x14); - Xil_Out32(0xFD403048, 0x02); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); - } - if (lane_active == 1) { - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - Xil_Out32(0xFD407068, 0x1); - Xil_Out32(0xFD40706C, 0x1); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407008, 0x0); - Xil_Out32(0xFD40700C, 0xF4); - Xil_Out32(0xFD407010, 0x0); - Xil_Out32(0xFD407014, 0x0); - Xil_Out32(0xFD407018, 0x00); - Xil_Out32(0xFD40701C, 0xFB); - Xil_Out32(0xFD407020, 0xFF); - Xil_Out32(0xFD407024, 0x0); - Xil_Out32(0xFD407028, 0x00); - Xil_Out32(0xFD40702C, 0x00); - Xil_Out32(0xFD407030, 0x4A); - Xil_Out32(0xFD407034, 0x4A); - Xil_Out32(0xFD407038, 0x4A); - Xil_Out32(0xFD40703C, 0x4A); - Xil_Out32(0xFD407040, 0x0); - Xil_Out32(0xFD407044, 0x14); - Xil_Out32(0xFD407048, 0x02); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); - } + for (loop = 0; loop <= 3; loop++) { + if (currbistresult[loop] == 1 && prevbistresult[loop] == 1) + bistpasscount[loop] = bistpasscount[loop] + 1; + if (bistpasscount[loop] < 4 && currbistresult[loop] == 0 && + itercount > 2) { + if (meancountalt_bistpasscount[loop] < + bistpasscount[loop]) { + meancountalt_bistpasscount[loop] = + bistpasscount[loop]; + meancountalt[loop] = + ((itercount - 1) - + ((bistpasscount[loop] + 1) / 2)); + } + bistpasscount[loop] = 0; + } + if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && + (currbistresult[loop] == 0 || itercount == 63) && + prevbistresult[loop] == 1) + meancount[loop] = + (itercount - 1) - + ((bistpasscount[loop] + 1) / 2); + prevbistresult[loop] = currbistresult[loop]; + } + } while (++itercount < 64);
- if (lane_active == 2) { - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40B068, 0x1); - Xil_Out32(0xFD40B06C, 0x1); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B008, 0x0); - Xil_Out32(0xFD40B00C, 0xF4); - Xil_Out32(0xFD40B010, 0x0); - Xil_Out32(0xFD40B014, 0x0); - Xil_Out32(0xFD40B018, 0x00); - Xil_Out32(0xFD40B01C, 0xFB); - Xil_Out32(0xFD40B020, 0xFF); - Xil_Out32(0xFD40B024, 0x0); - Xil_Out32(0xFD40B028, 0x00); - Xil_Out32(0xFD40B02C, 0x00); - Xil_Out32(0xFD40B030, 0x4A); - Xil_Out32(0xFD40B034, 0x4A); - Xil_Out32(0xFD40B038, 0x4A); - Xil_Out32(0xFD40B03C, 0x4A); - Xil_Out32(0xFD40B040, 0x0); - Xil_Out32(0xFD40B044, 0x14); - Xil_Out32(0xFD40B048, 0x02); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); - } + for (loop = 0; loop <= 3; loop++) { + if (lane0_active == 0 && loop == 0) + continue; + if (lane1_active == 0 && loop == 1) + continue; + if (lane2_active == 0 && loop == 2) + continue; + if (lane3_active == 0 && loop == 3) + continue;
- if (lane_active == 3) { - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - Xil_Out32(0xFD40F068, 0x1); - Xil_Out32(0xFD40F06C, 0x1); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F008, 0x0); - Xil_Out32(0xFD40F00C, 0xF4); - Xil_Out32(0xFD40F010, 0x0); - Xil_Out32(0xFD40F014, 0x0); - Xil_Out32(0xFD40F018, 0x00); - Xil_Out32(0xFD40F01C, 0xFB); - Xil_Out32(0xFD40F020, 0xFF); - Xil_Out32(0xFD40F024, 0x0); - Xil_Out32(0xFD40F028, 0x00); - Xil_Out32(0xFD40F02C, 0x00); - Xil_Out32(0xFD40F030, 0x4A); - Xil_Out32(0xFD40F034, 0x4A); - Xil_Out32(0xFD40F038, 0x4A); - Xil_Out32(0xFD40F03C, 0x4A); - Xil_Out32(0xFD40F040, 0x0); - Xil_Out32(0xFD40F044, 0x14); - Xil_Out32(0xFD40F048, 0x02); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); - } - return 1; -} + if (meancount[loop] == 0) + meancount[loop] = meancountalt[loop];
-static int serdes_bist_run(u32 lane_active) -{ - if (lane_active == 0) { - psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4010AC, 0x0020); - Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); - } - if (lane_active == 1) { - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD4050AC, 0x0020); - Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); - } - if (lane_active == 2) { - psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); - Xil_Out32(0xFD4090AC, 0x0020); - Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); + if (gen2_calib != 1) { + ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x04 + meancount[loop] * 8) >= + 0x100) ? 0x10 : 0x00; + Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]); + Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]); + Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]); + Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]); + } + if (gen2_calib == 1) { + ill1_val[loop] = + ((0x104 + meancount[loop] * 8) % 0x100); + ill12_val[loop] = + ((0x104 + meancount[loop] * 8) >= + 0x200) ? 0x02 : 0x01; + Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]); + Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]); + Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]); + Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]); + } } - if (lane_active == 3) { - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); - Xil_Out32(0xFD40D0AC, 0x0020); - Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); + if (gen2_calib != 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401924, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405924, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409924, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D924, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + } + if (gen2_calib == 1) { + if (lane0_active == 1) + Xil_Out32(0xFD401928, ill1_val[0]); + if (lane0_active == 1) + psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); + if (lane1_active == 1) + Xil_Out32(0xFD405928, ill1_val[1]); + if (lane1_active == 1) + psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); + if (lane2_active == 1) + Xil_Out32(0xFD409928, ill1_val[2]); + if (lane2_active == 1) + psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); + if (lane3_active == 1) + Xil_Out32(0xFD40D928, ill1_val[3]); + if (lane3_active == 1) + psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); } - mask_delay(100); - return 1; -}
-static int serdes_bist_result(u32 lane_active) -{ - u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; + if (lane0_active == 1) + psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); + if (lane1_active == 1) + psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); + if (lane2_active == 1) + psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); + if (lane3_active == 1) + psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
- if (lane_active == 0) { - pkt_cnt_l0 = Xil_In32(0xFD40304C); - pkt_cnt_h0 = Xil_In32(0xFD403050); - err_cnt_l0 = Xil_In32(0xFD403054); - err_cnt_h0 = Xil_In32(0xFD403058); - } - if (lane_active == 1) { - pkt_cnt_l0 = Xil_In32(0xFD40704C); - pkt_cnt_h0 = Xil_In32(0xFD407050); - err_cnt_l0 = Xil_In32(0xFD407054); - err_cnt_h0 = Xil_In32(0xFD407058); - } - if (lane_active == 2) { - pkt_cnt_l0 = Xil_In32(0xFD40B04C); - pkt_cnt_h0 = Xil_In32(0xFD40B050); - err_cnt_l0 = Xil_In32(0xFD40B054); - err_cnt_h0 = Xil_In32(0xFD40B058); + Xil_Out32(0xFD410098, 0); + if (lane0_active == 1) { + Xil_Out32(0xFD403004, 0); + Xil_Out32(0xFD403008, 0); + Xil_Out32(0xFD40300C, 0); + Xil_Out32(0xFD403010, 0); + Xil_Out32(0xFD403014, 0); + Xil_Out32(0xFD403018, 0); + Xil_Out32(0xFD40301C, 0); + Xil_Out32(0xFD403020, 0); + Xil_Out32(0xFD403024, 0); + Xil_Out32(0xFD403028, 0); + Xil_Out32(0xFD40302C, 0); + Xil_Out32(0xFD403030, 0); + Xil_Out32(0xFD403034, 0); + Xil_Out32(0xFD403038, 0); + Xil_Out32(0xFD40303C, 0); + Xil_Out32(0xFD403040, 0); + Xil_Out32(0xFD403044, 0); + Xil_Out32(0xFD403048, 0); + Xil_Out32(0xFD40304C, 0); + Xil_Out32(0xFD403050, 0); + Xil_Out32(0xFD403054, 0); + Xil_Out32(0xFD403058, 0); + Xil_Out32(0xFD403068, 1); + Xil_Out32(0xFD40306C, 0); + Xil_Out32(0xFD4010AC, 0); + psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); } - if (lane_active == 3) { - pkt_cnt_l0 = Xil_In32(0xFD40F04C); - pkt_cnt_h0 = Xil_In32(0xFD40F050); - err_cnt_l0 = Xil_In32(0xFD40F054); - err_cnt_h0 = Xil_In32(0xFD40F058); + if (lane1_active == 1) { + Xil_Out32(0xFD407004, 0); + Xil_Out32(0xFD407008, 0); + Xil_Out32(0xFD40700C, 0); + Xil_Out32(0xFD407010, 0); + Xil_Out32(0xFD407014, 0); + Xil_Out32(0xFD407018, 0); + Xil_Out32(0xFD40701C, 0); + Xil_Out32(0xFD407020, 0); + Xil_Out32(0xFD407024, 0); + Xil_Out32(0xFD407028, 0); + Xil_Out32(0xFD40702C, 0); + Xil_Out32(0xFD407030, 0); + Xil_Out32(0xFD407034, 0); + Xil_Out32(0xFD407038, 0); + Xil_Out32(0xFD40703C, 0); + Xil_Out32(0xFD407040, 0); + Xil_Out32(0xFD407044, 0); + Xil_Out32(0xFD407048, 0); + Xil_Out32(0xFD40704C, 0); + Xil_Out32(0xFD407050, 0); + Xil_Out32(0xFD407054, 0); + Xil_Out32(0xFD407058, 0); + Xil_Out32(0xFD407068, 1); + Xil_Out32(0xFD40706C, 0); + Xil_Out32(0xFD4050AC, 0); + psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); } - if (lane_active == 0) - Xil_Out32(0xFD403004, 0x0); - if (lane_active == 1) - Xil_Out32(0xFD407004, 0x0); - if (lane_active == 2) - Xil_Out32(0xFD40B004, 0x0); - if (lane_active == 3) - Xil_Out32(0xFD40F004, 0x0); - if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || - (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) - return 0; - return 1; -} - -static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate, - u32 gen2_calib) -{ - u64 tempbistresult; - u32 currbistresult[4]; - u32 prevbistresult[4]; - u32 itercount = 0; - u32 ill12_val[4], ill1_val[4]; - u32 loop = 0; - u32 iterresult[8]; - u32 meancount[4]; - u32 bistpasscount[4]; - u32 meancountalt[4]; - u32 meancountalt_bistpasscount[4]; - u32 lane0_active; - u32 lane1_active; - u32 lane2_active; - u32 lane3_active; - - lane0_active = (lane0_protocol == 1); - lane1_active = (lane1_protocol == 1); - lane2_active = (lane2_protocol == 1); - lane3_active = (lane3_protocol == 1); - for (loop = 0; loop <= 3; loop++) { - iterresult[loop] = 0; - iterresult[loop + 4] = 0; - meancountalt[loop] = 0; - meancountalt_bistpasscount[loop] = 0; - meancount[loop] = 0; - prevbistresult[loop] = 0; - bistpasscount[loop] = 0; + if (lane2_active == 1) { + Xil_Out32(0xFD40B004, 0); + Xil_Out32(0xFD40B008, 0); + Xil_Out32(0xFD40B00C, 0); + Xil_Out32(0xFD40B010, 0); + Xil_Out32(0xFD40B014, 0); + Xil_Out32(0xFD40B018, 0); + Xil_Out32(0xFD40B01C, 0); + Xil_Out32(0xFD40B020, 0); + Xil_Out32(0xFD40B024, 0); + Xil_Out32(0xFD40B028, 0); + Xil_Out32(0xFD40B02C, 0); + Xil_Out32(0xFD40B030, 0); + Xil_Out32(0xFD40B034, 0); + Xil_Out32(0xFD40B038, 0); + Xil_Out32(0xFD40B03C, 0); + Xil_Out32(0xFD40B040, 0); + Xil_Out32(0xFD40B044, 0); + Xil_Out32(0xFD40B048, 0); + Xil_Out32(0xFD40B04C, 0); + Xil_Out32(0xFD40B050, 0); + Xil_Out32(0xFD40B054, 0); + Xil_Out32(0xFD40B058, 0); + Xil_Out32(0xFD40B068, 1); + Xil_Out32(0xFD40B06C, 0); + Xil_Out32(0xFD4090AC, 0); + psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); + psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); } - itercount = 0; - if (lane0_active) - serdes_bist_static_settings(0); - if (lane1_active) - serdes_bist_static_settings(1); - if (lane2_active) - serdes_bist_static_settings(2); - if (lane3_active) - serdes_bist_static_settings(3); - do { - if (gen2_calib != 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x04 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane1_active == 1) - ill1_val[1] = ((0x04 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane2_active == 1) - ill1_val[2] = ((0x04 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; - if (lane3_active == 1) - ill1_val[3] = ((0x04 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x04 + itercount * 8) >= - 0x100) ? 0x10 : 0x00; + if (lane3_active == 1) { + Xil_Out32(0xFD40F004, 0); + Xil_Out32(0xFD40F008, 0); + Xil_Out32(0xFD40F00C, 0); + Xil_Out32(0xFD40F010, 0); + Xil_Out32(0xFD40F014, 0); + Xil_Out32(0xFD40F018, 0); + Xil_Out32(0xFD40F01C, 0); + Xil_Out32(0xFD40F020, 0); + Xil_Out32(0xFD40F024, 0); + Xil_Out32(0xFD40F028, 0); + Xil_Out32(0xFD40F02C, 0); + Xil_Out32(0xFD40F030, 0); + Xil_Out32(0xFD40F034, 0); + Xil_Out32(0xFD40F038, 0); + Xil_Out32(0xFD40F03C, 0); + Xil_Out32(0xFD40F040, 0); + Xil_Out32(0xFD40F044, 0); + Xil_Out32(0xFD40F048, 0); + Xil_Out32(0xFD40F04C, 0); + Xil_Out32(0xFD40F050, 0); + Xil_Out32(0xFD40F054, 0); + Xil_Out32(0xFD40F058, 0); + Xil_Out32(0xFD40F068, 1); + Xil_Out32(0xFD40F06C, 0); + Xil_Out32(0xFD40D0AC, 0); + psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); + psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); + } + return 1; +}
- if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, - ill12_val[3]); - } - if (gen2_calib == 1) { - if (lane0_active == 1) - ill1_val[0] = ((0x104 + itercount * 8) % 0x100); - if (lane0_active == 1) - ill12_val[0] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane1_active == 1) - ill1_val[1] = ((0x104 + itercount * 8) % 0x100); - if (lane1_active == 1) - ill12_val[1] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane2_active == 1) - ill1_val[2] = ((0x104 + itercount * 8) % 0x100); - if (lane2_active == 1) - ill12_val[2] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; - if (lane3_active == 1) - ill1_val[3] = ((0x104 + itercount * 8) % 0x100); - if (lane3_active == 1) - ill12_val[3] = - ((0x104 + itercount * 8) >= - 0x200) ? 0x02 : 0x01; +static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) +{ + unsigned int rdata = 0; + unsigned int sata_gen2 = 1; + unsigned int temp_ill12 = 0; + unsigned int temp_PLL_REF_SEL_OFFSET; + unsigned int temp_TM_IQ_ILL1; + unsigned int temp_TM_E_ILL1; + unsigned int temp_tx_dig_tm_61; + unsigned int temp_tm_dig_6; + unsigned int temp_pll_fbdiv_frac_3_msb_offset;
- if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, - ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, - ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, - ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, - ill12_val[3]); - } + if (lane0_protocol == 2 || lane0_protocol == 1) { + Xil_Out32(0xFD401910, 0xF3); + Xil_Out32(0xFD40193C, 0xF3); + Xil_Out32(0xFD401914, 0xF3); + Xil_Out32(0xFD401940, 0xF3); + } + if (lane1_protocol == 2 || lane1_protocol == 1) { + Xil_Out32(0xFD405910, 0xF3); + Xil_Out32(0xFD40593C, 0xF3); + Xil_Out32(0xFD405914, 0xF3); + Xil_Out32(0xFD405940, 0xF3); + } + if (lane2_protocol == 2 || lane2_protocol == 1) { + Xil_Out32(0xFD409910, 0xF3); + Xil_Out32(0xFD40993C, 0xF3); + Xil_Out32(0xFD409914, 0xF3); + Xil_Out32(0xFD409940, 0xF3); + } + if (lane3_protocol == 2 || lane3_protocol == 1) { + Xil_Out32(0xFD40D910, 0xF3); + Xil_Out32(0xFD40D93C, 0xF3); + Xil_Out32(0xFD40D914, 0xF3); + Xil_Out32(0xFD40D940, 0xF3); + }
- if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); - if (lane0_active == 1) - currbistresult[0] = 0; - if (lane1_active == 1) - currbistresult[1] = 0; - if (lane2_active == 1) - currbistresult[2] = 0; - if (lane3_active == 1) - currbistresult[3] = 0; - serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol, - lane2_rate, lane1_protocol, lane1_rate, - lane0_protocol, lane0_rate); - if (lane3_active == 1) - serdes_bist_run(3); - if (lane2_active == 1) - serdes_bist_run(2); - if (lane1_active == 1) - serdes_bist_run(1); - if (lane0_active == 1) - serdes_bist_run(0); - tempbistresult = 0; - if (lane3_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(3); - tempbistresult = tempbistresult << 1; - if (lane2_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(2); - tempbistresult = tempbistresult << 1; - if (lane1_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(1); - tempbistresult = tempbistresult << 1; - if (lane0_active == 1) - tempbistresult = tempbistresult | serdes_bist_result(0); - Xil_Out32(0xFD410098, 0x0); - Xil_Out32(0xFD410098, 0x2); + if (sata_gen2 == 1) { + if (lane0_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); + Xil_Out32(0xFD402360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); + temp_TM_E_ILL1 = Xil_In32(0xFD401924); + Xil_Out32(0xFD4018F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); + temp_tm_dig_6 = Xil_In32(0xFD40106C); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD401990) & 0xF0;
- if (itercount < 32) { - iterresult[0] = - ((iterresult[0] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[1] = - ((iterresult[1] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[2] = - ((iterresult[2] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[3] = - ((iterresult[3] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } else { - iterresult[4] = - ((iterresult[4] << 1) | - ((tempbistresult & 0x1) == 0x1)); - iterresult[5] = - ((iterresult[5] << 1) | - ((tempbistresult & 0x2) == 0x2)); - iterresult[6] = - ((iterresult[6] << 1) | - ((tempbistresult & 0x4) == 0x4)); - iterresult[7] = - ((iterresult[7] << 1) | - ((tempbistresult & 0x8) == 0x8)); - } - currbistresult[0] = - currbistresult[0] | ((tempbistresult & 0x1) == 1); - currbistresult[1] = - currbistresult[1] | ((tempbistresult & 0x2) == 0x2); - currbistresult[2] = - currbistresult[2] | ((tempbistresult & 0x4) == 0x4); - currbistresult[3] = - currbistresult[3] | ((tempbistresult & 0x8) == 0x8); + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0);
- for (loop = 0; loop <= 3; loop++) { - if (currbistresult[loop] == 1 && prevbistresult[loop] == 1) - bistpasscount[loop] = bistpasscount[loop] + 1; - if (bistpasscount[loop] < 4 && currbistresult[loop] == 0 && - itercount > 2) { - if (meancountalt_bistpasscount[loop] < - bistpasscount[loop]) { - meancountalt_bistpasscount[loop] = - bistpasscount[loop]; - meancountalt[loop] = - ((itercount - 1) - - ((bistpasscount[loop] + 1) / 2)); - } - bistpasscount[loop] = 0; - } - if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && - (currbistresult[loop] == 0 || itercount == 63) && - prevbistresult[loop] == 1) - meancount[loop] = - (itercount - 1) - - ((bistpasscount[loop] + 1) / 2); - prevbistresult[loop] = currbistresult[loop]; + Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40106C, temp_tm_dig_6); + Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); + Xil_Out32(0xFD401990, temp_ill12); + Xil_Out32(0xFD401924, temp_TM_E_ILL1); } - } while (++itercount < 64); + if (lane1_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); + Xil_Out32(0xFD406360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); + temp_TM_E_ILL1 = Xil_In32(0xFD405924); + Xil_Out32(0xFD4058F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); + temp_tm_dig_6 = Xil_In32(0xFD40506C); + psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD405990) & 0xF0;
- for (loop = 0; loop <= 3; loop++) { - if (lane0_active == 0 && loop == 0) - continue; - if (lane1_active == 0 && loop == 1) - continue; - if (lane2_active == 0 && loop == 2) - continue; - if (lane3_active == 0 && loop == 3) - continue; + serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0);
- if (meancount[loop] == 0) - meancount[loop] = meancountalt[loop]; + Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40506C, temp_tm_dig_6); + Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); + Xil_Out32(0xFD405990, temp_ill12); + Xil_Out32(0xFD405924, temp_TM_E_ILL1); + } + if (lane2_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); + Xil_Out32(0xFD40A360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); + psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); + temp_TM_E_ILL1 = Xil_In32(0xFD409924); + Xil_Out32(0xFD4098F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); + temp_tm_dig_6 = Xil_In32(0xFD40906C); + psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD409990) & 0xF0;
- if (gen2_calib != 1) { - ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x04 + meancount[loop] * 8) >= - 0x100) ? 0x10 : 0x00; - Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]); - Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]); - Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]); - Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]); + serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0); + + Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40906C, temp_tm_dig_6); + Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); + Xil_Out32(0xFD409990, temp_ill12); + Xil_Out32(0xFD409924, temp_TM_E_ILL1); } - if (gen2_calib == 1) { - ill1_val[loop] = - ((0x104 + meancount[loop] * 8) % 0x100); - ill12_val[loop] = - ((0x104 + meancount[loop] * 8) >= - 0x200) ? 0x02 : 0x01; - Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]); - Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]); - Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]); - Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]); + if (lane3_protocol == 2) { + temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); + Xil_Out32(0xFD40E360, 0x0); + temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); + temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); + temp_TM_E_ILL1 = Xil_In32(0xFD40D924); + Xil_Out32(0xFD40D8F8, 0x78); + temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); + temp_tm_dig_6 = Xil_In32(0xFD40D06C); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); + temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; + + serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0); + + Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); + Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); + Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); + Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); + Xil_Out32(0xFD40D06C, temp_tm_dig_6); + Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); + temp_ill12 = + temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); + Xil_Out32(0xFD40D990, temp_ill12); + Xil_Out32(0xFD40D924, temp_TM_E_ILL1); } + rdata = Xil_In32(0xFD410098); + rdata = (rdata & 0xDF); + Xil_Out32(0xFD410098, rdata); } - if (gen2_calib != 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401924, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405924, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409924, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D924, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); + + if (lane0_protocol == 2 && lane0_rate == 3) { + psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); } - if (gen2_calib == 1) { - if (lane0_active == 1) - Xil_Out32(0xFD401928, ill1_val[0]); - if (lane0_active == 1) - psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); - if (lane1_active == 1) - Xil_Out32(0xFD405928, ill1_val[1]); - if (lane1_active == 1) - psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); - if (lane2_active == 1) - Xil_Out32(0xFD409928, ill1_val[2]); - if (lane2_active == 1) - psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); - if (lane3_active == 1) - Xil_Out32(0xFD40D928, ill1_val[3]); - if (lane3_active == 1) - psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); + if (lane1_protocol == 2 && lane1_rate == 3) { + psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); + } + if (lane2_protocol == 2 && lane2_rate == 3) { + psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); + } + if (lane3_protocol == 2 && lane3_rate == 3) { + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); + } + + if (lane0_protocol == 1) { + if (lane0_rate == 0) { + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + } else { + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, 0, 0); + serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, + lane2_protocol, lane2_rate, + lane1_protocol, lane1_rate, + lane0_protocol, lane0_rate, + 1); + } }
- if (lane0_active == 1) - psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); - if (lane1_active == 1) - psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); - if (lane2_active == 1) - psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); - if (lane3_active == 1) - psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); + if (lane0_protocol == 3) + Xil_Out32(0xFD401914, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401940, 0xF3); + if (lane0_protocol == 3) + Xil_Out32(0xFD401990, 0x20); + if (lane0_protocol == 3) + Xil_Out32(0xFD401924, 0x37); + + if (lane1_protocol == 3) + Xil_Out32(0xFD405914, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405940, 0xF3); + if (lane1_protocol == 3) + Xil_Out32(0xFD405990, 0x20); + if (lane1_protocol == 3) + Xil_Out32(0xFD405924, 0x37); + + if (lane2_protocol == 3) + Xil_Out32(0xFD409914, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409940, 0xF3); + if (lane2_protocol == 3) + Xil_Out32(0xFD409990, 0x20); + if (lane2_protocol == 3) + Xil_Out32(0xFD409924, 0x37); + + if (lane3_protocol == 3) + Xil_Out32(0xFD40D914, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D940, 0xF3); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D990, 0x20); + if (lane3_protocol == 3) + Xil_Out32(0xFD40D924, 0x37); + + return 1; +} + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
- Xil_Out32(0xFD410098, 0); - if (lane0_active == 1) { - Xil_Out32(0xFD403004, 0); - Xil_Out32(0xFD403008, 0); - Xil_Out32(0xFD40300C, 0); - Xil_Out32(0xFD403010, 0); - Xil_Out32(0xFD403014, 0); - Xil_Out32(0xFD403018, 0); - Xil_Out32(0xFD40301C, 0); - Xil_Out32(0xFD403020, 0); - Xil_Out32(0xFD403024, 0); - Xil_Out32(0xFD403028, 0); - Xil_Out32(0xFD40302C, 0); - Xil_Out32(0xFD403030, 0); - Xil_Out32(0xFD403034, 0); - Xil_Out32(0xFD403038, 0); - Xil_Out32(0xFD40303C, 0); - Xil_Out32(0xFD403040, 0); - Xil_Out32(0xFD403044, 0); - Xil_Out32(0xFD403048, 0); - Xil_Out32(0xFD40304C, 0); - Xil_Out32(0xFD403050, 0); - Xil_Out32(0xFD403054, 0); - Xil_Out32(0xFD403058, 0); - Xil_Out32(0xFD403068, 1); - Xil_Out32(0xFD40306C, 0); - Xil_Out32(0xFD4010AC, 0); - psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); - psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); - } - if (lane1_active == 1) { - Xil_Out32(0xFD407004, 0); - Xil_Out32(0xFD407008, 0); - Xil_Out32(0xFD40700C, 0); - Xil_Out32(0xFD407010, 0); - Xil_Out32(0xFD407014, 0); - Xil_Out32(0xFD407018, 0); - Xil_Out32(0xFD40701C, 0); - Xil_Out32(0xFD407020, 0); - Xil_Out32(0xFD407024, 0); - Xil_Out32(0xFD407028, 0); - Xil_Out32(0xFD40702C, 0); - Xil_Out32(0xFD407030, 0); - Xil_Out32(0xFD407034, 0); - Xil_Out32(0xFD407038, 0); - Xil_Out32(0xFD40703C, 0); - Xil_Out32(0xFD407040, 0); - Xil_Out32(0xFD407044, 0); - Xil_Out32(0xFD407048, 0); - Xil_Out32(0xFD40704C, 0); - Xil_Out32(0xFD407050, 0); - Xil_Out32(0xFD407054, 0); - Xil_Out32(0xFD407058, 0); - Xil_Out32(0xFD407068, 1); - Xil_Out32(0xFD40706C, 0); - Xil_Out32(0xFD4050AC, 0); - psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); - psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); - } - if (lane2_active == 1) { - Xil_Out32(0xFD40B004, 0); - Xil_Out32(0xFD40B008, 0); - Xil_Out32(0xFD40B00C, 0); - Xil_Out32(0xFD40B010, 0); - Xil_Out32(0xFD40B014, 0); - Xil_Out32(0xFD40B018, 0); - Xil_Out32(0xFD40B01C, 0); - Xil_Out32(0xFD40B020, 0); - Xil_Out32(0xFD40B024, 0); - Xil_Out32(0xFD40B028, 0); - Xil_Out32(0xFD40B02C, 0); - Xil_Out32(0xFD40B030, 0); - Xil_Out32(0xFD40B034, 0); - Xil_Out32(0xFD40B038, 0); - Xil_Out32(0xFD40B03C, 0); - Xil_Out32(0xFD40B040, 0); - Xil_Out32(0xFD40B044, 0); - Xil_Out32(0xFD40B048, 0); - Xil_Out32(0xFD40B04C, 0); - Xil_Out32(0xFD40B050, 0); - Xil_Out32(0xFD40B054, 0); - Xil_Out32(0xFD40B058, 0); - Xil_Out32(0xFD40B068, 1); - Xil_Out32(0xFD40B06C, 0); - Xil_Out32(0xFD4090AC, 0); - psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); - psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); - } - if (lane3_active == 1) { - Xil_Out32(0xFD40F004, 0); - Xil_Out32(0xFD40F008, 0); - Xil_Out32(0xFD40F00C, 0); - Xil_Out32(0xFD40F010, 0); - Xil_Out32(0xFD40F014, 0); - Xil_Out32(0xFD40F018, 0); - Xil_Out32(0xFD40F01C, 0); - Xil_Out32(0xFD40F020, 0); - Xil_Out32(0xFD40F024, 0); - Xil_Out32(0xFD40F028, 0); - Xil_Out32(0xFD40F02C, 0); - Xil_Out32(0xFD40F030, 0); - Xil_Out32(0xFD40F034, 0); - Xil_Out32(0xFD40F038, 0); - Xil_Out32(0xFD40F03C, 0); - Xil_Out32(0xFD40F040, 0); - Xil_Out32(0xFD40F044, 0); - Xil_Out32(0xFD40F048, 0); - Xil_Out32(0xFD40F04C, 0); - Xil_Out32(0xFD40F050, 0); - Xil_Out32(0xFD40F054, 0); - Xil_Out32(0xFD40F058, 0); - Xil_Out32(0xFD40F068, 1); - Xil_Out32(0xFD40F06C, 0); - Xil_Out32(0xFD40D0AC, 0); - psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); - psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); - } return 1; }
-static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, - u32 lane2_protocol, u32 lane2_rate, - u32 lane1_protocol, u32 lane1_rate, - u32 lane0_protocol, u32 lane0_rate) +static unsigned long psu_peripherals_pre_init_data(void) { - unsigned int rdata = 0; - unsigned int sata_gen2 = 1; - unsigned int temp_ill12 = 0; - unsigned int temp_PLL_REF_SEL_OFFSET; - unsigned int temp_TM_IQ_ILL1; - unsigned int temp_TM_E_ILL1; - unsigned int temp_tx_dig_tm_61; - unsigned int temp_tm_dig_6; - unsigned int temp_pll_fbdiv_frac_3_msb_offset; + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
- if (lane0_protocol == 2 || lane0_protocol == 1) { - Xil_Out32(0xFD401910, 0xF3); - Xil_Out32(0xFD40193C, 0xF3); - Xil_Out32(0xFD401914, 0xF3); - Xil_Out32(0xFD401940, 0xF3); - } - if (lane1_protocol == 2 || lane1_protocol == 1) { - Xil_Out32(0xFD405910, 0xF3); - Xil_Out32(0xFD40593C, 0xF3); - Xil_Out32(0xFD405914, 0xF3); - Xil_Out32(0xFD405940, 0xF3); - } - if (lane2_protocol == 2 || lane2_protocol == 1) { - Xil_Out32(0xFD409910, 0xF3); - Xil_Out32(0xFD40993C, 0xF3); - Xil_Out32(0xFD409914, 0xF3); - Xil_Out32(0xFD409940, 0xF3); - } - if (lane3_protocol == 2 || lane3_protocol == 1) { - Xil_Out32(0xFD40D910, 0xF3); - Xil_Out32(0xFD40D93C, 0xF3); - Xil_Out32(0xFD40D914, 0xF3); - Xil_Out32(0xFD40D940, 0xF3); - } + return 1; +}
- if (sata_gen2 == 1) { - if (lane0_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); - Xil_Out32(0xFD402360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); - psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); - temp_TM_E_ILL1 = Xil_In32(0xFD401924); - Xil_Out32(0xFD4018F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); - temp_tm_dig_6 = Xil_In32(0xFD40106C); - psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD401990) & 0xF0; +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + + serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); + psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
- serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0); + return 1; +}
- Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40106C, temp_tm_dig_6); - Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); - Xil_Out32(0xFD401990, temp_ill12); - Xil_Out32(0xFD401924, temp_TM_E_ILL1); - } - if (lane1_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); - Xil_Out32(0xFD406360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); - psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); - temp_TM_E_ILL1 = Xil_In32(0xFD405924); - Xil_Out32(0xFD4058F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); - temp_tm_dig_6 = Xil_In32(0xFD40506C); - psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD405990) & 0xF0; +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
- serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0); + return 1; +}
- Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40506C, temp_tm_dig_6); - Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); - Xil_Out32(0xFD405990, temp_ill12); - Xil_Out32(0xFD405924, temp_TM_E_ILL1); - } - if (lane2_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); - Xil_Out32(0xFD40A360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); - psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); - temp_TM_E_ILL1 = Xil_In32(0xFD409924); - Xil_Out32(0xFD4098F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); - temp_tm_dig_6 = Xil_In32(0xFD40906C); - psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD409990) & 0xF0; +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); + psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U); + psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
- serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0); + return 1; +}
- Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40906C, temp_tm_dig_6); - Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); - Xil_Out32(0xFD409990, temp_ill12); - Xil_Out32(0xFD409924, temp_TM_E_ILL1); - } - if (lane3_protocol == 2) { - temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); - Xil_Out32(0xFD40E360, 0x0); - temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); - psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); - temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); - temp_TM_E_ILL1 = Xil_In32(0xFD40D924); - Xil_Out32(0xFD40D8F8, 0x78); - temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); - temp_tm_dig_6 = Xil_In32(0xFD40D06C); - psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); - psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); - temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + int cur_R006_tREFPRD;
- serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0); + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011);
- Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); - Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); - Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); - Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); - Xil_Out32(0xFD40D06C, temp_tm_dig_6); - Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); - temp_ill12 = - temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); - Xil_Out32(0xFD40D990, temp_ill12); - Xil_Out32(0xFD40D924, temp_TM_E_ILL1); - } - rdata = Xil_In32(0xFD410098); - rdata = (rdata & 0xDF); - Xil_Out32(0xFD410098, rdata); + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0;
- if (lane0_protocol == 2 && lane0_rate == 3) { - psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); - } - if (lane1_protocol == 2 && lane1_rate == 3) { - psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); - } - if (lane2_protocol == 2 && lane2_rate == 3) { - psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); - } - if (lane3_protocol == 2 && lane3_rate == 3) { - psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); - psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); - } + Xil_Out32(0xFD080004U, 0x00040063U);
- if (lane0_protocol == 1) { - if (lane0_rate == 0) { - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - } else { - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, 0, 0); - serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate, - lane2_protocol, lane2_rate, - lane1_protocol, lane1_rate, - lane0_protocol, lane0_rate, - 1); - } - } + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
- if (lane0_protocol == 3) - Xil_Out32(0xFD401914, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401940, 0xF3); - if (lane0_protocol == 3) - Xil_Out32(0xFD401990, 0x20); - if (lane0_protocol == 3) - Xil_Out32(0xFD401924, 0x37); + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0;
- if (lane1_protocol == 3) - Xil_Out32(0xFD405914, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405940, 0xF3); - if (lane1_protocol == 3) - Xil_Out32(0xFD405990, 0x20); - if (lane1_protocol == 3) - Xil_Out32(0xFD405924, 0x37); + Xil_Out32(0xFD080200U, 0x100091C7U);
- if (lane2_protocol == 3) - Xil_Out32(0xFD409914, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409940, 0xF3); - if (lane2_protocol == 3) - Xil_Out32(0xFD409990, 0x20); - if (lane2_protocol == 3) - Xil_Out32(0xFD409924, 0x37); + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
- if (lane3_protocol == 3) - Xil_Out32(0xFD40D914, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D940, 0xF3); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D990, 0x20); - if (lane3_protocol == 3) - Xil_Out32(0xFD40D924, 0x37); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
return 1; }
On 6/20/22 18:36, Stefan Herbrechtsmeier wrote:
From: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
Check if rx channel dev pointer is valid and not if the address of the pointer is valid.
Signed-off-by: Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com
(no changes since v1)
drivers/firmware/firmware-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 0f0d2b07c0..341d7cf135 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -92,7 +92,7 @@ static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) res_maxlen > PMUFW_PAYLOAD_ARG_CNT) return -EINVAL;
- if (!(zynqmp_power.tx_chan.dev) || !(&zynqmp_power.rx_chan.dev))
if (!(zynqmp_power.tx_chan.dev) || !(zynqmp_power.rx_chan.dev)) return -EINVAL;
debug("%s, Sending IPI message with ID: 0x%0x\n", __func__, req[0]);
Applied. M
participants (2)
-
Michal Simek -
Stefan Herbrechtsmeier