The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled.

Signed-off-by: Peng Fan Peng.Fan@freescale.com Signed-off-by: Ranjani Vaidyanathan Ranjani.Vaidyanathan@freescale.com --- arch/arm/cpu/armv7/mx6/soc.c | 24 ++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/crm_regs.h | 2 ++ 2 files changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5f5f497..13807b6 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -255,6 +255,23 @@ static void clear_mmdc_ch_mask(void) writel(0, &mxc_ccm->ccdr); }

+static void init_bandgap(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + /* + * Ensure the bandgap has stabilized. + */ + while (!(readl(&anatop->ana_misc0) & 0x80)) + ; + /* + * For best noise performance of the analog blocks using the + * outputs of the bandgap, the reftop_selfbiasoff bit should + * be set. + */ + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); +} + + #ifdef CONFIG_MX6SL static void set_preclk_from_osc(void) { @@ -275,6 +292,13 @@ int arch_cpu_init(void) clear_mmdc_ch_mask();

/* + * Disable self-bias circuit in the analog bandap. + * The self-bias circuit is used by the bandgap during startup. + * This bit should be set after the bandgap has initialized. + */ + init_bandgap(); + + /* * When low freq boot is enabled, ROM will not set AHB * freq, so we need to ensure AHB freq is 132MHz in such * scenario. diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 39f3c07..0592ce0 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1063,4 +1063,6 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)

+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 + #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */

There are three wdogs for i.MX 6SoloX. Add wdog3 support in function imx_set_wdog_powerdown.

Signed-off-by: Peng Fan Peng.Fan@freescale.com --- arch/arm/cpu/armv7/mx6/soc.c | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 13807b6..847e714 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -230,6 +230,11 @@ static void imx_set_wdog_powerdown(bool enable) struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;

+#ifdef CONFIG_MX6SX + struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; + writew(enable, &wdog3->wmcr); +#endif + /* Write to the PDE (Power Down Enable) bit */ writew(enable, &wdog1->wmcr); writew(enable, &wdog2->wmcr);

Hi,

Please ignore this patch 1/3, since "imx: mx6: Fixed AIPS3 base address issue" from Ye.Li already fix this. Patch 2/3 and patch 3/3 are fine. Please review.

On 1/15/2015 2:22 PM, Peng Fan wrote:

Signed-off-by: Peng Fan Peng.Fan@freescale.com

arch/arm/include/asm/arch-mx6/imx-regs.h | 50 ++++++++++++++++---------------- 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5314298..44e31c9 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -277,31 +277,31 @@ #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)

#ifdef CONFIG_MX6SX -#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) -#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) -#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) -#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) -#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) -#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) -#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) -#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) -#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) -#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) -#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) -#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) -#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) -#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) -#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) -#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) -#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) -#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) -#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) -#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) -#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) -#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) +#define GIS_BASE_ADDR (AIPS3_BASE_ADDR + 0x04000) +#define DCIC1_BASE_ADDR (AIPS3_BASE_ADDR + 0x0C000) +#define DCIC2_BASE_ADDR (AIPS3_BASE_ADDR + 0x10000) +#define CSI1_BASE_ADDR (AIPS3_BASE_ADDR + 0x14000) +#define PXP_BASE_ADDR (AIPS3_BASE_ADDR + 0x18000) +#define CSI2_BASE_ADDR (AIPS3_BASE_ADDR + 0x1C000) +#define LCDIF1_BASE_ADDR (AIPS3_BASE_ADDR + 0x20000) +#define LCDIF2_BASE_ADDR (AIPS3_BASE_ADDR + 0x24000) +#define VADC_BASE_ADDR (AIPS3_BASE_ADDR + 0x28000) +#define VDEC_BASE_ADDR (AIPS3_BASE_ADDR + 0x2C000) +#define SPBA_BASE_ADDR (AIPS3_BASE_ADDR + 0x3C000) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_BASE_ADDR + 0x7C000) +#define ADC1_BASE_ADDR (AIPS3_BASE_ADDR + 0x80000) +#define ADC2_BASE_ADDR (AIPS3_BASE_ADDR + 0x84000) +#define WDOG3_BASE_ADDR (AIPS3_BASE_ADDR + 0x88000) +#define ECSPI5_BASE_ADDR (AIPS3_BASE_ADDR + 0x8C000) +#define HS_BASE_ADDR (AIPS3_BASE_ADDR + 0x90000) +#define MU_MCU_BASE_ADDR (AIPS3_BASE_ADDR + 0x94000) +#define CANFD_BASE_ADDR (AIPS3_BASE_ADDR + 0x98000) +#define MU_DSP_BASE_ADDR (AIPS3_BASE_ADDR + 0x9C000) +#define UART6_BASE_ADDR (AIPS3_BASE_ADDR + 0xA0000) +#define PWM5_BASE_ADDR (AIPS3_BASE_ADDR + 0xA4000) +#define PWM6_BASE_ADDR (AIPS3_BASE_ADDR + 0xA8000) +#define PWM7_BASE_ADDR (AIPS3_BASE_ADDR + 0xAC000) +#define PWM8_BASE_ADDR (AIPS3_BASE_ADDR + 0xB0000) #endif

#define CHIP_REV_1_0 0x10

Thanks, Peng.