[U-Boot-Users] Question on ECC SDRAM initialization in PPC4xx
In the ppc4xx cpu source files, I see that ECC for SDRAM is supported. The code checks some settings ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8) and then enables ECC on the processor.
*Does this automatically detect the presence of a SDRAM chips connected in an ECC configuration?* Are additional software configuration settings needed before this point to enable ECC?
SOURCE ./cpu/ppc4xx/spd_sdram.c
/* now check for ECC ability of module. We only support ECC * on 32 bit wide devices with 8 bit ECC. */ if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) { sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT; ecc_on = 1; } else { sdram0_ecccfg = 0; ecc_on = 0; }
Thanks, Jeff
Hi Jeff,
On Friday 04 August 2006 19:01, Jeff Mann wrote:
In the ppc4xx cpu source files, I see that ECC for SDRAM is supported. The code checks some settings ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8) and then enables ECC on the processor.
*Does this automatically detect the presence of a SDRAM chips connected in an ECC configuration?* Are additional software configuration settings needed before this point to enable ECC?
Please note that the spd_sdram code handles 405 SDRAM and 440 DDR. Your code references the 405 SDRAM init code. IIRC, the 440 part of the code doesn't seem to support ECC right now.
What are you looking for exactly? For a know to be working ECC init (at least for me), please take a look at the non SPD 4xx SDRAM init code cpu/ppc4xx/sdram.c. Here you will find code to setup and init the 440 DDR controller with and without ECC support (CONFIG_SDRAM_ECC).
Best regards, Stefan
participants (2)
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Jeff Mann -
Stefan Roese