Hi Stefano,

On Tue, Nov 28, 2017 at 06:15:30PM +0100, Stefano Babic wrote:

Hi Peng,

On 28/11/2017 13:31, Peng Fan wrote:

...

Add i.MX8M into Kconfig, create a new folder mx8m dedicated for i.MX8M.

Signed-off-by: Peng Fan peng.fan@nxp.com

arch/arm/Kconfig | 8 ++++++++ arch/arm/Makefile | 4 ++-- arch/arm/mach-imx/mx8m/Kconfig | 10 ++++++++++ 3 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-imx/mx8m/Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 30e71b2569..e579986d14 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -588,6 +588,12 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC.

+config ARCH_MX8M

• bool "NXP i.MX8M platform"
• select ARM64
• select DM
• select SUPPORT_SPL

I think we should start from the beginning with support for multiple variants of the processor. I know there will be at least i.MX8 and i.MX8M, but I suppose that I am not well informed and many variants will come, exactly as we had with i.MX6.

So we need a hierarchy: first the SOC family, then the SOC variant: MX8 and MX8M (or whatever).

But in the patches, it is not clear because ARCH = SOC = M8M.

Which variants are already known ? As far as I can see, at least Quad, QuadMax and QuadPlus.

i.MX8M is different from Quad/QuadMax and etc. It is similar as i.MX6/7 , all is controlled by Cortex-A[x]. So I choose a new SoC family entry here. Just like we have MX7 and MX7ULP. MX8 will be used for Quad, QuadMax QuadX. MX8M here is used for i.MX8MQ and etc.

What do you think?

Thanks, Peng.

...

config ARCH_MX25 bool "NXP MX25" select CPU_ARM926EJS @@ -1157,6 +1163,8 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig"

source "arch/arm/mach-imx/mx2/Kconfig"

+source "arch/arm/mach-imx/mx8m/Kconfig"

source "arch/arm/mach-imx/mx7ulp/Kconfig"

source "arch/arm/mach-imx/mx7/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5f1caf8f86..4db0398dde 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -95,11 +95,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/

ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m)) libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610)) libs-y += arch/arm/mach-imx/ endif endif diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig new file mode 100644 index 0000000000..3a84c2f2b0 --- /dev/null +++ b/arch/arm/mach-imx/mx8m/Kconfig @@ -0,0 +1,10 @@ +if ARCH_MX8M

+config MX8M

• bool
• select ROM_UNIFIED_SECTIONS

+config SYS_SOC

• default "mx8m"

+endif

Best regards, Stefano

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================

--

Hi Stefano,

-----Original Message----- From: Stefano Babic [mailto:sbabic@denx.de] Sent: Wednesday, November 29, 2017 6:05 PM To: Peng Fan van.freenix@gmail.com; Stefano Babic sbabic@denx.de Cc: Peng Fan peng.fan@nxp.com; Fabio Estevam fabio.estevam@nxp.com; u-boot@lists.denx.de Subject: Re: [PATCH 01/23] imx: add i.MX8M into Kconfig

Hi Peng,

On 29/11/2017 06:49, Peng Fan wrote:

...

Hi Stefano,

On Tue, Nov 28, 2017 at 06:15:30PM +0100, Stefano Babic wrote:

...

Hi Peng,

On 28/11/2017 13:31, Peng Fan wrote:

...

Add i.MX8M into Kconfig, create a new folder mx8m dedicated for i.MX8M.

Signed-off-by: Peng Fan peng.fan@nxp.com

arch/arm/Kconfig | 8 ++++++++ arch/arm/Makefile | 4 ++-- arch/arm/mach-imx/mx8m/Kconfig | 10 ++++++++++ 3 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-imx/mx8m/Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 30e71b2569..e579986d14 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -588,6 +588,12 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC.

+config ARCH_MX8M

• bool "NXP i.MX8M platform"
• select ARM64
• select DM
• select SUPPORT_SPL

I think we should start from the beginning with support for multiple variants of the processor. I know there will be at least i.MX8 and i.MX8M, but I suppose that I am not well informed and many variants will come, exactly as we had with i.MX6.

So we need a hierarchy: first the SOC family, then the SOC variant: MX8 and MX8M (or whatever).

But in the patches, it is not clear because ARCH = SOC = M8M.

Which variants are already known ? As far as I can see, at least Quad, QuadMax and QuadPlus.

i.MX8M is different from Quad/QuadMax and etc. It is similar as i.MX6/7 , all is controlled by Cortex-A[x].

Ouch...

...

So I choose a new SoC family entry here. Just like we have MX7 and MX7ULP. MX8 will be used for Quad, QuadMax QuadX

Ok, this is also my expectation.

...

. MX8M here is used for i.MX8MQ and etc.

What do you think?

I have so less information and knowledge about the new NXP processors and I cannot better help, I trust your judge. But what can we share between M8M and M8 ? What about all stuff going into mx8m directories (cpu, closk, ..) ? Could they be reused for MX8 or do they remain an island ?

MX8M and MX8 has different architecture. To MX8, all clocks, power domains, pin configuration, and reset and etc are all controlled by SCU and different clock/power/xx architecture with MX8M.

So most code could not be reused.

Thanks, Peng.

Regards, Stefano

...

Thanks, Peng.

...

...

config ARCH_MX25 bool "NXP MX25" select CPU_ARM926EJS @@ -1157,6 +1163,8 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig"

source "arch/arm/mach-imx/mx2/Kconfig"

+source "arch/arm/mach-imx/mx8m/Kconfig"

source "arch/arm/mach-imx/mx7ulp/Kconfig"

source "arch/arm/mach-imx/mx7/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5f1caf8f86..4db0398dde 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -95,11 +95,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/

ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter

$(SOC),

...

...

...

mx25 mx5 mx6 mx7 mx35)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter

$(SOC),

...

...

...

+mx25 mx5 mx6 mx7 mx35 mx8m)) libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs +mx8m vf610)) libs-y += arch/arm/mach-imx/ endif endif diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig new file mode 100644 index 0000000000..3a84c2f2b0 --- /dev/null +++ b/arch/arm/mach-imx/mx8m/Kconfig @@ -0,0 +1,10 @@ +if ARCH_MX8M

+config MX8M

• bool
• select ROM_UNIFIED_SECTIONS

+config SYS_SOC

• default "mx8m"

+endif

Best regards, Stefano

--

============================================================

...

...

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de

============================================================

...

--

========= DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de ============================================================ =========

Hi Peng,

On 28/11/2017 13:31, Peng Fan wrote:

Add register definition header file for i.MX8M

Signed-off-by: Peng Fan peng.fan@nxp.com

arch/arm/include/asm/arch-mx8m/imx-regs.h | 298 ++++++++++++++++++++++++++++++ 1 file changed, 298 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx8m/imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h b/arch/arm/include/asm/arch-mx8m/imx-regs.h new file mode 100644 index 0000000000..0c02721df1 --- /dev/null +++ b/arch/arm/include/asm/arch-mx8m/imx-regs.h @@ -0,0 +1,298 @@ +/*

• • Copyright 2017 NXP
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <asm/mach-imx/regs-lcdif.h>

+#ifndef __ASM_ARCH_MX8M_REGS_H__ +#define __ASM_ARCH_MX8M_REGS_H__

+#define M4_BOOTROM_BASE_ADDR 0x007E0000

+#define SAI1_BASE_ADDR 0x30010000 +#define SAI6_BASE_ADDR 0x30030000 +#define SAI5_BASE_ADDR 0x30040000 +#define SAI4_BASE_ADDR 0x30050000 +#define SPBA2_BASE_ADDR 0x300F0000 +#define AIPS1_BASE_ADDR 0x301F0000 +#define GPIO1_BASE_ADDR 0X30200000 +#define GPIO2_BASE_ADDR 0x30210000 +#define GPIO3_BASE_ADDR 0x30220000 +#define GPIO4_BASE_ADDR 0x30230000 +#define GPIO5_BASE_ADDR 0x30240000 +#define ANA_TSENSOR_BASE_ADDR 0x30260000 +#define ANA_OSC_BASE_ADDR 0x30270000 +#define WDOG1_BASE_ADDR 0x30280000 +#define WDOG2_BASE_ADDR 0x30290000 +#define WDOG3_BASE_ADDR 0x302A0000 +#define SDMA2_BASE_ADDR 0x302C0000 +#define GPT1_BASE_ADDR 0x302D0000 +#define GPT2_BASE_ADDR 0x302E0000 +#define GPT3_BASE_ADDR 0x302F0000 +#define ROMCP_BASE_ADDR 0x30310000 +#define LCDIF_BASE_ADDR 0x30320000 +#define IOMUXC_BASE_ADDR 0x30330000 +#define IOMUXC_GPR_BASE_ADDR 0x30340000 +#define OCOTP_BASE_ADDR 0x30350000 +#define ANA_PLL_BASE_ADDR 0x30360000 +#define SNVS_HP_BASE_ADDR 0x30370000 +#define CCM_BASE_ADDR 0x30380000 +#define SRC_BASE_ADDR 0x30390000 +#define GPC_BASE_ADDR 0x303A0000 +#define SEMAPHORE1_BASE_ADDR 0x303B0000 +#define SEMAPHORE2_BASE_ADDR 0x303C0000 +#define RDC_BASE_ADDR 0x303D0000 +#define CSU_BASE_ADDR 0x303E0000

+#define AIPS2_BASE_ADDR 0x305F0000 +#define PWM1_BASE_ADDR 0x30660000 +#define PWM2_BASE_ADDR 0x30670000 +#define PWM3_BASE_ADDR 0x30680000 +#define PWM4_BASE_ADDR 0x30690000 +#define SYSCNT_RD_BASE_ADDR 0x306A0000 +#define SYSCNT_CMP_BASE_ADDR 0x306B0000 +#define SYSCNT_CTRL_BASE_ADDR 0x306C0000 +#define GPT6_BASE_ADDR 0x306E0000 +#define GPT5_BASE_ADDR 0x306F0000 +#define GPT4_BASE_ADDR 0x30700000 +#define PERFMON1_BASE_ADDR 0x307C0000 +#define PERFMON2_BASE_ADDR 0x307D0000 +#define QOSC_BASE_ADDR 0x307F0000

+#define SPDIF1_BASE_ADDR 0x30810000 +#define ECSPI1_BASE_ADDR 0x30820000 +#define ECSPI2_BASE_ADDR 0x30830000 +#define ECSPI3_BASE_ADDR 0x30840000 +#define UART1_BASE_ADDR 0x30860000 +#define UART3_BASE_ADDR 0x30880000 +#define UART2_BASE_ADDR 0x30890000 +#define SPDIF2_BASE_ADDR 0x308A0000 +#define SAI2_BASE_ADDR 0x308B0000 +#define SAI3_BASE_ADDR 0x308C0000 +#define SPBA1_BASE_ADDR 0x308F0000 +#define CAAM_BASE_ADDR 0x30900000 +#define AIPS3_BASE_ADDR 0x309F0000 +#define MIPI_PHY_BASE_ADDR 0x30A00000 +#define MIPI_DSI_BASE_ADDR 0x30A10000 +#define I2C1_BASE_ADDR 0x30A20000 +#define I2C2_BASE_ADDR 0x30A30000 +#define I2C3_BASE_ADDR 0x30A40000 +#define I2C4_BASE_ADDR 0x30A50000 +#define UART4_BASE_ADDR 0x30A60000 +#define MIPI_CSI_BASE_ADDR 0x30A70000 +#define MIPI_CSI_PHY1_BASE_ADDR 0x30A80000 +#define CSI1_BASE_ADDR 0x30A90000 +#define MU_A_BASE_ADDR 0x30AA0000 +#define MU_B_BASE_ADDR 0x30AB0000 +#define SEMAPHOR_HS_BASE_ADDR 0x30AC0000 +#define USDHC1_BASE_ADDR 0x30B40000 +#define USDHC2_BASE_ADDR 0x30B50000 +#define MIPI_CS2_BASE_ADDR 0x30B60000 +#define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000 +#define CSI2_BASE_ADDR 0x30B80000 +#define QSPI0_BASE_ADDR 0x30BB0000 +#define QSPI0_AMBA_BASE 0x08000000 +#define SDMA1_BASE_ADDR 0x30BD0000 +#define ENET1_BASE_ADDR 0x30BE0000

+#define HDMI_CTRL_BASE_ADDR 0x32C00000 +#define AIPS4_BASE_ADDR 0x32DF0000 +#define DC1_BASE_ADDR 0x32E00000 +#define DC2_BASE_ADDR 0x32E10000 +#define DC3_BASE_ADDR 0x32E20000 +#define HDMI_SEC_BASE_ADDR 0x32E40000 +#define TZASC_BASE_ADDR 0x32F80000 +#define MTR_BASE_ADDR 0x32FB0000 +#define PLATFORM_CTRL_BASE_ADDR 0x32FE0000

+#define MXS_APBH_BASE 0x33000000 +#define MXS_GPMI_BASE 0x33002000 +#define MXS_BCH_BASE 0x33004000

+#define USB1_BASE_ADDR 0x38100000 +#define USB2_BASE_ADDR 0x38200000 +#define USB1_PHY_BASE_ADDR 0x381F0000 +#define USB2_PHY_BASE_ADDR 0x382F0000

+#define IOMUXC_GPR0 (IOMUXC_GPR_BASE_ADDR + 0x00) +#define IOMUXC_GPR1 (IOMUXC_GPR_BASE_ADDR + 0x04) +#define IOMUXC_GPR2 (IOMUXC_GPR_BASE_ADDR + 0x08) +#define IOMUXC_GPR3 (IOMUXC_GPR_BASE_ADDR + 0x0c) +#define IOMUXC_GPR4 (IOMUXC_GPR_BASE_ADDR + 0x10) +#define IOMUXC_GPR5 (IOMUXC_GPR_BASE_ADDR + 0x14) +#define IOMUXC_GPR6 (IOMUXC_GPR_BASE_ADDR + 0x18) +#define IOMUXC_GPR7 (IOMUXC_GPR_BASE_ADDR + 0x1c) +#define IOMUXC_GPR8 (IOMUXC_GPR_BASE_ADDR + 0x20) +#define IOMUXC_GPR9 (IOMUXC_GPR_BASE_ADDR + 0x24) +#define IOMUXC_GPR10 (IOMUXC_GPR_BASE_ADDR + 0x28)

We have only structures in u-boot and not defines + offset. This (and this is an issue in all these patches) must be converted in a structure, exactly as we have with i.MX6.

Please note that due to missing documentation, I cannot deeper check.

+#define GPR_TZASC_EN (1 << 0) +#define GPR_TZASC_EN_LOCK (1 << 16)

+#define SCTR_BASE_ADDR 0x306C0000 +#define CNTCR_OFF 0x00 +#define CNTFID0_OFF 0x20 +#define CNTFID1_OFF 0x24

Ditto, they are offsets (at leastI interprete it), and it should be converted.

+#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9)

+#define SRC_SCR_M4_ENABLE_OFFSET 3 +#define SRC_SCR_M4_ENABLE_MASK (1 << 3) +#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0 +#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 0)

+#define MXS_LCDIF_BASE LCDIF_BASE_ADDR

+#define SRC_IPS_BASE_ADDR 0x30390000 +#define SRC_DDRC_RCR_ADDR 0x30391000 +#define SRC_DDRC2_RCR_ADDR 0x30391004

+#define DDR_CSD1_BASE_ADDR 0x40000000

+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))

I see there is the same in i.MX6, but __KERNEL_STRICT_NAMES is not used in U-Boot and can be dropped.

+#include <asm/types.h> +struct ocotp_regs {

• u32 ctrl;
• u32 ctrl_set;
• u32 ctrl_clr;
• u32 ctrl_tog;
• u32 timing;
• u32 rsvd0[3];
• u32 data;
• u32 rsvd1[3];
• u32 read_ctrl;
• u32 rsvd2[3];
• u32 read_fuse_data;
• u32 rsvd3[3];
• u32 sw_sticky;
• u32 rsvd4[3];
• u32 scs;
• u32 scs_set;
• u32 scs_clr;
• u32 scs_tog;
• u32 crc_addr;
• u32 rsvd5[3];
• u32 crc_value;
• u32 rsvd6[3];
• u32 version;
• u32 rsvd7[0xdb];
• /* fuse banks */
• struct fuse_bank {

• u32	fuse_regs[0x10];
  

• } bank[0];

+};

ok, so it is compatible with i.MX6

+struct fuse_bank0_regs {

• u32 lock;
• u32 rsvd0[3];
• u32 uid_low;
• u32 rsvd1[3];
• u32 uid_high;
• u32 rsvd2[7];

+};

+struct fuse_bank1_regs {

• u32 tester3;
• u32 rsvd0[3];
• u32 tester4;
• u32 rsvd1[3];
• u32 tester5;
• u32 rsvd2[3];
• u32 cfg0;
• u32 rsvd3[3];

+};

+struct fuse_bank9_regs {

• u32 mac_addr0;
• u32 rsvd0[3];
• u32 mac_addr1;
• u32 rsvd1[11];

+};

+/* System Reset Controller (SRC) */ +struct src {

• u32 scr;
• u32 a53rcr;
• u32 a53rcr1;
• u32 m4rcr;
• u32 reserved1[4];
• u32 usbophy1_rcr;
• u32 usbophy2_rcr;
• u32 mipiphy_rcr;
• u32 pciephy_rcr;
• u32 hdmi_rcr;
• u32 disp_rcr;
• u32 reserved2[2];
• u32 gpu_rcr;
• u32 vpu_rcr;
• u32 pcie2_rcr;
• u32 mipiphy1_rcr;
• u32 mipiphy2_rcr;
• u32 reserved3;
• u32 sbmr1;
• u32 srsr;
• u32 reserved4[2];
• u32 sisr;
• u32 simr;
• u32 sbmr2;
• u32 gpr1;
• u32 gpr2;
• u32 gpr3;
• u32 gpr4;
• u32 gpr5;
• u32 gpr6;
• u32 gpr7;
• u32 gpr8;
• u32 gpr9;
• u32 gpr10;
• u32 reserved5[985];
• u32 ddr1_rcr;
• u32 ddr2_rcr;

+};

+struct wdog_regs {

• u16 wcr; /* Control */
• u16 wsr; /* Service */
• u16 wrsr; /* Reset Status */
• u16 wicr; /* Interrupt Control */
• u16 wmcr; /* Miscellaneous Control */

+};

+/* Boot device type */ +#define BOOT_TYPE_SD 0x1 +#define BOOT_TYPE_MMC 0x2 +#define BOOT_TYPE_NAND 0x3 +#define BOOT_TYPE_QSPI 0x4 +#define BOOT_TYPE_WEIM 0x5 +#define BOOT_TYPE_SPINOR 0x6 +#define BOOT_TYPE_USB 0xF

+#define ROM_SW_INFO_ADDR 0x00000968 +#define ROM_SW_INFO_ADDR_A0 0x000009e8

+struct bootrom_sw_info {

• u8 reserved_1;
• u8 boot_dev_instance;
• u8 boot_dev_type;
• u8 reserved_2;
• u32 core_freq;
• u32 axi_freq;
• u32 ddr_freq;
• u32 tick_freq;
• u32 reserved_3[3];

+};

+#include <stdbool.h> +bool is_usb_boot(void);

+#define is_boot_from_usb is_usb_boot +#define disconnect_from_pc(void) \

• clrbits_le32(USB1_BASE_ADDR + 0xc704, (1 << 31));

It is like in i.MX7, but for i.MX7 we have plain macros. If we need real function as is_usb_boot(), we should move the code outside this header - we define in imx-regs.h just the layout of the registers.

Best regards, Stefano

On 29/11/2017 07:01, Peng Fan wrote:

On Tue, Nov 28, 2017 at 06:40:40PM +0100, Stefano Babic wrote:

...

Hi Peng,

On 28/11/2017 13:31, Peng Fan wrote:

...

Add register definition header file for i.MX8M

Signed-off-by: Peng Fan peng.fan@nxp.com

arch/arm/include/asm/arch-mx8m/imx-regs.h | 298 ++++++++++++++++++++++++++++++ 1 file changed, 298 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx8m/imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h b/arch/arm/include/asm/arch-mx8m/imx-regs.h new file mode 100644 index 0000000000..0c02721df1 --- /dev/null +++ b/arch/arm/include/asm/arch-mx8m/imx-regs.h @@ -0,0 +1,298 @@ +/*

• • Copyright 2017 NXP
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <asm/mach-imx/regs-lcdif.h>

+#ifndef __ASM_ARCH_MX8M_REGS_H__ +#define __ASM_ARCH_MX8M_REGS_H__

+#define M4_BOOTROM_BASE_ADDR 0x007E0000

+#define SAI1_BASE_ADDR 0x30010000 +#define SAI6_BASE_ADDR 0x30030000 +#define SAI5_BASE_ADDR 0x30040000 +#define SAI4_BASE_ADDR 0x30050000 +#define SPBA2_BASE_ADDR 0x300F0000 +#define AIPS1_BASE_ADDR 0x301F0000 +#define GPIO1_BASE_ADDR 0X30200000 +#define GPIO2_BASE_ADDR 0x30210000 +#define GPIO3_BASE_ADDR 0x30220000 +#define GPIO4_BASE_ADDR 0x30230000 +#define GPIO5_BASE_ADDR 0x30240000 +#define ANA_TSENSOR_BASE_ADDR 0x30260000 +#define ANA_OSC_BASE_ADDR 0x30270000 +#define WDOG1_BASE_ADDR 0x30280000 +#define WDOG2_BASE_ADDR 0x30290000 +#define WDOG3_BASE_ADDR 0x302A0000 +#define SDMA2_BASE_ADDR 0x302C0000 +#define GPT1_BASE_ADDR 0x302D0000 +#define GPT2_BASE_ADDR 0x302E0000 +#define GPT3_BASE_ADDR 0x302F0000 +#define ROMCP_BASE_ADDR 0x30310000 +#define LCDIF_BASE_ADDR 0x30320000 +#define IOMUXC_BASE_ADDR 0x30330000 +#define IOMUXC_GPR_BASE_ADDR 0x30340000 +#define OCOTP_BASE_ADDR 0x30350000 +#define ANA_PLL_BASE_ADDR 0x30360000 +#define SNVS_HP_BASE_ADDR 0x30370000 +#define CCM_BASE_ADDR 0x30380000 +#define SRC_BASE_ADDR 0x30390000 +#define GPC_BASE_ADDR 0x303A0000 +#define SEMAPHORE1_BASE_ADDR 0x303B0000 +#define SEMAPHORE2_BASE_ADDR 0x303C0000 +#define RDC_BASE_ADDR 0x303D0000 +#define CSU_BASE_ADDR 0x303E0000

+#define AIPS2_BASE_ADDR 0x305F0000 +#define PWM1_BASE_ADDR 0x30660000 +#define PWM2_BASE_ADDR 0x30670000 +#define PWM3_BASE_ADDR 0x30680000 +#define PWM4_BASE_ADDR 0x30690000 +#define SYSCNT_RD_BASE_ADDR 0x306A0000 +#define SYSCNT_CMP_BASE_ADDR 0x306B0000 +#define SYSCNT_CTRL_BASE_ADDR 0x306C0000 +#define GPT6_BASE_ADDR 0x306E0000 +#define GPT5_BASE_ADDR 0x306F0000 +#define GPT4_BASE_ADDR 0x30700000 +#define PERFMON1_BASE_ADDR 0x307C0000 +#define PERFMON2_BASE_ADDR 0x307D0000 +#define QOSC_BASE_ADDR 0x307F0000

+#define SPDIF1_BASE_ADDR 0x30810000 +#define ECSPI1_BASE_ADDR 0x30820000 +#define ECSPI2_BASE_ADDR 0x30830000 +#define ECSPI3_BASE_ADDR 0x30840000 +#define UART1_BASE_ADDR 0x30860000 +#define UART3_BASE_ADDR 0x30880000 +#define UART2_BASE_ADDR 0x30890000 +#define SPDIF2_BASE_ADDR 0x308A0000 +#define SAI2_BASE_ADDR 0x308B0000 +#define SAI3_BASE_ADDR 0x308C0000 +#define SPBA1_BASE_ADDR 0x308F0000 +#define CAAM_BASE_ADDR 0x30900000 +#define AIPS3_BASE_ADDR 0x309F0000 +#define MIPI_PHY_BASE_ADDR 0x30A00000 +#define MIPI_DSI_BASE_ADDR 0x30A10000 +#define I2C1_BASE_ADDR 0x30A20000 +#define I2C2_BASE_ADDR 0x30A30000 +#define I2C3_BASE_ADDR 0x30A40000 +#define I2C4_BASE_ADDR 0x30A50000 +#define UART4_BASE_ADDR 0x30A60000 +#define MIPI_CSI_BASE_ADDR 0x30A70000 +#define MIPI_CSI_PHY1_BASE_ADDR 0x30A80000 +#define CSI1_BASE_ADDR 0x30A90000 +#define MU_A_BASE_ADDR 0x30AA0000 +#define MU_B_BASE_ADDR 0x30AB0000 +#define SEMAPHOR_HS_BASE_ADDR 0x30AC0000 +#define USDHC1_BASE_ADDR 0x30B40000 +#define USDHC2_BASE_ADDR 0x30B50000 +#define MIPI_CS2_BASE_ADDR 0x30B60000 +#define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000 +#define CSI2_BASE_ADDR 0x30B80000 +#define QSPI0_BASE_ADDR 0x30BB0000 +#define QSPI0_AMBA_BASE 0x08000000 +#define SDMA1_BASE_ADDR 0x30BD0000 +#define ENET1_BASE_ADDR 0x30BE0000

+#define HDMI_CTRL_BASE_ADDR 0x32C00000 +#define AIPS4_BASE_ADDR 0x32DF0000 +#define DC1_BASE_ADDR 0x32E00000 +#define DC2_BASE_ADDR 0x32E10000 +#define DC3_BASE_ADDR 0x32E20000 +#define HDMI_SEC_BASE_ADDR 0x32E40000 +#define TZASC_BASE_ADDR 0x32F80000 +#define MTR_BASE_ADDR 0x32FB0000 +#define PLATFORM_CTRL_BASE_ADDR 0x32FE0000

+#define MXS_APBH_BASE 0x33000000 +#define MXS_GPMI_BASE 0x33002000 +#define MXS_BCH_BASE 0x33004000

+#define USB1_BASE_ADDR 0x38100000 +#define USB2_BASE_ADDR 0x38200000 +#define USB1_PHY_BASE_ADDR 0x381F0000 +#define USB2_PHY_BASE_ADDR 0x382F0000

+#define IOMUXC_GPR0 (IOMUXC_GPR_BASE_ADDR + 0x00) +#define IOMUXC_GPR1 (IOMUXC_GPR_BASE_ADDR + 0x04) +#define IOMUXC_GPR2 (IOMUXC_GPR_BASE_ADDR + 0x08) +#define IOMUXC_GPR3 (IOMUXC_GPR_BASE_ADDR + 0x0c) +#define IOMUXC_GPR4 (IOMUXC_GPR_BASE_ADDR + 0x10) +#define IOMUXC_GPR5 (IOMUXC_GPR_BASE_ADDR + 0x14) +#define IOMUXC_GPR6 (IOMUXC_GPR_BASE_ADDR + 0x18) +#define IOMUXC_GPR7 (IOMUXC_GPR_BASE_ADDR + 0x1c) +#define IOMUXC_GPR8 (IOMUXC_GPR_BASE_ADDR + 0x20) +#define IOMUXC_GPR9 (IOMUXC_GPR_BASE_ADDR + 0x24) +#define IOMUXC_GPR10 (IOMUXC_GPR_BASE_ADDR + 0x28)

We have only structures in u-boot and not defines + offset. This (and this is an issue in all these patches) must be converted in a structure, exactly as we have with i.MX6.

Please note that due to missing documentation, I cannot deeper check.

I recalled that there is a discussion in maillist about using structure or address. I followed linux kernel style to use address here.

Since structure is prefered, I'll refine the code.

Right. There were long discussions in the ML and it was decided to diverge from kernel and use structures in U-Boot. I do not want to restart that painly discussion...:-)

Best regards, Stefano

...

...

+#define GPR_TZASC_EN (1 << 0) +#define GPR_TZASC_EN_LOCK (1 << 16)

+#define SCTR_BASE_ADDR 0x306C0000 +#define CNTCR_OFF 0x00 +#define CNTFID0_OFF 0x20 +#define CNTFID1_OFF 0x24

Ditto, they are offsets (at leastI interprete it), and it should be converted.

Ok.

...

...

+#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9)

+#define SRC_SCR_M4_ENABLE_OFFSET 3 +#define SRC_SCR_M4_ENABLE_MASK (1 << 3) +#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0 +#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 0)

+#define MXS_LCDIF_BASE LCDIF_BASE_ADDR

+#define SRC_IPS_BASE_ADDR 0x30390000 +#define SRC_DDRC_RCR_ADDR 0x30391000 +#define SRC_DDRC2_RCR_ADDR 0x30391004

+#define DDR_CSD1_BASE_ADDR 0x40000000

+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))

I see there is the same in i.MX6, but __KERNEL_STRICT_NAMES is not used in U-Boot and can be dropped.

Ok.

...

...

+#include <asm/types.h> +struct ocotp_regs {

• u32 ctrl;
• u32 ctrl_set;
• u32 ctrl_clr;
• u32 ctrl_tog;
• u32 timing;
• u32 rsvd0[3];
• u32 data;
• u32 rsvd1[3];
• u32 read_ctrl;
• u32 rsvd2[3];
• u32 read_fuse_data;
• u32 rsvd3[3];
• u32 sw_sticky;
• u32 rsvd4[3];
• u32 scs;
• u32 scs_set;
• u32 scs_clr;
• u32 scs_tog;
• u32 crc_addr;
• u32 rsvd5[3];
• u32 crc_value;
• u32 rsvd6[3];
• u32 version;
• u32 rsvd7[0xdb];
• /* fuse banks */
• struct fuse_bank {

• u32	fuse_regs[0x10];
  

• } bank[0];

+};

ok, so it is compatible with i.MX6

...

+struct fuse_bank0_regs {

• u32 lock;
• u32 rsvd0[3];
• u32 uid_low;
• u32 rsvd1[3];
• u32 uid_high;
• u32 rsvd2[7];

+};

+struct fuse_bank1_regs {

• u32 tester3;
• u32 rsvd0[3];
• u32 tester4;
• u32 rsvd1[3];
• u32 tester5;
• u32 rsvd2[3];
• u32 cfg0;
• u32 rsvd3[3];

+};

+struct fuse_bank9_regs {

• u32 mac_addr0;
• u32 rsvd0[3];
• u32 mac_addr1;
• u32 rsvd1[11];

+};

+/* System Reset Controller (SRC) */ +struct src {

• u32 scr;
• u32 a53rcr;
• u32 a53rcr1;
• u32 m4rcr;
• u32 reserved1[4];
• u32 usbophy1_rcr;
• u32 usbophy2_rcr;
• u32 mipiphy_rcr;
• u32 pciephy_rcr;
• u32 hdmi_rcr;
• u32 disp_rcr;
• u32 reserved2[2];
• u32 gpu_rcr;
• u32 vpu_rcr;
• u32 pcie2_rcr;
• u32 mipiphy1_rcr;
• u32 mipiphy2_rcr;
• u32 reserved3;
• u32 sbmr1;
• u32 srsr;
• u32 reserved4[2];
• u32 sisr;
• u32 simr;
• u32 sbmr2;
• u32 gpr1;
• u32 gpr2;
• u32 gpr3;
• u32 gpr4;
• u32 gpr5;
• u32 gpr6;
• u32 gpr7;
• u32 gpr8;
• u32 gpr9;
• u32 gpr10;
• u32 reserved5[985];
• u32 ddr1_rcr;
• u32 ddr2_rcr;

+};

+struct wdog_regs {

• u16 wcr; /* Control */
• u16 wsr; /* Service */
• u16 wrsr; /* Reset Status */
• u16 wicr; /* Interrupt Control */
• u16 wmcr; /* Miscellaneous Control */

+};

+/* Boot device type */ +#define BOOT_TYPE_SD 0x1 +#define BOOT_TYPE_MMC 0x2 +#define BOOT_TYPE_NAND 0x3 +#define BOOT_TYPE_QSPI 0x4 +#define BOOT_TYPE_WEIM 0x5 +#define BOOT_TYPE_SPINOR 0x6 +#define BOOT_TYPE_USB 0xF

+#define ROM_SW_INFO_ADDR 0x00000968 +#define ROM_SW_INFO_ADDR_A0 0x000009e8

+struct bootrom_sw_info {

• u8 reserved_1;
• u8 boot_dev_instance;
• u8 boot_dev_type;
• u8 reserved_2;
• u32 core_freq;
• u32 axi_freq;
• u32 ddr_freq;
• u32 tick_freq;
• u32 reserved_3[3];

+};

+#include <stdbool.h> +bool is_usb_boot(void);

...

+#define is_boot_from_usb is_usb_boot +#define disconnect_from_pc(void) \

• clrbits_le32(USB1_BASE_ADDR + 0xc704, (1 << 31));

It is like in i.MX7, but for i.MX7 we have plain macros. If we need real function as is_usb_boot(), we should move the code outside this header - we define in imx-regs.h just the layout of the registers.

Ok.

Thanks, Peng

...

Best regards, Stefano

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================

On Tue, Nov 28, 2017 at 07:14:29PM +0100, Stefano Babic wrote:

On 28/11/2017 13:31, Peng Fan wrote:

...

Add clock driver to support i.MX8M.

There are two kind PLLs, FRAC pll and SSCG pll. ROM already configured SYS PLL1/2, we only need to configure the output. ocotp/i2c/pll decoding and configuration/usdhc/lcdif/dram pll/ enet clock are configured in the code.

Signed-off-by: Peng Fan peng.fan@nxp.com

arch/arm/include/asm/arch-mx8m/clock.h | 864 +++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx8m/Makefile | 7 + arch/arm/mach-imx/mx8m/clock.c | 782 +++++++++++++++++++++++++++++ arch/arm/mach-imx/mx8m/clock_slice.c | 820 +++++++++++++++++++++++++++++++ 4 files changed, 2473 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx8m/clock.h create mode 100644 arch/arm/mach-imx/mx8m/Makefile create mode 100644 arch/arm/mach-imx/mx8m/clock.c create mode 100644 arch/arm/mach-imx/mx8m/clock_slice.c

diff --git a/arch/arm/include/asm/arch-mx8m/clock.h b/arch/arm/include/asm/arch-mx8m/clock.h new file mode 100644 index 0000000000..a64dbaa57a --- /dev/null +++ b/arch/arm/include/asm/arch-mx8m/clock.h @@ -0,0 +1,864 @@ +/*

• • Copyright 2017 NXP
• • Peng Fan peng.fan@nxp.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef _ASM_ARCH_IMX8M_CLOCK_H +#define _ASM_ARCH_IMX8M_CLOCK_H

+#include <linux/bitops.h>

+enum pll_clocks {

• ANATOP_ARM_PLL,
• ANATOP_GPU_PLL,
• ANATOP_SYSTEM_PLL1,
• ANATOP_SYSTEM_PLL2,
• ANATOP_SYSTEM_PLL3,
• ANATOP_AUDIO_PLL1,
• ANATOP_AUDIO_PLL2,
• ANATOP_VIDEO_PLL1,
• ANATOP_VIDEO_PLL2,
• ANATOP_DRAM_PLL,

+};

+enum clk_slice_type {

• CORE_CLOCK_SLICE,
• BUS_CLOCK_SLICE,
• IP_CLOCK_SLICE,
• AHB_CLOCK_SLICE,
• IPG_CLOCK_SLICE,
• CORE_SEL_CLOCK_SLICE,
• DRAM_SEL_CLOCK_SLICE,

+};

+enum clk_root_index {

• MXC_ARM_CLK = 0,
• ARM_A53_CLK_ROOT = 0,
• ARM_M4_CLK_ROOT = 1,
• VPU_A53_CLK_ROOT = 2,
• GPU_CORE_CLK_ROOT = 3,
• GPU_SHADER_CLK_ROOT = 4,
• MAIN_AXI_CLK_ROOT = 16,
• ENET_AXI_CLK_ROOT = 17,
• NAND_USDHC_BUS_CLK_ROOT = 18,
• VPU_BUS_CLK_ROOT = 19,
• DISPLAY_AXI_CLK_ROOT = 20,
• DISPLAY_APB_CLK_ROOT = 21,
• DISPLAY_RTRM_CLK_ROOT = 22,
• USB_BUS_CLK_ROOT = 23,
• GPU_AXI_CLK_ROOT = 24,
• GPU_AHB_CLK_ROOT = 25,
• NOC_CLK_ROOT = 26,
• NOC_APB_CLK_ROOT = 27,
• AHB_CLK_ROOT = 32,
• IPG_CLK_ROOT = 33,
• MXC_IPG_CLK = 33,
• AUDIO_AHB_CLK_ROOT = 34,
• MIPI_DSI_ESC_RX_CLK_ROOT = 36,
• DRAM_SEL_CFG = 48,
• CORE_SEL_CFG = 49,
• DRAM_ALT_CLK_ROOT = 64,
• DRAM_APB_CLK_ROOT = 65,
• VPU_G1_CLK_ROOT = 66,
• VPU_G2_CLK_ROOT = 67,
• DISPLAY_DTRC_CLK_ROOT = 68,
• DISPLAY_DC8000_CLK_ROOT = 69,
• PCIE1_CTRL_CLK_ROOT = 70,
• PCIE1_PHY_CLK_ROOT = 71,
• PCIE1_AUX_CLK_ROOT = 72,
• DC_PIXEL_CLK_ROOT = 73,
• LCDIF_PIXEL_CLK_ROOT = 74,
• SAI1_CLK_ROOT = 75,
• SAI2_CLK_ROOT = 76,
• SAI3_CLK_ROOT = 77,
• SAI4_CLK_ROOT = 78,
• SAI5_CLK_ROOT = 79,
• SAI6_CLK_ROOT = 80,
• SPDIF1_CLK_ROOT = 81,
• SPDIF2_CLK_ROOT = 82,
• ENET_REF_CLK_ROOT = 83,
• ENET_TIMER_CLK_ROOT = 84,
• ENET_PHY_REF_CLK_ROOT = 85,
• NAND_CLK_ROOT = 86,
• QSPI_CLK_ROOT = 87,
• MXC_ESDHC_CLK = 88,
• USDHC1_CLK_ROOT = 88,
• MXC_ESDHC2_CLK = 89,
• USDHC2_CLK_ROOT = 89,
• I2C1_CLK_ROOT = 90,
• MXC_I2C_CLK = 90,
• I2C2_CLK_ROOT = 91,
• I2C3_CLK_ROOT = 92,
• I2C4_CLK_ROOT = 93,
• UART1_CLK_ROOT = 94,
• UART2_CLK_ROOT = 95,
• UART3_CLK_ROOT = 96,
• UART4_CLK_ROOT = 97,
• USB_CORE_REF_CLK_ROOT = 98,
• USB_PHY_REF_CLK_ROOT = 99,
• GIC_CLK_ROOT = 100,
• ECSPI1_CLK_ROOT = 101,
• ECSPI2_CLK_ROOT = 102,
• PWM1_CLK_ROOT = 103,
• PWM2_CLK_ROOT = 104,
• PWM3_CLK_ROOT = 105,
• PWM4_CLK_ROOT = 106,
• GPT1_CLK_ROOT = 107,
• GPT2_CLK_ROOT = 108,
• GPT3_CLK_ROOT = 109,
• GPT4_CLK_ROOT = 110,
• GPT5_CLK_ROOT = 111,
• GPT6_CLK_ROOT = 112,
• TRACE_CLK_ROOT = 113,
• WDOG_CLK_ROOT = 114,
• WRCLK_CLK_ROOT = 115,
• IPP_DO_CLKO1 = 116,
• IPP_DO_CLKO2 = 117,
• MIPI_DSI_CORE_CLK_ROOT = 118,
• MIPI_DSI_PHY_REF_CLK_ROOT = 119,
• MIPI_DSI_DBI_CLK_ROOT = 120,
• OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
• MIPI_CSI1_CORE_CLK_ROOT = 122,
• MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
• MIPI_CSI1_ESC_CLK_ROOT = 124,
• MIPI_CSI2_CORE_CLK_ROOT = 125,
• MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
• MIPI_CSI2_ESC_CLK_ROOT = 127,
• PCIE2_CTRL_CLK_ROOT = 128,
• PCIE2_PHY_CLK_ROOT = 129,
• PCIE2_AUX_CLK_ROOT = 130,
• ECSPI3_CLK_ROOT = 131,
• OLD_MIPI_DSI_ESC_RX_ROOT = 132,
• DISPLAY_HDMI_CLK_ROOT = 133,
• CLK_ROOT_MAX,

+};

+enum clk_root_src {

• OSC_25M_CLK,
• ARM_PLL_CLK,
• DRAM_PLL1_CLK,
• VIDEO_PLL2_CLK,
• VPU_PLL_CLK,
• GPU_PLL_CLK,
• SYSTEM_PLL1_800M_CLK,
• SYSTEM_PLL1_400M_CLK,
• SYSTEM_PLL1_266M_CLK,
• SYSTEM_PLL1_200M_CLK,
• SYSTEM_PLL1_160M_CLK,
• SYSTEM_PLL1_133M_CLK,
• SYSTEM_PLL1_100M_CLK,
• SYSTEM_PLL1_80M_CLK,
• SYSTEM_PLL1_40M_CLK,
• SYSTEM_PLL2_1000M_CLK,
• SYSTEM_PLL2_500M_CLK,
• SYSTEM_PLL2_333M_CLK,
• SYSTEM_PLL2_250M_CLK,
• SYSTEM_PLL2_200M_CLK,
• SYSTEM_PLL2_166M_CLK,
• SYSTEM_PLL2_125M_CLK,
• SYSTEM_PLL2_100M_CLK,
• SYSTEM_PLL2_50M_CLK,
• SYSTEM_PLL3_CLK,
• AUDIO_PLL1_CLK,
• AUDIO_PLL2_CLK,
• VIDEO_PLL_CLK,
• OSC_32K_CLK,
• EXT_CLK_1,
• EXT_CLK_2,
• EXT_CLK_3,
• EXT_CLK_4,
• OSC_27M_CLK,

+};

+/* CCGR index */ +enum clk_ccgr_index {

• CCGR_DVFS = 0,
• CCGR_ANAMIX = 1,
• CCGR_CPU = 2,
• CCGR_CSU = 4,
• CCGR_DRAM1 = 5,
• CCGR_DRAM2_OBSOLETE = 6,
• CCGR_ECSPI1 = 7,
• CCGR_ECSPI2 = 8,
• CCGR_ECSPI3 = 9,
• CCGR_ENET1 = 10,
• CCGR_GPIO1 = 11,
• CCGR_GPIO2 = 12,
• CCGR_GPIO3 = 13,
• CCGR_GPIO4 = 14,
• CCGR_GPIO5 = 15,
• CCGR_GPT1 = 16,
• CCGR_GPT2 = 17,
• CCGR_GPT3 = 18,
• CCGR_GPT4 = 19,
• CCGR_GPT5 = 20,
• CCGR_GPT6 = 21,
• CCGR_HS = 22,
• CCGR_I2C1 = 23,
• CCGR_I2C2 = 24,
• CCGR_I2C3 = 25,
• CCGR_I2C4 = 26,
• CCGR_IOMUX = 27,
• CCGR_IOMUX1 = 28,
• CCGR_IOMUX2 = 29,
• CCGR_IOMUX3 = 30,
• CCGR_IOMUX4 = 31,
• CCGR_M4 = 32,
• CCGR_MU = 33,
• CCGR_OCOTP = 34,
• CCGR_OCRAM = 35,
• CCGR_OCRAM_S = 36,
• CCGR_PCIE = 37,
• CCGR_PERFMON1 = 38,
• CCGR_PERFMON2 = 39,
• CCGR_PWM1 = 40,
• CCGR_PWM2 = 41,
• CCGR_PWM3 = 42,
• CCGR_PWM4 = 43,
• CCGR_QOS = 44,
• CCGR_DISMIX = 45,
• CCGR_MEGAMIX = 46,
• CCGR_QSPI = 47,
• CCGR_RAWNAND = 48,
• CCGR_RDC = 49,
• CCGR_ROM = 50,
• CCGR_SAI1 = 51,
• CCGR_SAI2 = 52,
• CCGR_SAI3 = 53,
• CCGR_SAI4 = 54,
• CCGR_SAI5 = 55,
• CCGR_SAI6 = 56,
• CCGR_SCTR = 57,
• CCGR_SDMA1 = 58,
• CCGR_SDMA2 = 59,
• CCGR_SEC_DEBUG = 60,
• CCGR_SEMA1 = 61,
• CCGR_SEMA2 = 62,
• CCGR_SIM_DISPLAY = 63,
• CCGR_SIM_ENET = 64,
• CCGR_SIM_M = 65,
• CCGR_SIM_MAIN = 66,
• CCGR_SIM_S = 67,
• CCGR_SIM_WAKEUP = 68,
• CCGR_SIM_USB = 69,
• CCGR_SIM_VPU = 70,
• CCGR_SNVS = 71,
• CCGR_TRACE = 72,
• CCGR_UART1 = 73,
• CCGR_UART2 = 74,
• CCGR_UART3 = 75,
• CCGR_UART4 = 76,
• CCGR_USB_CTRL1 = 77,
• CCGR_USB_CTRL2 = 78,
• CCGR_USB_PHY1 = 79,
• CCGR_USB_PHY2 = 80,
• CCGR_USDHC1 = 81,
• CCGR_USDHC2 = 82,
• CCGR_WDOG1 = 83,
• CCGR_WDOG2 = 84,
• CCGR_WDOG3 = 85,
• CCGR_VA53 = 86,
• CCGR_GPU = 87,
• CCGR_HEVC = 88,
• CCGR_AVC = 89,
• CCGR_VP9 = 90,
• CCGR_HEVC_INTER = 91,
• CCGR_GIC = 92,
• CCGR_DISPLAY = 93,
• CCGR_HDMI = 94,
• CCGR_HDMI_PHY = 95,
• CCGR_XTAL = 96,
• CCGR_PLL = 97,
• CCGR_TSENSOR = 98,
• CCGR_VPU_DEC = 99,
• CCGR_PCIE2 = 100,
• CCGR_MIPI_CSI1 = 101,
• CCGR_MIPI_CSI2 = 102,
• CCGR_MAX,

+};

+/* src index */ +enum clk_src_index {

• CLK_SRC_CKIL_SYNC_REQ = 0,
• CLK_SRC_ARM_PLL_EN = 1,
• CLK_SRC_GPU_PLL_EN = 2,
• CLK_SRC_VPU_PLL_EN = 3,
• CLK_SRC_DRAM_PLL_EN = 4,
• CLK_SRC_SYSTEM_PLL1_EN = 5,
• CLK_SRC_SYSTEM_PLL2_EN = 6,
• CLK_SRC_SYSTEM_PLL3_EN = 7,
• CLK_SRC_AUDIO_PLL1_EN = 8,
• CLK_SRC_AUDIO_PLL2_EN = 9,
• CLK_SRC_VIDEO_PLL1_EN = 10,
• CLK_SRC_VIDEO_PLL2_EN = 11,
• CLK_SRC_ARM_PLL = 12,
• CLK_SRC_GPU_PLL = 13,
• CLK_SRC_VPU_PLL = 14,
• CLK_SRC_DRAM_PLL = 15,
• CLK_SRC_SYSTEM_PLL1_800M = 16,
• CLK_SRC_SYSTEM_PLL1_400M = 17,
• CLK_SRC_SYSTEM_PLL1_266M = 18,
• CLK_SRC_SYSTEM_PLL1_200M = 19,
• CLK_SRC_SYSTEM_PLL1_160M = 20,
• CLK_SRC_SYSTEM_PLL1_133M = 21,
• CLK_SRC_SYSTEM_PLL1_100M = 22,
• CLK_SRC_SYSTEM_PLL1_80M = 23,
• CLK_SRC_SYSTEM_PLL1_40M = 24,
• CLK_SRC_SYSTEM_PLL2_1000M = 25,
• CLK_SRC_SYSTEM_PLL2_500M = 26,
• CLK_SRC_SYSTEM_PLL2_333M = 27,
• CLK_SRC_SYSTEM_PLL2_250M = 28,
• CLK_SRC_SYSTEM_PLL2_200M = 29,
• CLK_SRC_SYSTEM_PLL2_166M = 30,
• CLK_SRC_SYSTEM_PLL2_125M = 31,
• CLK_SRC_SYSTEM_PLL2_100M = 32,
• CLK_SRC_SYSTEM_PLL2_50M = 33,
• CLK_SRC_SYSTEM_PLL3 = 34,
• CLK_SRC_AUDIO_PLL1 = 35,
• CLK_SRC_AUDIO_PLL2 = 36,
• CLK_SRC_VIDEO_PLL1 = 37,
• CLK_SRC_VIDEO_PLL2 = 38,
• CLK_SRC_OSC_25M = 39,
• CLK_SRC_OSC_27M = 40,

+};

+enum root_pre_div {

• CLK_ROOT_PRE_DIV1 = 0,
• CLK_ROOT_PRE_DIV2,
• CLK_ROOT_PRE_DIV3,
• CLK_ROOT_PRE_DIV4,
• CLK_ROOT_PRE_DIV5,
• CLK_ROOT_PRE_DIV6,
• CLK_ROOT_PRE_DIV7,
• CLK_ROOT_PRE_DIV8,

+};

+enum root_post_div {

• CLK_ROOT_POST_DIV1 = 0,
• CLK_ROOT_POST_DIV2,
• CLK_ROOT_POST_DIV3,
• CLK_ROOT_POST_DIV4,
• CLK_ROOT_POST_DIV5,
• CLK_ROOT_POST_DIV6,
• CLK_ROOT_POST_DIV7,
• CLK_ROOT_POST_DIV8,
• CLK_ROOT_POST_DIV9,
• CLK_ROOT_POST_DIV10,
• CLK_ROOT_POST_DIV11,
• CLK_ROOT_POST_DIV12,
• CLK_ROOT_POST_DIV13,
• CLK_ROOT_POST_DIV14,
• CLK_ROOT_POST_DIV15,
• CLK_ROOT_POST_DIV16,
• CLK_ROOT_POST_DIV17,
• CLK_ROOT_POST_DIV18,
• CLK_ROOT_POST_DIV19,
• CLK_ROOT_POST_DIV20,
• CLK_ROOT_POST_DIV21,
• CLK_ROOT_POST_DIV22,
• CLK_ROOT_POST_DIV23,
• CLK_ROOT_POST_DIV24,
• CLK_ROOT_POST_DIV25,
• CLK_ROOT_POST_DIV26,
• CLK_ROOT_POST_DIV27,
• CLK_ROOT_POST_DIV28,
• CLK_ROOT_POST_DIV29,
• CLK_ROOT_POST_DIV30,
• CLK_ROOT_POST_DIV31,
• CLK_ROOT_POST_DIV32,
• CLK_ROOT_POST_DIV33,
• CLK_ROOT_POST_DIV34,
• CLK_ROOT_POST_DIV35,
• CLK_ROOT_POST_DIV36,
• CLK_ROOT_POST_DIV37,
• CLK_ROOT_POST_DIV38,
• CLK_ROOT_POST_DIV39,
• CLK_ROOT_POST_DIV40,
• CLK_ROOT_POST_DIV41,
• CLK_ROOT_POST_DIV42,
• CLK_ROOT_POST_DIV43,
• CLK_ROOT_POST_DIV44,
• CLK_ROOT_POST_DIV45,
• CLK_ROOT_POST_DIV46,
• CLK_ROOT_POST_DIV47,
• CLK_ROOT_POST_DIV48,
• CLK_ROOT_POST_DIV49,
• CLK_ROOT_POST_DIV50,
• CLK_ROOT_POST_DIV51,
• CLK_ROOT_POST_DIV52,
• CLK_ROOT_POST_DIV53,
• CLK_ROOT_POST_DIV54,
• CLK_ROOT_POST_DIV55,
• CLK_ROOT_POST_DIV56,
• CLK_ROOT_POST_DIV57,
• CLK_ROOT_POST_DIV58,
• CLK_ROOT_POST_DIV59,
• CLK_ROOT_POST_DIV60,
• CLK_ROOT_POST_DIV61,
• CLK_ROOT_POST_DIV62,
• CLK_ROOT_POST_DIV63,
• CLK_ROOT_POST_DIV64,

+};

+struct clk_root_map {

• enum clk_root_index entry;
• enum clk_slice_type slice_type;
• u32 slice_index;
• u8 src_mux[8];

+};

+/* CORE clock generation: i ranges from 0 to 4 */ +#define CCM_CORE_CLK_ROOT_GEN_TAGET(i) (0x30388000UL + 0x80 * (i) + 0x00) +#define CCM_CORE_CLK_ROOT_GEN_TAGET_SET(i) (0x30388000UL + 0x80 * (i) + 0x04) +#define CCM_CORE_CLK_ROOT_GEN_TAGET_CLR(i) (0x30388000UL + 0x80 * (i) + 0x08) +#define CCM_CORE_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x0c) +#define CCM_CORE_CLK_ROOT_GEN_MISC(i) (0x30388000UL + 0x80 * (i) + 0x10) +#define CCM_CORE_CLK_ROOT_GEN_MISC_SET(i) (0x30388000UL + 0x80 * (i) + 0x14) +#define CCM_CORE_CLK_ROOT_GEN_MISC_CLR(i) (0x30388000UL + 0x80 * (i) + 0x18) +#define CCM_CORE_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x1c) +#define CCM_CORE_CLK_ROOT_GEN_NM_POST(i) (0x30388000UL + 0x80 * (i) + 0x20) +#define CCM_CORE_CLK_ROOT_GEN_NM_POST_SET(i) (0x30388000UL + 0x80 * (i) + 0x24) +#define CCM_CORE_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30388000UL + 0x80 * (i) + 0x28) +#define CCM_CORE_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x2c) +#define CCM_CORE_CLK_ROOT_GEN_NM_PRE(i) (0x30388000UL + 0x80 * (i) + 0x30) +#define CCM_CORE_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30388000UL + 0x80 * (i) + 0x3c) +#define CCM_CORE_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30388000UL + 0x80 * (i) + 0x38) +#define CCM_CORE_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x3c) +#define CCM_CORE_CLK_ROOT_GEN_DB_POST(i) (0x30388000UL + 0x80 * (i) + 0x40) +#define CCM_CORE_CLK_ROOT_GEN_DB_POST_SET(i) (0x30388000UL + 0x80 * (i) + 0x44) +#define CCM_CORE_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30388000UL + 0x80 * (i) + 0x48) +#define CCM_CORE_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30388000UL + 0x80 * (i) + 0x4c) +#define CCM_CORE_CLK_ROOT_GEN_DB_PRE(i) (0x30388000UL + 0x80 * (i) + 0x50) +#define CCM_CORE_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30388000UL + 0x80 * (i) + 0x54) +#define CCM_CORE_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30388000UL + 0x80 * (i) + 0x58) +#define CCM_CORE_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x5c) +#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL(i) (0x30388000UL + 0x80 * (i) + 0x70) +#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30388000UL + 0x80 * (i) + 0x74) +#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30388000UL + 0x80 * (i) + 0x78) +#define CCM_CORE_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30388000UL + 0x80 * (i) + 0x7c)

I can just say that all these macros are quite cryptic - bad things for me is that they look a way to generate the layout of the CCM's register, and again this does not match with the assertion to have strutures instead of plain offsets.

And if I compare clock.h with i.MX6 / i.MX7, the last ones look very clean - here it is quite messy.

ok. I'll clean this. These macros are written according to CCM DoC. Only one place in code uses the macros. I'll clean that piece code and see if i could remove these macros.

...

+/* BUS clock generation: i ranges from 0 to 11 */ +#define CCM_BUS_CLK_ROOT_GEN_TAGET(i) (0x30388800UL + 0x80 * (i) + 0x00) +#define CCM_BUS_CLK_ROOT_GEN_TAGET_SET(i) (0x30388800UL + 0x80 * (i) + 0x04) +#define CCM_BUS_CLK_ROOT_GEN_TAGET_CLR(i) (0x30388800UL + 0x80 * (i) + 0x08) +#define CCM_BUS_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x0c) +#define CCM_BUS_CLK_ROOT_GEN_MISC(i) (0x30388800UL + 0x80 * (i) + 0x10) +#define CCM_BUS_CLK_ROOT_GEN_MISC_SET(i) (0x30388800UL + 0x80 * (i) + 0x14) +#define CCM_BUS_CLK_ROOT_GEN_MISC_CLR(i) (0x30388800UL + 0x80 * (i) + 0x18) +#define CCM_BUS_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x1c) +#define CCM_BUS CLK_ROOT_GEN_NM_POST(i) (0x30388800UL + 0x80 * (i) + 0x20) +#define CCM_BUS_CLK_ROOT_GEN_NM_POST_SET(i) (0x30388800UL + 0x80 * (i) + 0x24) +#define CCM_BUS_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30388800UL + 0x80 * (i) + 0x28) +#define CCM_BUS_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x2c) +#define CCM_BUS_CLK_ROOT_GEN_NM_PRE(i) (0x30388800UL + 0x80 * (i) + 0x30) +#define CCM_BUS_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30388800UL + 0x80 * (i) + 0x3c) +#define CCM_BUS_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30388800UL + 0x80 * (i) + 0x38) +#define CCM_BUS_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x3c) +#define CCM_BUS_CLK_ROOT_GEN_DB_POST(i) (0x30388800UL + 0x80 * (i) + 0x40) +#define CCM_BUS_CLK_ROOT_GEN_DB_POST_SET(i) (0x30388800UL + 0x80 * (i) + 0x44) +#define CCM_BUS_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30388800UL + 0x80 * (i) + 0x48) +#define CCM_BUS_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30388800UL + 0x80 * (i) + 0x4c) +#define CCM_BUS_CLK_ROOT_GEN_DB_PRE(i) (0x30388800UL + 0x80 * (i) + 0x50) +#define CCM_BUS_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30388800UL + 0x80 * (i) + 0x54) +#define CCM_BUS_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30388800UL + 0x80 * (i) + 0x58) +#define CCM_BUS_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x5c) +#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL(i) (0x30388800UL + 0x80 * (i) + 0x70) +#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30388800UL + 0x80 * (i) + 0x74) +#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30388800UL + 0x80 * (i) + 0x78) +#define CCM_BUS_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30388800UL + 0x80 * (i) + 0x7c)

+/* IP clock generation: i ranges from 0 to 77 */ +#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (0x3038a000UL + 0x80 * (i) + 0x00) +#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (0x3038a000UL + 0x80 * (i) + 0x04) +#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x08) +#define CCM_IP_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x0c) +#define CCM_IP_CLK_ROOT_GEN_MISC(i) (0x3038a000UL + 0x80 * (i) + 0x10) +#define CCM_IP_CLK_ROOT_GEN_MISC_SET(i) (0x3038a000UL + 0x80 * (i) + 0x14) +#define CCM_IP_CLK_ROOT_GEN_MISC_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x18) +#define CCM_IP_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x1c) +#define CCM_IP_CLK_ROOT_GEN_NM_POST(i) (0x3038a000UL + 0x80 * (i) + 0x20) +#define CCM_IP_CLK_ROOT_GEN_NM_POST_SET(i) (0x3038a000UL + 0x80 * (i) + 0x24) +#define CCM_IP_CLK_ROOT_GEN_NM_POST_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x28) +#define CCM_IP_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x2c) +#define CCM_IP_CLK_ROOT_GEN_NM_PRE(i) (0x3038a000UL + 0x80 * (i) + 0x30) +#define CCM_IP_CLK_ROOT_GEN_NM_PRE_SET(i) (0x3038a000UL + 0x80 * (i) + 0x3c) +#define CCM_IP_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x38) +#define CCM_IP_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x3c) +#define CCM_IP_CLK_ROOT_GEN_DB_POST(i) (0x3038a000UL + 0x80 * (i) + 0x40) +#define CCM_IP_CLK_ROOT_GEN_DB_POST_SET(i) (0x3038a000UL + 0x80 * (i) + 0x44) +#define CCM_IP_CLK_ROOT_GEN_DB_POST_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x48) +#define CCM_IP_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x3038a000UL + 0x80 * (i) + 0x4c) +#define CCM_IP_CLK_ROOT_GEN_DB_PRE(i) (0x3038a000UL + 0x80 * (i) + 0x50) +#define CCM_IP_CLK_ROOT_GEN_DB_PRE_SET(i) (0x3038a000UL + 0x80 * (i) + 0x54) +#define CCM_IP_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x58) +#define CCM_IP_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x5c) +#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL(i) (0x3038a000UL + 0x80 * (i) + 0x70) +#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x3038a000UL + 0x80 * (i) + 0x74) +#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x3038a000UL + 0x80 * (i) + 0x78) +#define CCM_IP_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x3038a000UL + 0x80 * (i) + 0x7c)

+/* AHB clock generation: i ranges from 0 to 1*/ +#define CCM_AHB_CLK_ROOT_GEN_TAGET(i) (0x30389000UL + 0x80 * (i) + 0x00) +#define CCM_AHB_CLK_ROOT_GEN_TAGET_SET(i) (0x30389000UL + 0x80 * (i) + 0x04) +#define CCM_AHB_CLK_ROOT_GEN_TAGET_CLR(i) (0x30389000UL + 0x80 * (i) + 0x08) +#define CCM_AHB_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x0c) +#define CCM_AHB_CLK_ROOT_GEN_MISC(i) (0x30389000UL + 0x80 * (i) + 0x10) +#define CCM_AHB_CLK_ROOT_GEN_MISC_SET(i) (0x30389000UL + 0x80 * (i) + 0x14) +#define CCM_AHB_CLK_ROOT_GEN_MISC_CLR(i) (0x30389000UL + 0x80 * (i) + 0x18) +#define CCM_AHB_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x1c) +#define CCM_AHB CLK_ROOT_GEN_NM_POST(i) (0x30389000UL + 0x80 * (i) + 0x20) +#define CCM_AHB_CLK_ROOT_GEN_NM_POST_SET(i) (0x30389000UL + 0x80 * (i) + 0x24) +#define CCM_AHB_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30389000UL + 0x80 * (i) + 0x28) +#define CCM_AHB_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x2c) +#define CCM_AHB_CLK_ROOT_GEN_NM_PRE(i) (0x30389000UL + 0x80 * (i) + 0x30) +#define CCM_AHB_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30389000UL + 0x80 * (i) + 0x3c) +#define CCM_AHB_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30389000UL + 0x80 * (i) + 0x38) +#define CCM_AHB_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x3c) +#define CCM_AHB_CLK_ROOT_GEN_DB_POST(i) (0x30389000UL + 0x80 * (i) + 0x40) +#define CCM_AHB_CLK_ROOT_GEN_DB_POST_SET(i) (0x30389000UL + 0x80 * (i) + 0x44) +#define CCM_AHB_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30389000UL + 0x80 * (i) + 0x48) +#define CCM_AHB_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30389000UL + 0x80 * (i) + 0x4c) +#define CCM_AHB_CLK_ROOT_GEN_DB_PRE(i) (0x30389000UL + 0x80 * (i) + 0x50) +#define CCM_AHB_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30389000UL + 0x80 * (i) + 0x54) +#define CCM_AHB_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30389000UL + 0x80 * (i) + 0x58) +#define CCM_AHB_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x5c) +#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL(i) (0x30389000UL + 0x80 * (i) + 0x70) +#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30389000UL + 0x80 * (i) + 0x74) +#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30389000UL + 0x80 * (i) + 0x78) +#define CCM_AHB_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30389000UL + 0x80 * (i) + 0x7c)

+/* IPG clock generation: i ranges from 0 to 1*/ +#define CCM_IPG_CLK_ROOT_GEN_TAGET(i) (0x30389080UL + 0x80 * (i) + 0x00) +#define CCM_IPG_CLK_ROOT_GEN_TAGET_SET(i) (0x30389080UL + 0x80 * (i) + 0x04) +#define CCM_IPG_CLK_ROOT_GEN_TAGET_CLR(i) (0x30389080UL + 0x80 * (i) + 0x08) +#define CCM_IPG_CLK_ROOT_GEN_TAGET_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x0c) +#define CCM_IPG_CLK_ROOT_GEN_MISC(i) (0x30389080UL + 0x80 * (i) + 0x10) +#define CCM_IPG_CLK_ROOT_GEN_MISC_SET(i) (0x30389080UL + 0x80 * (i) + 0x14) +#define CCM_IPG_CLK_ROOT_GEN_MISC_CLR(i) (0x30389080UL + 0x80 * (i) + 0x18) +#define CCM_IPG_CLK_ROOT_GEN_MISC_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x1c) +#define CCM_IPG CLK_ROOT_GEN_NM_POST(i) (0x30389080UL + 0x80 * (i) + 0x20) +#define CCM_IPG_CLK_ROOT_GEN_NM_POST_SET(i) (0x30389080UL + 0x80 * (i) + 0x24) +#define CCM_IPG_CLK_ROOT_GEN_NM_POST_CLR(i) (0x30389080UL + 0x80 * (i) + 0x28) +#define CCM_IPG_CLK_ROOT_GEN_NM_POST_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x2c) +#define CCM_IPG_CLK_ROOT_GEN_NM_PRE(i) (0x30389080UL + 0x80 * (i) + 0x30) +#define CCM_IPG_CLK_ROOT_GEN_NM_PRE_SET(i) (0x30389080UL + 0x80 * (i) + 0x3c) +#define CCM_IPG_CLK_ROOT_GEN_NM_PRE_CLR(i) (0x30389080UL + 0x80 * (i) + 0x38) +#define CCM_IPG_CLK_ROOT_GEN_NM_PRE_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x3c) +#define CCM_IPG_CLK_ROOT_GEN_DB_POST(i) (0x30389080UL + 0x80 * (i) + 0x40) +#define CCM_IPG_CLK_ROOT_GEN_DB_POST_SET(i) (0x30389080UL + 0x80 * (i) + 0x44) +#define CCM_IPG_CLK_ROOT_GEN_DB_POST_CLR(i) (0x30389080UL + 0x80 * (i) + 0x48) +#define CCM_IPG_CLK_ROOT_GEN_DB_POST_TOGGL(i) (0x30389080UL + 0x80 * (i) + 0x4c) +#define CCM_IPG_CLK_ROOT_GEN_DB_PRE(i) (0x30389080UL + 0x80 * (i) + 0x50) +#define CCM_IPG_CLK_ROOT_GEN_DB_PRE_SET(i) (0x30389080UL + 0x80 * (i) + 0x54) +#define CCM_IPG_CLK_ROOT_GEN_DB_PRE_CLR(i) (0x30389080UL + 0x80 * (i) + 0x58) +#define CCM_IPG_CLK_ROOT_GEN_DB_PRE_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x5c) +#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL(i) (0x30389080UL + 0x80 * (i) + 0x70) +#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL_SET(i) (0x30389080UL + 0x80 * (i) + 0x74) +#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL_CLR(i) (0x30389080UL + 0x80 * (i) + 0x78) +#define CCM_IPG_CLK_ROOT_GEN_ACC_CTRL_TOGGLE(i) (0x30389080UL + 0x80 * (i) + 0x7c)

+/* CORE_SEL clock generation */ +#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET (0x30389800UL + 0x00) +#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET_SET (0x30389800UL + 0x04) +#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET_CLR (0x30389800UL + 0x08) +#define CCM_CORE_SEL_CLK_ROOT_GEN_TAGET_TOGGLE (0x30389800UL + 0x0c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC (0x30389800UL + 0x10) +#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC_SET (0x30389800UL + 0x14) +#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC_CLR (0x30389800UL + 0x18) +#define CCM_CORE_SEL_CLK_ROOT_GEN_MISC_TOGGLE (0x30389800UL + 0x1c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST (0x30389800UL + 0x20) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST_SET (0x30389800UL + 0x24) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST_CLR (0x30389800UL + 0x28) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_POST_TOGGLE (0x30389800UL + 0x2c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE (0x30389800UL + 0x30) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE_SET (0x30389800UL + 0x3c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE_CLR (0x30389800UL + 0x38) +#define CCM_CORE_SEL_CLK_ROOT_GEN_NM_PRE_TOGGLE (0x30389800UL + 0x3c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST (0x30389800UL + 0x40) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST_SET (0x30389800UL + 0x44) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST_CLR (0x30389800UL + 0x48) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_POST_TOGGL (0x30389800UL + 0x4c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE (0x30389800UL + 0x50) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE_SET (0x30389800UL + 0x54) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE_CLR (0x30389800UL + 0x58) +#define CCM_CORE_SEL_CLK_ROOT_GEN_DB_PRE_TOGGLE (0x30389800UL + 0x5c) +#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL (0x30389800UL + 0x70) +#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL_SET (0x30389800UL + 0x74) +#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL_CLR (0x30389800UL + 0x78) +#define CCM_CORE_SEL_CLK_ROOT_GEN_ACC_CTRL_TOGGLE (0x30389800UL + 0x7c)

+/* DRAM_SEL clock generation */ +#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET (0x30389880UL + 0x00) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET_SET (0x30389880UL + 0x04) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET_CLR (0x30389880UL + 0x08) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET_TOGGLE (0x30389880UL + 0x0c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC (0x30389880UL + 0x10) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC_SET (0x30389880UL + 0x14) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC_CLR (0x30389880UL + 0x18) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_MISC_TOGGLE (0x30389880UL + 0x1c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST (0x30389880UL + 0x20) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST_SET (0x30389880UL + 0x24) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST_CLR (0x30389880UL + 0x28) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_POST_TOGGLE (0x30389880UL + 0x2c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE (0x30389880UL + 0x30) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE_SET (0x30389880UL + 0x3c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE_CLR (0x30389880UL + 0x38) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_NM_PRE_TOGGLE (0x30389880UL + 0x3c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST (0x30389880UL + 0x40) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST_SET (0x30389880UL + 0x44) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST_CLR (0x30389880UL + 0x48) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_POST_TOGGL (0x30389880UL + 0x4c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE (0x30389880UL + 0x50) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE_SET (0x30389880UL + 0x54) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE_CLR (0x30389880UL + 0x58) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_DB_PRE_TOGGLE (0x30389880UL + 0x5c) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL (0x30389880UL + 0x70) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL_SET (0x30389880UL + 0x74) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL_CLR (0x30389880UL + 0x78) +#define CCM_DRAM_SEL_CLK_ROOT_GEN_ACC_CTRL_TOGGLE (0x30389880UL + 0x7c)

+/* CCGR: i ranges from 0 to 191 */ +#define CCM_CCGR(i) (0x30384000UL + 0x10 * (i) + 0x00) +#define CCM_CCGR_SET(i) (0x30384000UL + 0x10 * (i) + 0x04) +#define CCM_CCGR_CLR(i) (0x30384000UL + 0x10 * (i) + 0x08) +#define CCM_CCGR_TOGGLE(i) (0x30384000UL + 0x10 * (i) + 0x0c)

+/* Source Control: i ranges from 0 to 191 */ +#define CCM_SRC(i) (0x30380800UL + 0x10 * (i) + 0x00) +#define CCM_SRC_SET(i) (0x30380800UL + 0x10 * (i) + 0x04) +#define CCM_SRC_CLR(i) (0x30380800UL + 0x10 * (i) + 0x08) +#define CCM_SRC_TOGGLE(i) (0x30380800UL + 0x10 * (i) + 0x0c)

+/* Observe Control: i ranges from 0 to 7 */ +#define CCM_OBSERVE(i) (0x30380400UL + 0x10 * (i) + 0x00) +#define CCM_OBSERVE_SET(i) (0x30380400UL + 0x10 * (i) + 0x04) +#define CCM_OBSERVE_CLR(i) (0x30380400UL + 0x10 * (i) + 0x08) +#define CCM_OBSERVE_TOGGLE(i) (0x30380400UL + 0x10 * (i) + 0x0c)

+/* Generic Control: i ranges from 0 to 9 */ +#define CCM_GEN(i) (0x30380000UL + 0x10 * (i) + 0x00) +#define CCM_GEN_SET(i) (0x30380000UL + 0x10 * (i) + 0x04) +#define CCM_GEN_CLR(i) (0x30380000UL + 0x10 * (i) + 0x08) +#define CCM_GEN_TOGGLE(i) (0x30380000UL + 0x10 * (i) + 0x0c)

+#define CCGR_CLK_ON_MASK 0x03 +#define CLK_SRC_ON_MASK 0x03

+#define CLK_ROOT_ON BIT(28) +#define CLK_ROOT_OFF (0 << 28) +#define CLK_ROOT_ENABLE_MASK BIT(28) +#define CLK_ROOT_ENABLE_SHIFT 28 +#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)

+/* For SEL, only use 1 bit */ +#define CLK_ROOT_SRC_MUX_MASK 0x07000000 +#define CLK_ROOT_SRC_MUX_SHIFT 24 +#define CLK_ROOT_SRC_0 0x00000000 +#define CLK_ROOT_SRC_1 0x01000000 +#define CLK_ROOT_SRC_2 0x02000000 +#define CLK_ROOT_SRC_3 0x03000000 +#define CLK_ROOT_SRC_4 0x04000000 +#define CLK_ROOT_SRC_5 0x05000000 +#define CLK_ROOT_SRC_6 0x06000000 +#define CLK_ROOT_SRC_7 0x07000000

+#define CLK_ROOT_PRE_DIV_MASK (0x00070000) +#define CLK_ROOT_PRE_DIV_SHIFT 16 +#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)

+#define CLK_ROOT_AUDO_SLOW_EN 0x1000

+#define CLK_ROOT_AUDO_DIV_MASK 0x700 +#define CLK_ROOT_AUDO_DIV_SHIFT 0x8 +#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)

+/* For CORE: mask is 0x7; For IPG: mask is 0x3 */ +#define CLK_ROOT_POST_DIV_MASK 0x3f +#define CLK_ROOT_CORE_POST_DIV_MASK 0x7 +#define CLK_ROOT_IPG_POST_DIV_MASK 0x3 +#define CLK_ROOT_POST_DIV_SHIFT 0 +#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)

+#define AUDIO_PLL1_CFG0_ADDR 0x30360000 +#define AUDIO_PLL1_CFG1_ADDR 0x30360004 +#define AUDIO_PLL2_CFG0_ADDR 0x30360008 +#define AUDIO_PLL2_CFG1_ADDR 0x3036000c +#define VIDEO_PLL_CFG0 0x30360010 +#define VIDEO_PLL_CFG1 0x30360014 +#define GPU_PLL_CFG0 0x30360018 +#define GPU_PLL_CFG1 0x3036001c +#define VPU_PLL_CFG0 0x30360020 +#define VPU_PLL_CFG1 0x30360024 +#define ARM_PLL_CFG0 0x30360028 +#define ARM_PLL_CFG1 0x3036002c +#define SYS_PLL1_CFG0 0x30360030 +#define SYS_PLL1_CFG1 0x30360034 +#define SYS_PLL1_CFG2 0x30360038 +#define SYS_PLL2_CFG0 0x3036003c +#define SYS_PLL2_CFG1 0x30360040 +#define SYS_PLL2_CFG2 0x30360044 +#define SYS_PLL3_CFG0 0x30360048 +#define SYS_PLL3_CFG1 0x3036004c +#define SYS_PLL3_CFG2 0x30360050 +#define VIDEO_PLL2_CFG0 0x30360054 +#define VIDEO_PLL2_CFG1 0x30360058 +#define VIDEO_PLL2_CFG2 0x3036005c +#define DRAM_PLL_CFG0 0x30360060 +#define DRAM_PLL_CFG1 0x30360064 +#define DRAM_PLL_CFG2 0x30360068 +#define DIGPROG 0x3036006c +#define OSC_MISC_CFG 0x30360070 +#define PLLOUT_MONITOR_CFG 0x30360074 +#define FRAC_PLLOUT_DIV_CFG 0x30360078 +#define SSCG_PLLOUT_DIV_CFG 0x3036007c

+/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/ +#define FRAC_PLL_LOCK_MASK BIT(31) +#define FRAC_PLL_CLKE_MASK BIT(21) +#define FRAC_PLL_PD_MASK BIT(19) +#define FRAC_PLL_REFCLK_SEL_MASK BIT(16) +#define FRAC_PLL_LOCK_SEL_MASK BIT(15) +#define FRAC_PLL_BYPASS_MASK BIT(14) +#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13) +#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12) +#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11) +#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5)) +#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5) +#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5 +#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f +#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)

+#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16) +#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16) +#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) +#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)

+#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7) +#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7 +#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f +#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)

+/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */ +#define SSCG_PLL_LOCK_MASK BIT(31) +#define SSCG_PLL_CLKE_MASK BIT(25) +#define SSCG_PLL_DIV2_CLKE_MASK BIT(23) +#define SSCG_PLL_DIV3_CLKE_MASK BIT(21) +#define SSCG_PLL_DIV4_CLKE_MASK BIT(19) +#define SSCG_PLL_DIV5_CLKE_MASK BIT(17) +#define SSCG_PLL_DIV6_CLKE_MASK BIT(15) +#define SSCG_PLL_DIV8_CLKE_MASK BIT(13) +#define SSCG_PLL_DIV10_CLKE_MASK BIT(11) +#define SSCG_PLL_DIV20_CLKE_MASK BIT(9) +#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9) +#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9) +#define SSCG_PLL_PLL3_CLKE_MASK BIT(9) +#define SSCG_PLL_PD_MASK BIT(7) +#define SSCG_PLL_BYPASS1_MASK BIT(5) +#define SSCG_PLL_BYPASS2_MASK BIT(4) +#define SSCG_PLL_LOCK_SEL_MASK BIT(3) +#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) +#define SSCG_PLL_REFCLK_SEL_MASK 0x3 +#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) +#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) +#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) +#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)

+#define SSCG_PLL_SSDS_MASK BIT(8) +#define SSCG_PLL_SSMD_MASK (0x7 << 5) +#define SSCG_PLL_SSMF_MASK (0xf << 1) +#define SSCG_PLL_SSE_MASK 0x1

+#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) +#define SSCG_PLL_REF_DIVR1_SHIFT 25 +#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK) +#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) +#define SSCG_PLL_REF_DIVR2_SHIFT 19 +#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK) +#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13) +#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13 +#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \

• 			 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
  

+#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7) +#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7 +#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \

• 			 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
  

+#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) +#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1 +#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \

• 			 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
  

+#define SSCG_PLL_FILTER_RANGE_MASK 0x1

+#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16) +#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8) +#define HW_DIGPROG_MINOR_MASK 0xff

+#define HW_OSC_27M_CLKE_MASK BIT(4) +#define HW_OSC_25M_CLKE_MASK BIT(2) +#define HW_OSC_32K_SEL_MASK 0x1 +#define HW_OSC_32K_SEL_RTC 0x1 +#define HW_OSC_32K_SEL_25M_DIV800 0x0

+#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20) +#define HW_FRAC_ARM_PLL_DIV_SHIFT 20 +#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16) +#define HW_FRAC_VPU_PLL_DIV_SHIFT 16 +#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12) +#define HW_FRAC_GPU_PLL_DIV_SHIFT 12 +#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10) +#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10 +#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4) +#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4 +#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7 +#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0

+#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16) +#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16 +#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14) +#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14 +#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8) +#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8 +#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4) +#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4 +#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7 +#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0

+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 +#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000 +#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000

+enum enet_freq {

• ENET_25MHZ = 0,
• ENET_50MHZ,
• ENET_125MHZ,

+};

+u32 imx_get_fecclk(void); +u32 imx_get_uartclk(void); +int clock_init(void); +unsigned int mxc_get_clock(enum clk_root_index clk); +int clock_enable(enum clk_ccgr_index index, bool enable); +int clock_root_enabled(enum clk_root_index clock_id); +int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,

•    enum root_post_div post_div, enum clk_root_src clock_src);
  

+int clock_set_target_val(enum clk_root_index clock_id, u32 val); +int clock_get_target_val(enum clk_root_index clock_id, u32 *val); +int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); +int clock_get_postdiv(enum clk_root_index clock_id,

•       enum root_post_div *post_div);
  

+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); +void mxs_set_lcdclk(u32 base_addr, u32 freq); +int set_clk_qspi(void); +void enable_ocotp_clk(unsigned char enable); +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); +#ifdef CONFIG_FEC_MXC +int set_clk_enet(enum enet_freq type); +#endif +void hab_caam_clock_enable(unsigned char enable); +#endif diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/mx8m/Makefile new file mode 100644 index 0000000000..05f38842f0 --- /dev/null +++ b/arch/arm/mach-imx/mx8m/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y += clock.o clock_slice.o diff --git a/arch/arm/mach-imx/mx8m/clock.c b/arch/arm/mach-imx/mx8m/clock.c new file mode 100644 index 0000000000..1d874ae8bf --- /dev/null +++ b/arch/arm/mach-imx/mx8m/clock.c @@ -0,0 +1,782 @@ +/*

• • Copyright 2017 NXP
• • Peng Fan peng.fan@nxp.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/arch/sys_proto.h>

+DECLARE_GLOBAL_DATA_PTR;

General remark: I am missing here what we need to export and what we don't, because you are not adding static to the functions. Can you check which functions are really exported and set the rest as static ?

...

+#ifdef CONFIG_SECURE_BOOT +void hab_caam_clock_enable(unsigned char enable)

                             ^-- this generates at least a warning

...

+{

• /* The CAAM clock is always on for iMX8M */

+} +#endif

+#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable) +{

• clock_enable(CCGR_OCOTP, !!enable);

+} +#endif

+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) +{

• /* 0 - 3 is valid i2c num */
• if (i2c_num > 3)

• return -EINVAL;
  

• clock_enable(CCGR_I2C1 + i2c_num, !!enable);
• return 0;

+}

+u32 decode_frac_pll(enum clk_root_src frac_pll) +{

• u32 pll_cfg0, pll_cfg1, pllout;
• u32 pll_refclk_sel, pll_refclk;
• u32 divr_val, divq_val, divf_val, divff, divfi;
• u32 pllout_div_shift, pllout_div_mask, pllout_div;
• switch (frac_pll) {
• case ARM_PLL_CLK:

• pll_cfg0 = readl((void __iomem *)ARM_PLL_CFG0);
  

• pll_cfg1 = readl((void __iomem *)ARM_PLL_CFG1);
  

• pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
  

• pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
  

• break;
  

• default:

• printf("Not supported\n");
  

• return 0;
  

• }
• pllout_div = readl((void __iomem *)FRAC_PLLOUT_DIV_CFG);
• pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
• /* Power down */
• if (pll_cfg0 & FRAC_PLL_PD_MASK)

• return 0;
  

• /* output not enabled */
• if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)

• return 0;
  

• pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
• if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)

• pll_refclk = 25000000u;
  

• else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)

• pll_refclk = 27000000u;
  

• else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)

• pll_refclk = 27000000u;
  

• else

• pll_refclk = 0;
  

• if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)

• return pll_refclk;
  

• divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>

• FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
  

• divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
• divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>

• FRAC_PLL_FRAC_DIV_CTL_SHIFT;
  

• divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
• divf_val = 1 + divfi + divff / (1 << 24);
• pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /

• ((divq_val + 1) * 2);
  

• return pllout / (pllout_div + 1);

+}

+u32 decode_sscg_pll(enum clk_root_src sscg_pll) +{

• u32 pll_cfg0, pll_cfg1, pll_cfg2;
• u32 pll_refclk_sel, pll_refclk;
• u32 divr1, divr2, divf1, divf2, divq, div;
• u32 sse;
• u32 pll_clke;
• u32 pllout_div_shift, pllout_div_mask, pllout_div;
• u32 pllout;
• switch (sscg_pll) {
• case SYSTEM_PLL1_800M_CLK:
• case SYSTEM_PLL1_400M_CLK:
• case SYSTEM_PLL1_266M_CLK:
• case SYSTEM_PLL1_200M_CLK:
• case SYSTEM_PLL1_160M_CLK:
• case SYSTEM_PLL1_133M_CLK:
• case SYSTEM_PLL1_100M_CLK:
• case SYSTEM_PLL1_80M_CLK:
• case SYSTEM_PLL1_40M_CLK:

• pll_cfg0 = readl((void __iomem *)SYS_PLL1_CFG0);
  

• pll_cfg1 = readl((void __iomem *)SYS_PLL1_CFG1);
  

• pll_cfg2 = readl((void __iomem *)SYS_PLL1_CFG2);
  

• pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
  

• pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
  

• break;
  

• case SYSTEM_PLL2_1000M_CLK:
• case SYSTEM_PLL2_500M_CLK:
• case SYSTEM_PLL2_333M_CLK:
• case SYSTEM_PLL2_250M_CLK:
• case SYSTEM_PLL2_200M_CLK:
• case SYSTEM_PLL2_166M_CLK:
• case SYSTEM_PLL2_125M_CLK:
• case SYSTEM_PLL2_100M_CLK:
• case SYSTEM_PLL2_50M_CLK:

• pll_cfg0 = readl((void __iomem *)SYS_PLL2_CFG0);
  

• pll_cfg1 = readl((void __iomem *)SYS_PLL2_CFG1);
  

• pll_cfg2 = readl((void __iomem *)SYS_PLL2_CFG2);
  

• pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
  

• pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
  

• break;
  

• case SYSTEM_PLL3_CLK:

• pll_cfg0 = readl((void __iomem *)SYS_PLL3_CFG0);
  

• pll_cfg1 = readl((void __iomem *)SYS_PLL3_CFG1);
  

• pll_cfg2 = readl((void __iomem *)SYS_PLL3_CFG2);
  

• pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
  

• pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
  

• break;
  

• case DRAM_PLL1_CLK:

• pll_cfg0 = readl((void __iomem *)DRAM_PLL_CFG0);
  

• pll_cfg1 = readl((void __iomem *)DRAM_PLL_CFG1);
  

• pll_cfg2 = readl((void __iomem *)DRAM_PLL_CFG2);
  

• pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
  

• pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
  

• break;
  

• default:

• printf("Not supported\n");
  

• return 0;
  

• }
• switch (sscg_pll) {
• case DRAM_PLL1_CLK:

• pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
  

• div = 1;
  

• break;
  

• case SYSTEM_PLL3_CLK:

• pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
  

• div = 1;
  

• break;
  

• case SYSTEM_PLL2_1000M_CLK:
• case SYSTEM_PLL1_800M_CLK:

• pll_clke = SSCG_PLL_CLKE_MASK;
  

• div = 1;
  

• break;
  

• case SYSTEM_PLL2_500M_CLK:
• case SYSTEM_PLL1_400M_CLK:

• pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
  

• div = 2;
  

• break;
  

• case SYSTEM_PLL2_333M_CLK:
• case SYSTEM_PLL1_266M_CLK:

• pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
  

• div = 3;
  

• break;
  

• case SYSTEM_PLL2_250M_CLK:
• case SYSTEM_PLL1_200M_CLK:

• pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
  

• div = 4;
  

• break;
  

• case SYSTEM_PLL2_200M_CLK:
• case SYSTEM_PLL1_160M_CLK:

• pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
  

• div = 5;
  

• break;
  

• case SYSTEM_PLL2_166M_CLK:
• case SYSTEM_PLL1_133M_CLK:

• pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
  

• div = 6;
  

• break;
  

• case SYSTEM_PLL2_125M_CLK:
• case SYSTEM_PLL1_100M_CLK:

• pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
  

• div = 8;
  

• break;
  

• case SYSTEM_PLL2_100M_CLK:
• case SYSTEM_PLL1_80M_CLK:

• pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
  

• div = 10;
  

• break;
  

• case SYSTEM_PLL2_50M_CLK:
• case SYSTEM_PLL1_40M_CLK:

• pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
  

• div = 20;
  

• break;
  

• default:

• printf("Not supported\n");
  

• return 0;
  

• }
• /* Power down */
• if (pll_cfg0 & SSCG_PLL_PD_MASK)

• return 0;
  

• /* output not enabled */
• if ((pll_cfg0 & pll_clke) == 0)

• return 0;
  

• pllout_div = readl((void __iomem *)SSCG_PLLOUT_DIV_CFG);
• pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
• pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
• if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)

• pll_refclk = 25000000u;
  

• else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)

• pll_refclk = 27000000u;
  

• else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)

• pll_refclk = 27000000u;
  

• else

• pll_refclk = 0;
  

• /* We assume bypass1/2 are the same value */
• if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||

•    (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
  

• return pll_refclk;
  

• divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>

• SSCG_PLL_REF_DIVR1_SHIFT;
  

• divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>

• SSCG_PLL_REF_DIVR2_SHIFT;
  

• divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>

• SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
  

• divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>

• SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
  

• divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>

• SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
  

• sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
• if (sse)

• sse = 8;
  

• else

• sse = 2;
  

• pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /

• (divr2 + 1) * (divf2 + 1) / (divq + 1);
  

• return pllout / (pllout_div + 1) / div;

+}

I cannot help with these function without manual :-(

...

+u32 get_root_src_clk(enum clk_root_src root_src) +{

• switch (root_src) {
• case OSC_25M_CLK:

• return 25000000u;
  

• case OSC_27M_CLK:

• return 25000000u;
  

• case OSC_32K_CLK:

• return 32000u;
  

• case ARM_PLL_CLK:

• return decode_frac_pll(root_src);
  

• case SYSTEM_PLL1_800M_CLK:
• case SYSTEM_PLL1_400M_CLK:
• case SYSTEM_PLL1_266M_CLK:
• case SYSTEM_PLL1_200M_CLK:
• case SYSTEM_PLL1_160M_CLK:
• case SYSTEM_PLL1_133M_CLK:
• case SYSTEM_PLL1_100M_CLK:
• case SYSTEM_PLL1_80M_CLK:
• case SYSTEM_PLL1_40M_CLK:
• case SYSTEM_PLL2_1000M_CLK:
• case SYSTEM_PLL2_500M_CLK:
• case SYSTEM_PLL2_333M_CLK:
• case SYSTEM_PLL2_250M_CLK:
• case SYSTEM_PLL2_200M_CLK:
• case SYSTEM_PLL2_166M_CLK:
• case SYSTEM_PLL2_125M_CLK:
• case SYSTEM_PLL2_100M_CLK:
• case SYSTEM_PLL2_50M_CLK:
• case SYSTEM_PLL3_CLK:

• return decode_sscg_pll(root_src);
  

• default:

• return 0;
  

• }
• return 0;

+}

+u32 get_root_clk(enum clk_root_index clock_id) +{

• enum clk_root_src root_src;
• u32 post_podf, pre_podf, root_src_clk;
• if (clock_root_enabled(clock_id) <= 0)

• return 0;
  

• if (clock_get_prediv(clock_id, &pre_podf) < 0)

• return 0;
  

• if (clock_get_postdiv(clock_id, &post_podf) < 0)

• return 0;
  

• if (clock_get_src(clock_id, &root_src) < 0)

• return 0;
  

• root_src_clk = get_root_src_clk(root_src);
• return root_src_clk / (post_podf + 1) / (pre_podf + 1);

+}

+unsigned int mxc_get_clock(enum clk_root_index clk) +{

• u32 val;
• if (clk >= CLK_ROOT_MAX)

• return 0;
  

• if (clk == MXC_ARM_CLK)

• return get_root_clk(ARM_A53_CLK_ROOT);
  

• if (clk == MXC_IPG_CLK) {

• clock_get_target_val(IPG_CLK_ROOT, &val);
  

• val = val & 0x3;
  

• return get_root_clk(AHB_CLK_ROOT) / (val + 1);
  

• }
• return get_root_clk(clk);

+}

+u32 imx_get_uartclk(void) +{

• return mxc_get_clock(UART1_CLK_ROOT);

+}

+enum frac_pll_out_val {

• FRAC_PLL_OUT_1000M,
• FRAC_PLL_OUT_1600M,

+};

+int frac_pll_init(u32 pll, enum frac_pll_out_val val) +{

• void __iomem *pll_cfg0, __iomem *pll_cfg1;
• u32 val_cfg0, val_cfg1;
• switch (pll) {
• case ANATOP_ARM_PLL:

• pll_cfg0 = (void * __iomem)ARM_PLL_CFG0;
  

• pll_cfg1 = (void * __iomem)ARM_PLL_CFG1;
  

• if (val == FRAC_PLL_OUT_1000M)
  

• 	val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
  

• else
  

• 	val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
  

• val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
  

• 	FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
  

• 	FRAC_PLL_REFCLK_DIV_VAL(4) |
  

• 	FRAC_PLL_OUTPUT_DIV_VAL(0);
  

• break;
  

• default:

• return -1;
  

• }
• /* bypass the clock */
• writel(readl(pll_cfg0) | FRAC_PLL_BYPASS_MASK, pll_cfg0);
• /* Set the value */
• writel(val_cfg1, pll_cfg1);
• writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);

...

• val_cfg0 = readl(pll_cfg0);
• /* unbypass the clock */
• writel(val_cfg0 & ~FRAC_PLL_BYPASS_MASK, pll_cfg0);
• while (!(readl(pll_cfg0) & FRAC_PLL_LOCK_MASK))

• ;
  

• clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);

It is quite inconsistent how accessors are used. Some lines above you use "writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0)", here clrbits_32. I would suggest you switch to [clr|set]bits_ accessors when you have just to toggle bits inside a register. That also for lines as :

writel(readl(pll_cfg0) | FRAC_PLL_BYPASS_MASK, pll_cfg0);

ok. I'll refine the code make it consistent.

...

• return 0;

+}

+int sscg_pll_init(u32 pll) +{

• void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
• u32 val_cfg0, val_cfg1, val_cfg2;
• u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
• switch (pll) {
• case ANATOP_SYSTEM_PLL1:

• pll_cfg0 = (void * __iomem)SYS_PLL1_CFG0;
  

• pll_cfg1 = (void * __iomem)SYS_PLL1_CFG1;
  

• pll_cfg2 = (void * __iomem)SYS_PLL1_CFG2;
  

• /* 800MHz */
  

• val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
  

• 	SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
  

• val_cfg1 = 0;
  

• val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
  

• 	SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
  

• 	SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
  

• 	SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
  

• 	SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
  

• 	SSCG_PLL_REFCLK_SEL_OSC_25M;
  

• break;
  

• case ANATOP_SYSTEM_PLL2:

• pll_cfg0 = (void * __iomem)SYS_PLL2_CFG0;
  

• pll_cfg1 = (void * __iomem)SYS_PLL2_CFG1;
  

• pll_cfg2 = (void * __iomem)SYS_PLL2_CFG2;
  

• /* 1000MHz */
  

• val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
  

• 	SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
  

• val_cfg1 = 0;
  

• val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
  

• 	SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
  

• 	SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
  

• 	SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
  

• 	SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
  

• 	SSCG_PLL_REFCLK_SEL_OSC_25M;
  

• break;
  

• case ANATOP_SYSTEM_PLL3:

• pll_cfg0 = (void * __iomem)SYS_PLL3_CFG0;
  

• pll_cfg1 = (void * __iomem)SYS_PLL3_CFG1;
  

• pll_cfg2 = (void * __iomem)SYS_PLL3_CFG2;
  

• /* 800MHz */
  

• val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
  

• 	SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
  

• val_cfg1 = 0;
  

• val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK |  SSCG_PLL_LOCK_SEL_MASK |
  

• 	SSCG_PLL_REFCLK_SEL_OSC_25M;
  

• break;
  

• default:

• return -1;
  

• }
• /*bypass*/
• writel(readl(pll_cfg0) | bypass1_mask | bypass2_mask, pll_cfg0);
• /* set value */
• writel(val_cfg2, pll_cfg2);
• writel(val_cfg1, pll_cfg1);
• /*unbypass1 and wait 70us */
• writel(val_cfg0 | bypass2_mask, pll_cfg1);
• __udelay(70);
• /* unbypass2 and wait lock */
• writel(val_cfg0, pll_cfg1);
• while (!(readl(pll_cfg0) & SSCG_PLL_LOCK_MASK))

• ;
  

• return 0;

+}

+void mxs_set_lcdclk(u32 base_addr, u32 freq) +{

• /*

• * TODO: need set frequency to freq
  

• * LCDIF_PIXEL_CLK: ip_clk_root(10) sel 1st input source and pre_div
  

• * to 0.
  

• */
  

• u32 *reg = (u32 *)CCM_IP_CLK_ROOT_GEN_TAGET_CLR(10);
• *reg = (0x7 << 24) | (0x7 << 16);
• /* select 800MHz root clock, select divider 8, output is 100 MHz */
• reg = (u32 *)CCM_IP_CLK_ROOT_GEN_TAGET_SET(10);
• *reg = (0x4 << 24) | (0x7 << 16);

+}

+#define SRC_DDR1_ENABLE_MASK (0x8F000000UL) +#define SRC_DDR2_ENABLE_MASK (0x8F000000UL) +void dram_pll_init(void) +{

• unsigned long pll_control_reg = DRAM_PLL_CFG0;
• u32 pwdn_mask = 0;
• u32 pll_clke = 0;
• u32 bypass1 = 0;
• u32 bypass2 = 0;
• setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
• setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
• pwdn_mask = SSCG_PLL_PD_MASK;
• pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
• bypass1 = SSCG_PLL_BYPASS1_MASK;
• bypass2 = SSCG_PLL_BYPASS2_MASK;
• /* Enable DDR1 and DDR2 domain */
• writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1000);
• writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
• /* Clear power down bit */
• clrbits_le32(pll_control_reg, pwdn_mask);
• /* Eanble ARM_PLL/SYS_PLL */
• setbits_le32(pll_control_reg, pll_clke);
• /* Clear bypass */
• clrbits_le32(pll_control_reg, bypass1);
• __udelay(100);
• clrbits_le32(pll_control_reg, bypass2);
• /* Wait until lock */
• while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))

• ;
  

I see several of these potential endless loop - is it hen possible the SOC stucks here ?

If PLL not lock, it means the pll programming flow is not correct or some configuration is wrong, or else. It should be locked to make system work stable. Normally it will not dead loop here.

...

+}

+int clock_init(void) +{

• u32 val_cfg0;
• u32 grade;
• clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |

• 	     CLK_ROOT_SOURCE_SEL(0));
  

• /*

• * 8MQ only supports two grades: consumer and industrial.
  

• * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
  

• */
  

• grade = get_cpu_temp_grade(NULL, NULL);
• if (!grade) {

• frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
  

• clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
  

• 	     CLK_ROOT_SOURCE_SEL(1) |
  

• 	     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
  

• } else {

• frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
  

• clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
  

• 	     CLK_ROOT_SOURCE_SEL(1) |
  

• 	     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  

• }
• /*

• * According to ANAMIX SPEC
  

• * sys pll1 fixed at 800MHz
  

• * sys pll2 fixed at 1GHz
  

• * Here we only enable the outputs.
  

• */
  

• val_cfg0 = readl(SYS_PLL1_CFG0);
• val_cfg0 |= SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |

• SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
  

• SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
  

• SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
  

• SSCG_PLL_DIV20_CLKE_MASK;
  

• writel(val_cfg0, SYS_PLL1_CFG0);
• val_cfg0 = readl(SYS_PLL2_CFG0);
• val_cfg0 |= SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |

• SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
  

• SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
  

• SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
  

• SSCG_PLL_DIV20_CLKE_MASK;
  

• writel(val_cfg0, SYS_PLL2_CFG0);
• /*

• * set uart clock root
  

• * 25M OSC
  

• */
  

• clock_enable(CCGR_UART1, 0);
• clock_enable(CCGR_UART2, 0);
• clock_enable(CCGR_UART3, 0);
• clock_enable(CCGR_UART4, 0);
• clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |

• 	     CLK_ROOT_SOURCE_SEL(0));
  

• clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |

• 	     CLK_ROOT_SOURCE_SEL(0));
  

• clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |

• 	     CLK_ROOT_SOURCE_SEL(0));
  

• clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |

• 	     CLK_ROOT_SOURCE_SEL(0));
  

• clock_enable(CCGR_UART1, 1);
• clock_enable(CCGR_UART2, 1);
• clock_enable(CCGR_UART3, 1);
• clock_enable(CCGR_UART4, 1);

Ok, I am quite lost - with older SOCs, we have the goal to set just the clocks that are required by U-Boot. I mean specially the peripheral cloks. It looks to me that all clocks are enabled here, instead of having a configuration.

ok. I'll try to refine this part. But we do not have a clock tree driver.

I may need to add a simple clock driver to handle clock gate and pll settings.

...

• /*

• * set usdhc clock root
  

• * sys pll1 400M
  

• */
  

• clock_enable(CCGR_USDHC1, 0);
• clock_enable(CCGR_USDHC2, 0);
• clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |

• 	     CLK_ROOT_SOURCE_SEL(1));
  

• clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |

• 	     CLK_ROOT_SOURCE_SEL(1) |
  

• 	     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  

• clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |

• 	     CLK_ROOT_SOURCE_SEL(1) |
  

• 	     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  

• clock_enable(CCGR_USDHC1, 1);
• clock_enable(CCGR_USDHC2, 1);
• /*

• * set qspi root
  

• * sys pll1 100M
  

• */
  

• clock_enable(CCGR_QSPI, 0);
• clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |

• 	     CLK_ROOT_SOURCE_SEL(7));
  

• clock_enable(CCGR_QSPI, 1);
• if (!is_usb_boot()) {

• clock_enable(CCGR_USB_CTRL1, 0);
  

• clock_enable(CCGR_USB_CTRL2, 0);
  

• clock_enable(CCGR_USB_PHY1, 0);
  

• clock_enable(CCGR_USB_PHY2, 0);
  

• /* 500M */
  

• clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
  

• 		     CLK_ROOT_SOURCE_SEL(1));
  

• /* 100M */
  

• clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
  

• 		     CLK_ROOT_SOURCE_SEL(1));
  

• /* 100M */
  

• clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
  

• 		     CLK_ROOT_SOURCE_SEL(1));
  

• clock_enable(CCGR_USB_CTRL1, 1);
  

• clock_enable(CCGR_USB_CTRL2, 1);
  

• clock_enable(CCGR_USB_PHY1, 1);
  

• clock_enable(CCGR_USB_PHY2, 1);
  

• }
• clock_enable(CCGR_WDOG1, 0);
• clock_enable(CCGR_WDOG2, 0);
• clock_enable(CCGR_WDOG3, 0);
• clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |

• 	     CLK_ROOT_SOURCE_SEL(0));
  

• clock_enable(CCGR_WDOG1, 1);
• clock_enable(CCGR_WDOG2, 1);
• clock_enable(CCGR_WDOG3, 1);
• clock_enable(CCGR_TSENSOR, 1);
• return 0;

+};

+int set_clk_qspi(void) +{

• clock_enable(CCGR_QSPI, 0);
• /*

• * TODO: configure clock
  

• */
  

• clock_enable(CCGR_QSPI, 1);
• return 0;

+}

+#ifdef CONFIG_FEC_MXC +int set_clk_enet(enum enet_freq type) +{

• u32 target;
• u32 enet1_ref;
• /* disable the clock first */
• clock_enable(CCGR_ENET1, 0);
• clock_enable(CCGR_SIM_ENET, 0);
• switch (type) {
• case ENET_125MHZ:

• enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  

• break;
  

• case ENET_50MHZ:

• enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  

• break;
  

• case ENET_25MHZ:

• enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  

• break;
  

• default:

• return -EINVAL;
  

• }

Syntattically speaking, you have disabled the clock and after that you check if input is correct - when you return from function, you have disabled the clock.

You should check parameters first.

Yes. Thanks.

...

• /* set enet axi clock 266Mhz */
• target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |

•  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  

•  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  

• clock_set_target_val(ENET_AXI_CLK_ROOT, target);
• target = CLK_ROOT_ON | enet1_ref |

•  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  

•  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  

• clock_set_target_val(ENET_REF_CLK_ROOT, target);
• target = CLK_ROOT_ON |

• ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  

• CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  

• CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  

• clock_set_target_val(ENET_TIMER_CLK_ROOT, target);

+#ifdef CONFIG_FEC_MXC_25M_REF_CLK

Is this already dead code ? Who sets it ?

In case we need it, so add this here. Currently no one set it.

...

• target = CLK_ROOT_ON |

•  ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
  

•  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  

•  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  

• clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);

+#endif

• /* enable clock */
• clock_enable(CCGR_SIM_ENET, 1);
• clock_enable(CCGR_ENET1, 1);
• return 0;

+} +#endif

+u32 imx_get_fecclk(void) +{

• return get_root_clk(ENET_AXI_CLK_ROOT);

+}

+/*

• • Dump some clockes.
• */

+#ifndef CONFIG_SPL_BUILD +int do_mscale_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,

• 	 char * const argv[])
  

What is the meaning for mscale ?

This should be renamed to do_mx8m_showclocks.

...

+{

• u32 freq;
• freq = decode_frac_pll(ARM_PLL_CLK);
• printf("ARM_PLL %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
• printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
• printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
• printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
• printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
• printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
• printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
• printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
• printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
• printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
• printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
• printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
• printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
• printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
• printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
• printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
• printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
• printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
• printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
• freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
• printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
• freq = mxc_get_clock(UART1_CLK_ROOT);
• printf("UART1 %8d MHz\n", freq / 1000000);
• freq = mxc_get_clock(USDHC1_CLK_ROOT);
• printf("USDHC1 %8d MHz\n", freq / 1000000);
• freq = mxc_get_clock(QSPI_CLK_ROOT);
• printf("QSPI %8d MHz\n", freq / 1000000);
• return 0;

+}

+U_BOOT_CMD(

• clocks, CONFIG_SYS_MAXARGS, 1, do_mscale_showclocks,
• "display clocks",
• ""

+); +#endif diff --git a/arch/arm/mach-imx/mx8m/clock_slice.c b/arch/arm/mach-imx/mx8m/clock_slice.c new file mode 100644 index 0000000000..0dc00cded1 --- /dev/null +++ b/arch/arm/mach-imx/mx8m/clock_slice.c @@ -0,0 +1,820 @@ +/*

• • Copyright 2017 NXP
• • Peng Fan peng.fan@nxp.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <errno.h>

+DECLARE_GLOBAL_DATA_PTR;

+static struct clk_root_map root_array[] = {

• {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,

• {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
  

• },
• {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,

• {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
  

•  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  

• },
• {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,

• {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
  

• },
• {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,

• {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  

• },
• {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,

• {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  

• },
• {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,

• {OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
  

• },
• {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,

• {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
  

• },
• {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,

• {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
  

• },
• {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,

• {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
  

•  AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
  

• },
• {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,

• {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
  

•  EXT_CLK_1, EXT_CLK_4}
  

• },
• {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,

• {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
  

•  EXT_CLK_1, EXT_CLK_3}
  

• },
• {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,

• {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  

•  EXT_CLK_2, EXT_CLK_3}
  

• },
• {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,

• {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  

• },
• {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,

• {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  

• },
• {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,

• {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  

• },
• {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,

• {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  

• },
• {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,

• {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
  

•  SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  

• },
• {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,

• {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
  

•  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  

• },
• {IPG_CLK_ROOT, IPG_CLOCK_SLICE, 0,

• {}
  

• },
• {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,

• {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
  

•  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
  

• },
• {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_40M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL1_CLK },
  

• },
• {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,

• {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
  

•  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_250M_CLK,
  

•  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
  

• },
• {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,

• {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  

•  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  

• },
• {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,

• {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
  

•  SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
  

• },
• {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,

• {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
  

•  SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
  

• },
• {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,

• {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
  

• },
• {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,

• {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
  

• },
• {PCIE1_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,

• {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
  

• },
• {PCIE1_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
  

•  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
  

•  SYSTEM_PLL1_400M_CLK}
  

• },
• {PCIE1_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,

• {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  

•  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
  

• },
• {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,

• {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  

•  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  

• },
• {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,

• {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
  

•  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  

• },
• {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,

• {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  

•  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  

•  OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
  

• },
• {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,

• {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  

•  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  

•  OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
  

• },
• {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,

• {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  

•  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  

•  OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
  

• },
• {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,

• {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  

•  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  

•  OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
  

• },
• {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,

• {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  

•  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  

•  OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
  

• },
• {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,

• {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  

•  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  

•  OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
  

• },
• {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,

• {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  

•  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  

•  OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
  

• },
• {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,

• {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
  

•  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
  

•  OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
  

• },
• {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,

• {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
  

• },
• {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
  

•  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
  

•  VIDEO_PLL_CLK}
  

• },
• {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,

• {OSC_25M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
  

•  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
  

• },
• {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,

• {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
  

•  SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
  

•  SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
  

• },
• {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,

• {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
  

•  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
  

• },
• {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,

• {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
  

•  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
  

• },
• {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,

• {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
  

•  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
  

• },
• {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,

• {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  

•  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  

•  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  

• },
• {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,

• {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  

•  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  

•  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  

• },
• {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,

• {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  

•  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  

•  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  

• },
• {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,

• {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
  

•  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
  

•  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
  

• },
• {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,

• {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  

•  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  

• },
• {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,

• {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  

•  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  

• },
• {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,

• {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  

•  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  

• },
• {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,

• {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
  

•  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  

• },
• {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,

• {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  

• },
• {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,

• {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
  

• },
• {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,

• {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  

•  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
  

• },
• {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,

• {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  

•  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  

• },
• {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,

• {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  

•  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  

• },
• {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  

•  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  

•  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  

• },
• {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  

•  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  

•  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  

• },
• {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  

•  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  

•  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  

• },
• {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
  

•  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
  

•  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
  

• },
• {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  

•  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  

•  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
  

• },
• {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  

•  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  

•  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
  

• },
• {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  

•  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  

•  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
  

• },
• {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  

•  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  

•  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
  

• },
• {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  

•  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  

•  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
  

• },
• {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
  

•  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
  

•  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
  

• },
• {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,

• {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
  

•  VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
  

•  SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
  

• },
• {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,

• {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
  

•  VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
  

• },
• {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,

• {OSC_25M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
  

•  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
  

• },
• {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,

• {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK,
  

•  SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
  

•  SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
  

• },
• {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,

• {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
  

•  SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
  

•  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
  

• },
• {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,

• {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  

• },
• {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,

• {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  

• },
• {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,

• {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  

• },
• {OLD_MIPI_DSI_ESC_CLK_ROOT, IP_CLOCK_SLICE, 57,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  

• },
• {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,

• {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  

• },
• {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,

• {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  

• },
• {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  

• },
• {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,

• {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  

• },
• {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,

• {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
  

• },
• {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
  

• },
• {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,

• {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
  

• },
• {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
  

•  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
  

•  EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
  

• },
• {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,

• {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
  

•  SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
  

• },
• {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,

• {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
  

•  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
  

• },
• {OLD_MIPI_DSI_ESC_RX_ROOT, IP_CLOCK_SLICE, 68,

• {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
  

•  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
  

•  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
  

• },
• {DISPLAY_HDMI_CLK_ROOT, IP_CLOCK_SLICE, 69,

• {OSC_25M_CLK, SYSTEM_PLL1_200M_CLK, SYSTEM_PLL2_200M_CLK,
  

•  VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
  

•  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
  

• },
• {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,

• {DRAM_PLL1_CLK}
  

• },
• {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,

• {DRAM_PLL1_CLK}
  

• },

+};

+static int select(enum clk_root_index clock_id) +{

• int i, size;
• struct clk_root_map *p = root_array;
• size = ARRAY_SIZE(root_array);
• for (i = 0; i < size; i++, p++) {

• if (clock_id == p->entry)
  

• 	return i;
  

• }
• return -EINVAL;

+}

+static int src_supported(int entry, enum clk_root_src clock_src) +{

• int i;
• struct clk_root_map *p = &root_array[entry];
• for (i = 0; i < 8; i++) {

• if (p->src_mux[i] == clock_src)
  

• 	return i;
  

• }
• return -EINVAL;

+}

+static void __iomem *get_clk_root_target(enum clk_slice_type slice_type,

• 			 u32 slice_index)
  

+{

• void __iomem *clk_root_target;
• switch (slice_type) {
• case CORE_CLOCK_SLICE:

• clk_root_target =
  

• (void __iomem *)CCM_CORE_CLK_ROOT_GEN_TAGET(slice_index);
  

• break;
  

• case BUS_CLOCK_SLICE:

• clk_root_target =
  

• 	(void __iomem *)CCM_BUS_CLK_ROOT_GEN_TAGET(slice_index);
  

• break;
  

• case IP_CLOCK_SLICE:

• clk_root_target =
  

• 	(void __iomem *)CCM_IP_CLK_ROOT_GEN_TAGET(slice_index);
  

• break;
  

• case AHB_CLOCK_SLICE:

• clk_root_target =
  

• 	(void __iomem *)CCM_AHB_CLK_ROOT_GEN_TAGET(slice_index);
  

• break;
  

• case IPG_CLOCK_SLICE:

• clk_root_target =
  

• 	(void __iomem *)CCM_IPG_CLK_ROOT_GEN_TAGET(slice_index);
  

• break;
  

• case CORE_SEL_CLOCK_SLICE:

• clk_root_target =
  

• 	(void __iomem *)CCM_CORE_SEL_CLK_ROOT_GEN_TAGET;
  

• break;
  

• case DRAM_SEL_CLOCK_SLICE:

• clk_root_target =
  

• 	(void __iomem *)CCM_DRAM_SEL_CLK_ROOT_GEN_TAGET;
  

• break;
  

• default:

• return NULL;
  

• }
• return clk_root_target;

+}

+int clock_get_target_val(enum clk_root_index clock_id, u32 *val) +{

• int root_entry;
• struct clk_root_map *p;
• void __iomem *clk_root_target;
• if (clock_id >= CLK_ROOT_MAX)

• return -EINVAL;
  

• root_entry = select(clock_id);
• if (root_entry < 0)

• return -EINVAL;
  

• p = &root_array[root_entry];
• clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
• if (!clk_root_target)

• return -EINVAL;
  

• *val = readl(clk_root_target);
• return 0;

+}

+int clock_set_target_val(enum clk_root_index clock_id, u32 val) +{

• int root_entry;
• struct clk_root_map *p;
• void __iomem *clk_root_target;
• if (clock_id >= CLK_ROOT_MAX)

• return -EINVAL;
  

• root_entry = select(clock_id);
• if (root_entry < 0)

• return -EINVAL;
  

• p = &root_array[root_entry];
• clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
• if (!clk_root_target)

• return -EINVAL;
  

• writel(val, clk_root_target);
• return 0;

+}

+/* AUDO SLOW is ignored, they are rarely used. */ +int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,

•    enum root_post_div post_div, enum clk_root_src clock_src)
  

+{

• u32 val;
• int root_entry, src_entry;
• struct clk_root_map *p;
• void __iomem *clk_root_target;
• if (clock_id >= CLK_ROOT_MAX)

• return -EINVAL;
  

• root_entry = select(clock_id);
• if (root_entry < 0)

• return -EINVAL;
  

• p = &root_array[root_entry];
• if ((p->slice_type == CORE_CLOCK_SLICE) ||

•    (p->slice_type == IPG_CLOCK_SLICE) ||
  

•    (p->slice_type == CORE_SEL_CLOCK_SLICE) ||
  

•    (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
  

• if (pre_div != CLK_ROOT_PRE_DIV1) {
  

• 	printf("Error pre div!\n");
  

• 	return -EINVAL;
  

• }
  

• }
• if ((p->slice_type == CORE_SEL_CLOCK_SLICE) ||

•    (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
  

• if (post_div != CLK_ROOT_POST_DIV1) {
  

• 	printf("Error post div!\n");
  

• 	return -EINVAL;
  

• }
  

• }
• if (p->slice_type == CORE_CLOCK_SLICE) {

• if (post_div > CLK_ROOT_POST_DIV8) {
  

• 	printf("Error post div!\n");
  

• 	return -EINVAL;
  

• }
  

• }
• if (p->slice_type == IPG_CLOCK_SLICE) {

• if (post_div > CLK_ROOT_POST_DIV4) {
  

• 	printf("Error post div!\n");
  

• 	return -EINVAL;
  

• }
  

• }
• src_entry = src_supported(root_entry, clock_src);
• if (src_entry < 0)

• return -EINVAL;
  

• val = CLK_ROOT_ON | (pre_div << CLK_ROOT_PRE_DIV_SHIFT) |

•      (post_div << CLK_ROOT_POST_DIV_SHIFT) |
  

•      src_entry << CLK_ROOT_SRC_MUX_SHIFT;
  

• clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
• if (!clk_root_target)

• return -EINVAL;
  

• writel(val, clk_root_target);
• return 0;

+}

+int clock_root_enabled(enum clk_root_index clock_id) +{

• void __iomem *clk_root_target;
• u32 slice_index, slice_type;
• u32 val;
• int root_entry;
• if (clock_id >= CLK_ROOT_MAX)

• return -EINVAL;
  

• root_entry = select(clock_id);
• if (root_entry < 0)

• return -EINVAL;
  

• slice_type = root_array[root_entry].slice_type;
• slice_index = root_array[root_entry].slice_index;
• if ((slice_type == IPG_CLOCK_SLICE) ||

•    (slice_type == DRAM_SEL_CLOCK_SLICE) ||
  

•    (slice_type == CORE_SEL_CLOCK_SLICE)) {
  

• /*
  

•  * Not supported, from CCM doc
  

•  * TODO
  

•  */
  

• return 0;
  

• }
• clk_root_target = get_clk_root_target(slice_type, slice_index);
• if (!clk_root_target)

• return -EINVAL;
  

• val = readl(clk_root_target);
• return (val & CLK_ROOT_ON) ? 1 : 0;

+}

+/* CCGR CLK gate operation */ +int clock_enable(enum clk_ccgr_index index, bool enable) +{

• void __iomem *ccgr;
• if (index >= CCGR_MAX)

• return -EINVAL;
  

• if (enable)

• ccgr = (void __iomem *)CCM_CCGR_SET(index);
  

• else

• ccgr = (void __iomem *)CCM_CCGR_CLR(index);
  

• writel(CCGR_CLK_ON_MASK, ccgr);
• return 0;

+}

+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div) +{

• u32 val;
• int root_entry;
• struct clk_root_map *p;
• void __iomem *clk_root_target;
• if (clock_id >= CLK_ROOT_MAX)

• return -EINVAL;
  

• root_entry = select(clock_id);
• if (root_entry < 0)

• return -EINVAL;
  

• p = &root_array[root_entry];
• if ((p->slice_type == CORE_CLOCK_SLICE) ||

•    (p->slice_type == IPG_CLOCK_SLICE) ||
  

•    (p->slice_type == CORE_SEL_CLOCK_SLICE) ||
  

•    (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
  

• *pre_div = 0;
  

• return 0;
  

• }
• clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
• if (!clk_root_target)

• return -EINVAL;
  

• val = readl(clk_root_target);
• val &= CLK_ROOT_PRE_DIV_MASK;
• val >>= CLK_ROOT_PRE_DIV_SHIFT;
• *pre_div = val;
• return 0;

+}

+int clock_get_postdiv(enum clk_root_index clock_id,

•       enum root_post_div *post_div)
  

+{

• u32 val, mask;
• int root_entry;
• struct clk_root_map *p;
• void __iomem *clk_root_target;
• if (clock_id >= CLK_ROOT_MAX)

• return -EINVAL;
  

• root_entry = select(clock_id);
• if (root_entry < 0)

• return -EINVAL;
  

• p = &root_array[root_entry];
• if ((p->slice_type == CORE_SEL_CLOCK_SLICE) ||

•    (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
  

• *post_div = 0;
  

• return 0;
  

• }
• clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
• if (!clk_root_target)

• return -EINVAL;
  

• if (p->slice_type == IPG_CLOCK_SLICE)

• mask = CLK_ROOT_IPG_POST_DIV_MASK;
  

• else if (p->slice_type == CORE_CLOCK_SLICE)

• mask = CLK_ROOT_CORE_POST_DIV_MASK;
  

• else

• mask = CLK_ROOT_POST_DIV_MASK;
  

• val = readl(clk_root_target);
• val &= mask;
• val >>= CLK_ROOT_POST_DIV_SHIFT;
• *post_div = val;
• return 0;

+}

+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src) +{

• u32 val;
• int root_entry;
• struct clk_root_map *p;
• void __iomem *clk_root_target;
• if (clock_id >= CLK_ROOT_MAX)

• return -EINVAL;
  

• root_entry = select(clock_id);
• if (root_entry < 0)

• return -EINVAL;
  

• p = &root_array[root_entry];
• clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
• if (!clk_root_target)

• return -EINVAL;
  

• val = readl(clk_root_target);
• val &= CLK_ROOT_SRC_MUX_MASK;
• val >>= CLK_ROOT_SRC_MUX_SHIFT;
• *p_clock_src = p->src_mux[val];
• return 0;

+}