[U-Boot] [PATCH 0/3] pcie-layerscape: Enable PCI-LUT initialization for NXP-Chasis-2
First patch is rename the stream-id defination file to generic so that this can be leveraged for new SOCs, ls2088, ls1088 etc.
Second add stream-ids allocation for NXP Chasis-2 based SOCs, ls1043, ls1046 etc. and Third patch enables PCI-LUT initialization.
Bharat Bhushan (3): fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h pcie-layerscape: Define stream-ids for Layerscape Chasis-2 pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs
.../asm/arch-fsl-layerscape/ls2080a_stream_id.h | 77 ---------------------- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 60 +++++++++++++++++ .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 77 ++++++++++++++++++++++ drivers/pci/pcie_layerscape_fixup.c | 4 -- include/configs/ls1043a_common.h | 1 + include/configs/ls2080a_common.h | 2 +- 6 files changed, 139 insertions(+), 82 deletions(-) delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
The stream ID allocation for Chasis3.0 devices, LS1088, LS2088 and LS2080, can be shared.
This patch renames this accordingly.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com --- .../asm/arch-fsl-layerscape/ls2080a_stream_id.h | 77 ---------------------- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 77 ++++++++++++++++++++++ include/configs/ls2080a_common.h | 2 +- 3 files changed, 78 insertions(+), 78 deletions(-) delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h deleted file mode 100644 index ee28323..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - */ -#ifndef __FSL_STREAM_ID_H -#define __FSL_STREAM_ID_H - -/* - * Stream IDs on ls2080a devices are not hardwired and are - * programmed by sw. There are a limited number of stream IDs - * available, and the partitioning of them is scenario dependent. - * This header defines the partitioning between legacy, PCI, - * and DPAA2 devices. - * - * This partitioning can be customized in this file depending - * on the specific hardware config: - * - * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) - * -all legacy devices get a unique stream ID assigned and programmed in - * their AMQR registers by u-boot - * - * -PCIe - * -there is a range of stream IDs set aside for PCI in this - * file. U-boot will scan the PCI bus and for each device discovered: - * -allocate a streamID - * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' - * -set a msi-map entry in the PEXn controller node in the - * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt - * for more info on the msi-map definition) - * - * -DPAA2 - * -u-boot will allocate a range of stream IDs to be used by the Management - * Complex for containers and will set these values in the MC DPC image. - * -the MC is responsible for allocating and setting up 'isolation context - * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. - * - * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for - * each of the different bus masters. The relationship between - * the AMQ registers and stream IDs is defined in the table below: - * AMQ bit streamID bit - * --------------------------- - * PL[18] 9 // privilege bit - * BMT[17] 8 // bypass translation - * VA[16] 7 // reserved - * [15] - // unused - * ICID[14:7] - // unused - * ICID[6:0] 6-0 // isolation context id - * ---------------------------- - * - */ - -#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ -#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ - -#define FSL_INVALID_STREAM_ID 0 - -#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) - -/* legacy devices */ -#define FSL_USB1_STREAM_ID 1 -#define FSL_USB2_STREAM_ID 2 -#define FSL_SDMMC_STREAM_ID 3 -#define FSL_SATA1_STREAM_ID 4 -#define FSL_SATA2_STREAM_ID 5 -#define FSL_DMA_STREAM_ID 6 - -/* PCI - programmed in PEXn_LUT */ -#define FSL_PEX_STREAM_ID_START 7 -#define FSL_PEX_STREAM_ID_END 22 - -/* DPAA2 - set in MC DPC and alloced by MC */ -#define FSL_DPAA2_STREAM_ID_START 23 -#define FSL_DPAA2_STREAM_ID_END 63 - -#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h new file mode 100644 index 0000000..ee28323 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -0,0 +1,77 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on ls2080a devices are not hardwired and are + * programmed by sw. There are a limited number of stream IDs + * available, and the partitioning of them is scenario dependent. + * This header defines the partitioning between legacy, PCI, + * and DPAA2 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * + * -DPAA2 + * -u-boot will allocate a range of stream IDs to be used by the Management + * Complex for containers and will set these values in the MC DPC image. + * -the MC is responsible for allocating and setting up 'isolation context + * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. + * + * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for + * each of the different bus masters. The relationship between + * the AMQ registers and stream IDs is defined in the table below: + * AMQ bit streamID bit + * --------------------------- + * PL[18] 9 // privilege bit + * BMT[17] 8 // bypass translation + * VA[16] 7 // reserved + * [15] - // unused + * ICID[14:7] - // unused + * ICID[6:0] 6-0 // isolation context id + * ---------------------------- + * + */ + +#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ +#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ + +#define FSL_INVALID_STREAM_ID 0 + +#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_SDMMC_STREAM_ID 3 +#define FSL_SATA1_STREAM_ID 4 +#define FSL_SATA2_STREAM_ID 5 +#define FSL_DMA_STREAM_ID 6 + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 7 +#define FSL_PEX_STREAM_ID_END 22 + +/* DPAA2 - set in MC DPC and alloced by MC */ +#define FSL_DPAA2_STREAM_ID_START 23 +#define FSL_DPAA2_STREAM_ID_END 63 + +#endif diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 7aef43f..e120f6e 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -13,7 +13,7 @@ #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147
-#include <asm/arch/ls2080a_stream_id.h> +#include <asm/arch/stream_id_lsch3.h> #include <asm/arch/config.h>
/* Link Definitions */
On 01/30/2017 02:45 AM, Bharat Bhushan wrote:
The stream ID allocation for Chasis3.0 devices, LS1088, LS2088 and LS2080, can be shared.
This patch renames this accordingly.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com
.../asm/arch-fsl-layerscape/ls2080a_stream_id.h | 77 ---------------------- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 77 ++++++++++++++++++++++ include/configs/ls2080a_common.h | 2 +- 3 files changed, 78 insertions(+), 78 deletions(-) delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
Bharat,
When you create patches, please use tools/patman/patman. It automatically does many things for you. If you have to create it manually, make sure you use -M -C flag for "git format-patch". This patch should show changes as
.../asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} | 0 include/configs/ls2080a_common.h | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} (100%)
It would be lot easier to review.
York
-----Original Message----- From: york sun Sent: Monday, January 30, 2017 9:44 PM To: Bharat Bhushan bharat.bhushan@nxp.com; Z.Q. Hou zhiqiang.hou@nxp.com; M.H. Lian minghuan.lian@nxp.com; u- boot@lists.denx.de Cc: albert.u.boot@aribaud.net; sjg@chromium.org Subject: Re: [PATCH 1/3] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
On 01/30/2017 02:45 AM, Bharat Bhushan wrote:
The stream ID allocation for Chasis3.0 devices, LS1088, LS2088 and LS2080, can be shared.
This patch renames this accordingly.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com
.../asm/arch-fsl-layerscape/ls2080a_stream_id.h | 77 ---------------------- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 77
++++++++++++++++++++++
include/configs/ls2080a_common.h | 2 +- 3 files changed, 78 insertions(+), 78 deletions(-) delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
Bharat,
When you create patches, please use tools/patman/patman. It automatically does many things for you. If you have to create it manually, make sure you use -M -C flag for "git format-patch". This patch should show changes as
.../asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} | 0 include/configs/ls2080a_common.h | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} (100%)
It would be lot easier to review.
Thanks York, , will ensure from next time.
Thanks -Bharat
York
From: U-Boot u-boot-bounces@lists.denx.de on behalf of Bharat Bhushan Bharat.Bhushan@nxp.com Sent: Monday, January 30, 2017 12:43 PM To: york sun; Z.Q. Hou; M.H. Lian; u-boot@lists.denx.de Cc: albert.u.boot@aribaud.net Subject: [U-Boot] [PATCH 1/3] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h
The stream ID allocation for Chasis3.0 devices,
s/Chasis/Chassis
LS1088, LS2088 and LS2080, can be shared.
This patch renames this accordingly.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com
.../asm/arch-fsl-layerscape/ls2080a_stream_id.h | 77 ---------------------- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 77 ++++++++++++++++++++++ include/configs/ls2080a_common.h | 2 +- 3 files changed, 78 insertions(+), 78 deletions(-) delete mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h deleted file mode 100644 index ee28323..0000000 --- a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h +++ /dev/null @@ -1,77 +0,0 @@ -/*
- Copyright 2014 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __FSL_STREAM_ID_H -#define __FSL_STREAM_ID_H
-/*
- Stream IDs on ls2080a devices are not hardwired and are
- programmed by sw. There are a limited number of stream IDs
- available, and the partitioning of them is scenario dependent.
- This header defines the partitioning between legacy, PCI,
- and DPAA2 devices.
- This partitioning can be customized in this file depending
- on the specific hardware config:
- -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
-all legacy devices get a unique stream ID assigned and programmed in
their AMQR registers by u-boot
- -PCIe
-there is a range of stream IDs set aside for PCI in this
file. U-boot will scan the PCI bus and for each device discovered:
-allocate a streamID
-set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
-set a msi-map entry in the PEXn controller node in the
device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
for more info on the msi-map definition)
- -DPAA2
-u-boot will allocate a range of stream IDs to be used by the Management
Complex for containers and will set these values in the MC DPC image.
-the MC is responsible for allocating and setting up 'isolation context
IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
- On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
- each of the different bus masters. The relationship between
- the AMQ registers and stream IDs is defined in the table below:
AMQ bit streamID bit
---------------------------
PL[18] 9 // privilege bit
BMT[17] 8 // bypass translation
VA[16] 7 // reserved
[15] - // unused
ICID[14:7] - // unused
ICID[6:0] 6-0 // isolation context id
----------------------------
- */
-#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ -#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
-#define FSL_INVALID_STREAM_ID 0
-#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
-/* legacy devices */ -#define FSL_USB1_STREAM_ID 1 -#define FSL_USB2_STREAM_ID 2 -#define FSL_SDMMC_STREAM_ID 3 -#define FSL_SATA1_STREAM_ID 4 -#define FSL_SATA2_STREAM_ID 5 -#define FSL_DMA_STREAM_ID 6
-/* PCI - programmed in PEXn_LUT */ -#define FSL_PEX_STREAM_ID_START 7 -#define FSL_PEX_STREAM_ID_END 22
-/* DPAA2 - set in MC DPC and alloced by MC */ -#define FSL_DPAA2_STREAM_ID_START 23 -#define FSL_DPAA2_STREAM_ID_END 63
-#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h new file mode 100644 index 0000000..ee28323 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -0,0 +1,77 @@ +/*
- Copyright 2014 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H
+/*
- Stream IDs on ls2080a devices are not hardwired and are
Why do we keep the references to ls2080a device if this definition targets LS chassis 3.0 devices? Same comment applies for patch 2/3.
- programmed by sw. There are a limited number of stream IDs
- available, and the partitioning of them is scenario dependent.
- This header defines the partitioning between legacy, PCI,
- and DPAA2 devices.
- This partitioning can be customized in this file depending
- on the specific hardware config:
- -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
-all legacy devices get a unique stream ID assigned and programmed in
their AMQR registers by u-boot
- -PCIe
-there is a range of stream IDs set aside for PCI in this
file. U-boot will scan the PCI bus and for each device discovered:
-allocate a streamID
-set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
-set a msi-map entry in the PEXn controller node in the
device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
for more info on the msi-map definition)
- -DPAA2
-u-boot will allocate a range of stream IDs to be used by the Management
Complex for containers and will set these values in the MC DPC image.
-the MC is responsible for allocating and setting up 'isolation context
IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
- On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
similar
- each of the different bus masters. The relationship between
- the AMQ registers and stream IDs is defined in the table below:
AMQ bit streamID bit
---------------------------
PL[18] 9 // privilege bit
BMT[17] 8 // bypass translation
VA[16] 7 // reserved
[15] - // unused
ICID[14:7] - // unused
ICID[6:0] 6-0 // isolation context id
----------------------------
- */
+#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ +#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
+#define FSL_INVALID_STREAM_ID 0
+#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
+/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_SDMMC_STREAM_ID 3 +#define FSL_SATA1_STREAM_ID 4 +#define FSL_SATA2_STREAM_ID 5 +#define FSL_DMA_STREAM_ID 6
+/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 7 +#define FSL_PEX_STREAM_ID_END 22
+/* DPAA2 - set in MC DPC and alloced by MC */ +#define FSL_DPAA2_STREAM_ID_START 23 +#define FSL_DPAA2_STREAM_ID_END 63
+#endif diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 7aef43f..e120f6e 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -13,7 +13,7 @@ #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147
-#include <asm/arch/ls2080a_stream_id.h> +#include <asm/arch/stream_id_lsch3.h> #include <asm/arch/config.h>
/* Link Definitions */
1.9.3
U-Boot mailing list U-Boot@lists.denx.de https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.denx...
-Mike
Layerscape Chasis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they lies behind SMMU.
This patch defines the stream-ids for Chasis-2 devices. stream-ids for DPAA1 are reserved for future use.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com --- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 60 ++++++++++++++++++++++ include/configs/ls1043a_common.h | 1 + 2 files changed, 61 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h new file mode 100644 index 0000000..bdfed83 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -0,0 +1,60 @@ +/* + * Copyright 2017 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on ls1043a devices are not hardwired and are + * programmed by sw. There are a limited number of stream IDs + * available, and the partitioning of them is scenario dependent. + * This header defines the partitioning between legacy, PCI, + * and DPAA1 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * + * -DPAA1 + * - Stream ids for DPAA1 use are reserved for future usecase. + * + */ + + +#define FSL_INVALID_STREAM_ID 0 + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9 + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 11 +#define FSL_PEX_STREAM_ID_END 26 + +/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END 63 + +#endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index aa2b6f1..eee6fad 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -13,6 +13,7 @@ #define CONFIG_MP #define CONFIG_GICV2
+#include <asm/arch/stream_id_lsch2.h> #include <asm/arch/config.h>
/* Link Definitions */
From: U-Boot u-boot-bounces@lists.denx.de on behalf of Bharat Bhushan Bharat.Bhushan@nxp.com Sent: Monday, January 30, 2017 12:43 PM To: york sun; Z.Q. Hou; M.H. Lian; u-boot@lists.denx.de Cc: albert.u.boot@aribaud.net Subject: [U-Boot] [PATCH 2/3] pcie-layerscape: Define stream-ids for Layerscape Chasis-2
Layerscape Chasis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they lies behind SMMU.
This patch defines the stream-ids for Chasis-2 devices. stream-ids for DPAA1 are reserved for future use.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com
.../asm/arch-fsl-layerscape/stream_id_lsch2.h | 60 ++++++++++++++++++++++ include/configs/ls1043a_common.h | 1 + 2 files changed, 61 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h new file mode 100644 index 0000000..bdfed83 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -0,0 +1,60 @@ +/*
- Copyright 2017 NXP Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H
+/*
- Stream IDs on ls1043a devices are not hardwired and are
- programmed by sw. There are a limited number of stream IDs
- available, and the partitioning of them is scenario dependent.
- This header defines the partitioning between legacy, PCI,
- and DPAA1 devices.
- This partitioning can be customized in this file depending
- on the specific hardware config:
- -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
-all legacy devices get a unique stream ID assigned and programmed in
their AMQR registers by u-boot
- -PCIe
-there is a range of stream IDs set aside for PCI in this
file. U-boot will scan the PCI bus and for each device discovered:
-allocate a streamID
-set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
-set a msi-map entry in the PEXn controller node in the
device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
for more info on the msi-map definition)
- -DPAA1
- Stream ids for DPAA1 use are reserved for future usecase.
- */
+#define FSL_INVALID_STREAM_ID 0
+/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9
+/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 11 +#define FSL_PEX_STREAM_ID_END 26
+/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END 63
+#endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index aa2b6f1..eee6fad 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -13,6 +13,7 @@ #define CONFIG_MP #define CONFIG_GICV2
+#include <asm/arch/stream_id_lsch2.h>
Since the following patch 3/3 enables LUT for all Chassis 2.0 devices, this definition should be included and validated for the other devices too: LS1046A, LS1012A, LS1021A.
#include <asm/arch/config.h>
/* Link Definitions */
1.9.3
U-Boot mailing list U-Boot@lists.denx.de https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.denx...
-Mike
Layerscape Chasis-2 also uses same PCIe controller as used in Chasis-3 and have similar PCI-Lut.
We need to initialize the pcie-lut for Chasis-2 also as in Chasis-3.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com --- drivers/pci/pcie_layerscape_fixup.c | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 19ede2f..2f13e1f 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -15,7 +15,6 @@ #include <fdt_support.h> #include "pcie_layerscape.h"
-#ifdef CONFIG_FSL_LSCH3 /* * Return next available LUT index. */ @@ -141,7 +140,6 @@ static void fdt_fixup_pcie(void *blob) streamid); } } -#endif
static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) { @@ -175,9 +173,7 @@ void ft_pci_setup(void *blob, bd_t *bd) list_for_each_entry(pcie, &ls_pcie_list, list) ft_pcie_ls_setup(blob, pcie);
-#ifdef CONFIG_FSL_LSCH3 fdt_fixup_pcie(blob); -#endif }
#else /* !CONFIG_OF_BOARD_SETUP */
participants (4)
-
Bharat Bhushan -
Bharat Bhushan
-
Mike Caraman -
york sun