Provides initial support for TI OMAP-L1x/DA8xx SoC devices. See http://www.ti.com

Provides: Low level initialisation. System clock API. Timer control.

Signed-off-by: Nick Thompson nick.thompson@gefanuc.com --- Applies to u-boot-ti

diff --git a/cpu/arm926ejs/davinci/cpu.c b/cpu/arm926ejs/davinci/cpu.c index 390cab8..4095d56 100644 --- a/cpu/arm926ejs/davinci/cpu.c +++ b/cpu/arm926ejs/davinci/cpu.c @@ -23,7 +23,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/hardware.h> - +#include <asm/io.h>

/* offsets from PLL controller base */ #define PLLC_PLLCTL 0x100 @@ -60,6 +60,44 @@ #define DDR_PLLDIV PLLC_PLLDIV1 #endif

+#ifdef CONFIG_SOC_DA8XX +const unsigned int const sysdiv[9] = { + PLL0_DIV1, PLL0_DIV2, PLL0_DIV3, PLL0_DIV4, + PLL0_DIV5, PLL0_DIV6, PLL0_DIV7, PLL0_DIV8, + PLL0_DIV9 +}; + +int clk_get(unsigned int id) +{ + int pre_div = (readl(PLL0_PREDIV) & 0xff) + 1; + int pllm = readl(PLL0_PLLM) + 1; + int post_div = (readl(PLL0_POSTDIV) & 0xff) + 1; + int pll_out = CONFIG_SYS_OSCIN_FREQ; + + if (id == DAVINCI_AUXCLK_CLKID) + goto out; + + /* + * Lets keep this simple. Combining operations can result in + * unexpected approximations + */ + pll_out /= pre_div; + pll_out *= pllm; + + if (id == DAVINCI_PLLM_CLKID) + goto out; + + pll_out /= post_div; + + if (id == DAVINCI_PLLC_CLKID) + goto out; + + pll_out /= (readl(sysdiv[id - 1]) & 0xff) + 1; + +out: + return pll_out; +} +#endif /* CONFIG_SOC_DA8XX */

#ifdef CONFIG_DISPLAY_CPUINFO

diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c index 5bb972f..7e07ae6 100644 --- a/cpu/arm926ejs/davinci/psc.c +++ b/cpu/arm926ejs/davinci/psc.c @@ -25,6 +25,7 @@

#include <common.h> #include <asm/arch/hardware.h> +#include <asm/io.h>

/* * The PSC manages three inputs to a "module" which may be a peripheral or @@ -47,21 +48,41 @@ /* Works on Always On power domain only (no PD argument) */ void lpsc_on(unsigned int id) { - dv_reg_p mdstat, mdctl; + unsigned int mdstat, mdctl, ptstat, ptcmd;

+#ifndef CONFIG_SOC_DA8XX if (id >= DAVINCI_LPSC_GEM) return; /* Don't work on DSP Power Domain */

- mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); - mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + mdstat = PSC_MDSTAT_BASE + (id * 4); + mdctl = PSC_MDCTL_BASE + (id * 4); + ptstat = PSC_PTSTAT; + ptcmd = PSC_PTCMD; +#else + if (id > DAVINCI_LPSC_L3_CBA_RAM) + return; + + if (id < DAVINCI_LPSC_BASE) { + mdstat = PSC0_MDSTAT + (id * 4); + mdctl = PSC0_MDCTL + (id * 4); + ptstat = PSC0_PTSTAT; + ptcmd = PSC0_PTCMD; + } else { + id -= 32; + mdstat = PSC1_MDSTAT + (id * 4); + mdctl = PSC1_MDCTL + (id * 4); + ptstat = PSC1_PTSTAT; + ptcmd = PSC1_PTCMD; + } +#endif

- while (REG(PSC_PTSTAT) & 0x01) + while (readl(ptstat) & 0x01) continue;

- if ((*mdstat & 0x1f) == 0x03) - return; /* Already on and enabled */ + if ((readl(mdstat) & 0x1f) == 0x03) + return; /* Already on and enabled */

- *mdctl |= 0x03; + writel(readl(mdctl) | 0x03, mdctl);

switch (id) { #ifdef CONFIG_SOC_DM644X @@ -80,16 +101,16 @@ void lpsc_on(unsigned int id) case DAVINCI_LPSC_MEMSTICK: case DAVINCI_LPSC_McBSP: case DAVINCI_LPSC_GPIO: - *mdctl |= 0x200; + writel(readl(mdctl) | 0x200, mdctl); break; #endif }

- REG(PSC_PTCMD) = 0x01; + writel(0x01, ptcmd);

- while (REG(PSC_PTSTAT) & 0x03) + while (readl(ptstat) & 0x01) continue; - while ((*mdstat & 0x1f) != 0x03) /* Probably an overkill... */ + while ((readl(mdstat) & 0x1f) != 0x03) continue; }