Register Global frame length adjustment is used to do frame length adjustment for SOF/ITP counter which is running on the ref_clk. Allow updating it could help on avoiding potential USB 2.0 devices time-out over a longer run.

Refer to Linux commit db2be4e9e30c (“usb: dwc3: Add frame length adjustment quirk”)

Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: - None

drivers/usb/dwc3/core.c | 34 ++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 7 +++++++ 2 files changed, 41 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 2e00353..b3d4751 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -310,6 +310,25 @@ static void dwc3_free_scratch_buffers(struct dwc3 *dwc) kfree(dwc->scratchbuf); }

+/* + * dwc3_frame_length_adjustment - Adjusts frame length if required + * @dwc3: Pointer to our controller context structure + * @val: Value of frame length + */ +static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 val) +{ + u32 reg; + u32 dft; + + reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); + dft = reg & DWC3_GFLADJ_30MHZ_MASK; + if (dft != val) { + reg &= ~DWC3_GFLADJ_30MHZ_MASK; + reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | val; + dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); + } +} + static void dwc3_core_num_eps(struct dwc3 *dwc) { struct dwc3_hwparams *parms = &dwc->hwparams; @@ -569,6 +588,9 @@ static int dwc3_core_init(struct dwc3 *dwc) if (ret) goto err1;

+ if (dwc->fladj_quirk && dwc->revision >= DWC3_REVISION_250A) + dwc3_frame_length_adjustment(dwc, dwc->fladj); + return 0;

err1: @@ -958,6 +980,18 @@ void dwc3_of_parse(struct dwc3 *dwc)

dwc->hird_threshold = hird_threshold | (dwc->is_utmi_l1_suspend << 4); + + dwc->fladj_quirk = false; + if (!dev_read_u32(dev, + "snps,quirk-frame-length-adjustment", + &dwc->fladj)) { + if (dwc->fladj <= DWC3_GFLADJ_30MHZ_MASK) + dwc->fladj_quirk = true; + else + dev_err(dev, + "snps,quirk-frame-length-adjustment invalid: 0x%x\n", + dwc->fladj); + } }

int dwc3_init(struct dwc3 *dwc) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 44533fd..4650216 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -115,6 +115,7 @@ #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))

#define DWC3_GHWPARAMS8 0xc600 +#define DWC3_GFLADJ 0xc630

/* Device Registers */ #define DWC3_DCFG 0xc700 @@ -291,6 +292,10 @@ #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))

+/* Global Frame Length Adjustment Register */ +#define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) +#define DWC3_GFLADJ_30MHZ_MASK 0x3f + /* Device Event Enable Register */ #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) @@ -764,6 +769,7 @@ struct dwc3 { u32 num_event_buffers; u32 u1u2; u32 maximum_speed; + u32 fladj; u32 revision;

#define DWC3_REVISION_173A 0x5533173a @@ -845,6 +851,7 @@ struct dwc3 {

unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; + unsigned fladj_quirk:1; int index; struct list_head list; };

Enable the undefined length INCR burst type and set INCRx. Different platforms may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value.

Refer to Linux commit (“usb: dwc3: Enable undefined length INCR burst type”)

Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: - None, only context changed to fit removal of [v1 2/7] usb: dwc3: add disable receiver detection in P3 quirk

drivers/usb/dwc3/core.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 13 +++++++ 2 files changed, 109 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index b3d4751..6dc9781 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -310,6 +310,99 @@ static void dwc3_free_scratch_buffers(struct dwc3 *dwc) kfree(dwc->scratchbuf); }

+#if CONFIG_IS_ENABLED(DM_USB) +/* set global incr burst type configuration registers */ +static void dwc3_set_incr_burst_type(struct dwc3 *dwc) +{ + struct udevice *dev = dwc->dev; + bool incrx_mode; + u32 incrx_size; + u32 *vals; + u32 cfg; + int ntype; + int ret; + int i; + + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); + + /* + * Handle property "snps,incr-burst-type-adjustment". + * Get the number of value from this property: + * result <= 0, means this property is not supported. + * result = 1, means INCRx burst mode supported. + * result > 1, means undefined length burst mode supported. + */ + ntype = dev_read_size(dev, "snps,incr-burst-type-adjustment") / sizeof(u32); + if (ntype <= 0) + return; + + vals = memalign(CONFIG_SYS_CACHELINE_SIZE, ntype * sizeof(u32)); + if (!vals) { + dev_err(dev, "Error to get memory\n"); + return; + } + + /* Get INCR burst type, and parse it */ + ret = dev_read_u32_array(dev, "snps,incr-burst-type-adjustment", vals, ntype); + if (ret) { + kfree(vals); + dev_err(dev, "Error to get property\n"); + return; + } + + incrx_size = *vals; + + if (ntype > 1) { + /* INCRX (undefined length) burst mode */ + incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; + for (i = 1; i < ntype; i++) { + if (vals[i] > incrx_size) + incrx_size = vals[i]; + } + } else { + /* INCRX burst mode */ + incrx_mode = INCRX_BURST_MODE; + } + + kfree(vals); + + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; + if (incrx_mode) + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; + switch (incrx_size) { + case 256: + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; + break; + case 128: + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; + break; + case 64: + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; + break; + case 32: + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; + break; + case 16: + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; + break; + case 8: + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; + break; + case 4: + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; + break; + case 1: + break; + default: + dev_err(dev, "Invalid property\n"); + break; + } + + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); +} +#endif + /* * dwc3_frame_length_adjustment - Adjusts frame length if required * @dwc3: Pointer to our controller context structure @@ -591,6 +684,9 @@ static int dwc3_core_init(struct dwc3 *dwc) if (dwc->fladj_quirk && dwc->revision >= DWC3_REVISION_250A) dwc3_frame_length_adjustment(dwc, dwc->fladj);

+#if CONFIG_IS_ENABLED(OF_CONTROL) + dwc3_set_incr_burst_type(dwc); +#endif return 0;

err1: diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 4650216..3f9b8e5 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -139,6 +139,17 @@

/* Bit fields */

+/* Global SoC Bus Configuration INCRx Register 0 */ +#define DWC3_GSBUSCFG0_INCR256BRSTENA BIT(7) /* INCR256 burst */ +#define DWC3_GSBUSCFG0_INCR128BRSTENA BIT(6) /* INCR128 burst */ +#define DWC3_GSBUSCFG0_INCR64BRSTENA BIT(5) /* INCR64 burst */ +#define DWC3_GSBUSCFG0_INCR32BRSTENA BIT(4) /* INCR32 burst */ +#define DWC3_GSBUSCFG0_INCR16BRSTENA BIT(3) /* INCR16 burst */ +#define DWC3_GSBUSCFG0_INCR8BRSTENA BIT(2) /* INCR8 burst */ +#define DWC3_GSBUSCFG0_INCR4BRSTENA BIT(1) /* INCR4 burst */ +#define DWC3_GSBUSCFG0_INCRBRSTENA BIT(0) /* undefined length enable */ +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff + /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) #define DWC3_GCTL_U2RSTECN (1 << 16) @@ -856,6 +867,8 @@ struct dwc3 { struct list_head list; };

+#define INCRX_BURST_MODE 0 +#define INCRX_UNDEF_LENGTH_BURST_MODE 1 /* -------------------------------------------------------------------------- */

/* -------------------------------------------------------------------------- */

Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: - None

drivers/usb/dwc3/dwc3-generic.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index d949083..66c878a 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -449,6 +449,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "rockchip,rk3328-dwc3" }, { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "qcom,dwc3" }, + { .compatible = "nxp,layerscape-dwc3" }, { } };

Benefit is, besides host mode, now user can choose device mode with setting of dr_mode = “peripheral”;

Signed-off-by: Ran Wang ran.wang_1@nxp.com --- Change in v2: - Remove property 'snps,dis_rxdet_inp3_quirk' due to its side effect to Linux kernel (USB device no detected)

arch/arm/dts/fsl-ls1088a.dtsi | 38 ++++++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 6653794..9d4f40c 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -121,18 +121,36 @@ interrupts = <0 21 0x4>; /* Level high type */ };

- usb0: usb3@3100000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 0x4>; /* Level high type */ - dr_mode = "host"; + usb0: usb@3100000 { + compatible = "nxp,layerscape-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + }; };

- usb1: usb3@3110000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 0x4>; /* Level high type */ - dr_mode = "host"; + usb1: usb@3110000 { + compatible = "nxp,layerscape-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + }; };

pcie@3400000 {