Hi Tsvetan,

On Thu, 19 Feb 2015 14:38:58 +0200 Siarhei Siamashka siarhei.siamashka@gmail.com wrote:

On Wed, 18 Feb 2015 22:29:07 -0800 (PST) TsvetanUsunov tsvetanusunov@gmail.com wrote:

...

Hi

For A13-OLinuxino till now we conservatively used the Linux-Sunxi uboot, but we recently got new lot of Samsung memories and we decided to tweak some parameters for this DDR in Linux-Sunxi uboot and found problems. As this uboot is with status not maintained anymore I will not discuss the problems, as probably no one will spend time on it,

This is actually very much interesting. What kind of problems you got after the change of DDR3 chips? My (probably somewhat limited) understanding is that all DDR3 chips have to support standard timings according to the JEDEC specs. There are several standard speed bins, so the faster chips just are tested for compatibility with a faster speed bin and labelled as such.

BUT

The "magic" Allwinner settings in u-boot make the DDR3 chips configuration violate the spec:

http://lists.denx.de/pipermail/u-boot/2015-January/201787.html

So I would not be very surprised if some of the chips can tolerate these settings and the others can't.

If you can confirm that this is indeed the problem, then we might try to drop the problematic magic settings sooner. You can find a collection of DDR3 timing parameters for different clock speeds and JEDEC speed bins at:

http://git.denx.de/?p=u-boot.git;a=blob;f=board/sunxi/dram_timings_sun4i.h;h...

The hardware documentation about the timing parameters is in the linux-sunxi wiki (no official documentation exists, but we took some efforts to collect the information about similar DRAM controllers used in Rockchip/TI SoCs from the Internet and verify that they actually apply to our hardware, mostly using the "trial and error" method of black box testing):

http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_TPR0 http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_TPR1 http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_TPR2

Additionally, by tweaking the impedance matching configuration (using a brute force search and some heuristics), we can reach much higher DRAM clock speeds on various hardware. Some information about this is here:

http://linux-sunxi.org/A10_DRAM_Controller_Calibration

I know that Olimex has opted to just change the RZQ resistors nominal away from the standard 240 Ohm in different board revisions instead of tweaking the impedance via software. This introduces a practical problem for us on Olimex boards, which employ these tricks.

It would be great if we could have a better cooperation with Olimex and maybe improve the DRAM configuration on Olimex boards to get better reliability and performance. Basically, we need to run certain tests on a statistically significant number of boards, preferably from different batches. I can help and answer questions. But most of the information is already available in the linux-sunxi wiki.

...

so we wisely decided to move to mainline uboot :) but it seems there are other issues to address.

That's a good choice :)

BTW, the blog post

https://olimex.wordpress.com/2014/10/27/a20-olinuxino-lime2-review-and-updates/

says that "Much better routing of DDR3 memory. We increased the number of layers to 8 vs the 6 layers in LIME, we put the DDR3 memory closer to the A20, we layout the tracks shorter, as result now LIME2 runs with DDR3 on 532Mhz on LIME there were problems to run DDR3 at more than 400Mhz"

I'm very happy about the improved DRAM clock speed in LIME2. But if I understand this correctly, the old LIME is not expected to be reliable with the DRAM clocked higher than 400MHz? Are you now going to contribute updates for

http://git.denx.de/?p=u-boot.git;a=blob;f=configs/A10-OLinuXino-Lime_defconfig;h=8fa1a330cd34e1a8202892595c549971b3275169;hb=HEAD
http://git.denx.de/?p=u-boot.git;a=blob;f=configs/A20-OLinuXino-Lime_defconfig;h=5442f645f87165c34bbed8ba3e6cde3d8a8b87e8;hb=HEAD

to pick a more reasonable DRAM clock speed? Or do you see no problems having it configured as 480MHz in the mainline u-boot for A10-OLinuXino-Lime and A20-OLinuXino-Lime?

This is just a reminder to say that I'm still very much interested to get a reply. You seem to be assuming that nobody here (and in the upstream U-Boot) is interested in the DRAM settings used on Olimex boards, but this is not quite true.

The wiki page at https://www.olimex.com/wiki/A13-OLinuXino now says:

"Please note that you might need different Debian Linux images for different boards with different hardware - you would need to inspect the DDR3 RAM memory and use the image suitable for your board. Previously we used HYNIX H5TQ2G83CFR, now we use SAMSUNG K4B2G0846Q.

Newest official Debian release (recommended):

Torrent of Debian release 11.2 suitable for boards with SAMSUNG K4B2G0846Q DDR3 RAM memory: A13 Debian Linux with kernel 3.4.90+, suitable for boards with SAMSUNG DDR3 RAM

Torrent of Debian release 10 suitable for boards with HYNIX H5TQ2G83CFR DDR3 RAM memory: A13 Debian Linux with kernel 3.4.90+, suitable for HYNIX DDR3 RAM".

So Olimex is using different DRAM settings for the A13-OLinuXino board, depending on the DRAM chip type. And providing binary images to the end users.

SAMSUNG K4B2G0846Q is quite interesting, because it is a family of DDR3 chips supporting speeds ranging from DDR3-1600 to DDR3-2133. And they are only officially backwards compatible with DDR3-1600, but not with anything lower. And we are mostly interested in DDR3-1066 timings. DDR3-1600 specifies 13.75 ns timings for tRCD/tRP, while DDR3-1066F speed bin specifies 13.125 ns. These newer SAMSUNG chips support higher clock frequencies, but have *worse* access latency. I would not be very surprised if this is exactly the source of the reliability problems. So it probably makes sense to use the DDR3-1066G speed bin timings (15 ns) for these chips. This can be done by adding the following line to the A13-OLinuXino defconfig file in U-Boot:

+S:CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y

Additionally, I did a bit of detective work earlier and "interrogated" a user named <TJvV> in the #olimex irc channel:

https://www.olimex.com/irc?date=2015-02-24

Appears that these binary images, supplied by Olimex, are indeed using non-default DRAM settings. And an additional observation is that the DCDC3 voltage is set to only 1.2V on this board (down from the default 1.25V configured by U-Boot). The reduced DCDC3 voltage may be responsible for poor reliability at high MBUS and DRAM clock speeds too.

To sum it up. It would be great if Olimex better cooperated with the upstream U-Boot and provided the DRAM settings for Olimex boards instead of diverging from the defaults in the custom binary images. IANAL, but some people may even treat the custom DRAM settings tweaks as a sort of GPL violation, unless Olimex provides U-Boot sources somewhere nearby.