[U-Boot] [PATCH 0/3] arm: socpfpga: gen5 clean up ETH RST & PHY mode
Socfpga Gen5 uses ad-hoc code to unreset the ETH MACs and set their PHY mode.
Change this to use the designware_socfpga net driver and remove the old ad-hoc code.
Simon Goldschmidt (3): net: designware: socfpga: adapt to Gen5 arm: socfpga: gen5 enable designware_socfpga arm: socfpga: gen5: remove hacked ETH RST handling
.../mach-socfpga/include/mach/reset_manager.h | 2 - arch/arm/mach-socfpga/misc.c | 65 ------------------- arch/arm/mach-socfpga/misc_gen5.c | 44 +------------ configs/socfpga_arria5_defconfig | 3 + configs/socfpga_cyclone5_defconfig | 3 + configs/socfpga_dbm_soc1_defconfig | 3 + configs/socfpga_de0_nano_soc_defconfig | 3 + configs/socfpga_de10_nano_defconfig | 3 + configs/socfpga_de1_soc_defconfig | 3 + configs/socfpga_is1_defconfig | 3 + configs/socfpga_sockit_defconfig | 3 + configs/socfpga_socrates_defconfig | 3 + configs/socfpga_sr1500_defconfig | 3 + configs/socfpga_vining_fpga_defconfig | 3 + drivers/net/dwmac_socfpga.c | 14 ++-- 15 files changed, 43 insertions(+), 115 deletions(-)
This driver was written for Arria10, but it applies to Gen5, too.
The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed.
This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5.
Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required).
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
drivers/net/dwmac_socfpga.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 08fc9677c4..309da69647 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -27,6 +27,7 @@ struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; enum dwmac_type type; void *phy_intf; + u32 reg_shift; };
static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) @@ -63,6 +64,7 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) }
pdata->phy_intf = range + args.args[0]; + pdata->reg_shift = args.args[1];
/* * Sadly, the Altera DT bindings don't have SoC-specific compatibles, @@ -88,9 +90,11 @@ static int dwmac_socfpga_probe(struct udevice *dev) struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; struct reset_ctl_bulk reset_bulk; int ret; - u8 modereg; + u32 modereg; + u32 modemask;
- if (pdata->type == DWMAC_SOCFPGA_ARRIA10) { + if (pdata->type == DWMAC_SOCFPGA_ARRIA10 || + pdata->type == DWMAC_SOCFPGA_GEN5) { switch (edata->phy_interface) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -115,9 +119,9 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(&reset_bulk);
- clrsetbits_le32(pdata->phy_intf, - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, - modereg); + modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; + clrsetbits_le32(pdata->phy_intf, modemask, + modereg << pdata->reg_shift);
reset_release_bulk(&reset_bulk); }
Hi Marek,
Am 10.01.2019 um 20:49 schrieb Simon Goldschmidt:
This driver was written for Arria10, but it applies to Gen5, too.
The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed.
This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5.
Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required).
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
drivers/net/dwmac_socfpga.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 08fc9677c4..309da69647 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -27,6 +27,7 @@ struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; enum dwmac_type type; void *phy_intf;
u32 reg_shift; };
static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
@@ -63,6 +64,7 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) }
pdata->phy_intf = range + args.args[0];
pdata->reg_shift = args.args[1];
/*
- Sadly, the Altera DT bindings don't have SoC-specific compatibles,
@@ -88,9 +90,11 @@ static int dwmac_socfpga_probe(struct udevice *dev) struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; struct reset_ctl_bulk reset_bulk; int ret;
- u8 modereg;
- u32 modereg;
- u32 modemask;
- if (pdata->type == DWMAC_SOCFPGA_ARRIA10) {
- if (pdata->type == DWMAC_SOCFPGA_ARRIA10 ||
pdata->type == DWMAC_SOCFPGA_GEN5) {
I just checked: the Linux driver does not seem to have special handling for Gen5/Arria10/Stratix10. Since Gen5 and Arria10 now both work and the registers for Stratix10 seem the same as for Arria10, could we maybe drop this special handling?
That would mean we could drop this whole 'type' and the 'enum dwmac_type'...
Regards, Simon
switch (edata->phy_interface) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII:@@ -115,9 +119,9 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(&reset_bulk);
clrsetbits_le32(pdata->phy_intf,SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,modereg);
modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;clrsetbits_le32(pdata->phy_intf, modemask,modereg << pdata->reg_shift);reset_release_bulk(&reset_bulk); }
On 1/10/19 8:54 PM, Simon Goldschmidt wrote:
Hi Marek,
Am 10.01.2019 um 20:49 schrieb Simon Goldschmidt:
This driver was written for Arria10, but it applies to Gen5, too.
The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed.
This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5.
Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required).
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
drivers/net/dwmac_socfpga.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 08fc9677c4..309da69647 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -27,6 +27,7 @@ struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; enum dwmac_type type; void *phy_intf; + u32 reg_shift; }; static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) @@ -63,6 +64,7 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) } pdata->phy_intf = range + args.args[0]; + pdata->reg_shift = args.args[1]; /* * Sadly, the Altera DT bindings don't have SoC-specific compatibles, @@ -88,9 +90,11 @@ static int dwmac_socfpga_probe(struct udevice *dev) struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; struct reset_ctl_bulk reset_bulk; int ret; - u8 modereg; + u32 modereg; + u32 modemask; - if (pdata->type == DWMAC_SOCFPGA_ARRIA10) { + if (pdata->type == DWMAC_SOCFPGA_ARRIA10 || + pdata->type == DWMAC_SOCFPGA_GEN5) {
I just checked: the Linux driver does not seem to have special handling for Gen5/Arria10/Stratix10. Since Gen5 and Arria10 now both work and the registers for Stratix10 seem the same as for Arria10, could we maybe drop this special handling?
That would mean we could drop this whole 'type' and the 'enum dwmac_type'...
I seem to remember the register layout for selecting the PHY mode on Gen5 and Arria10 was different, please check the datasheets. Of course, the less special-casing, the better.
Am Do., 10. Jan. 2019, 21:38 hat Marek Vasut marex@denx.de geschrieben:
On 1/10/19 8:54 PM, Simon Goldschmidt wrote:
Hi Marek,
Am 10.01.2019 um 20:49 schrieb Simon Goldschmidt:
This driver was written for Arria10, but it applies to Gen5, too.
The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed.
This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5.
Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required).
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
drivers/net/dwmac_socfpga.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 08fc9677c4..309da69647 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -27,6 +27,7 @@ struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; enum dwmac_type type; void *phy_intf;
- u32 reg_shift; }; static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
@@ -63,6 +64,7 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) } pdata->phy_intf = range + args.args[0];
- pdata->reg_shift = args.args[1]; /*
- Sadly, the Altera DT bindings don't have SoC-specific
compatibles, @@ -88,9 +90,11 @@ static int dwmac_socfpga_probe(struct udevice *dev) struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; struct reset_ctl_bulk reset_bulk; int ret;
- u8 modereg;
- u32 modereg;
- u32 modemask;
- if (pdata->type == DWMAC_SOCFPGA_ARRIA10) {
- if (pdata->type == DWMAC_SOCFPGA_ARRIA10 ||
pdata->type == DWMAC_SOCFPGA_GEN5) {I just checked: the Linux driver does not seem to have special handling for Gen5/Arria10/Stratix10. Since Gen5 and Arria10 now both work and the registers for Stratix10 seem the same as for Arria10, could we maybe drop this special handling?
That would mean we could drop this whole 'type' and the 'enum dwmac_type'...
I seem to remember the register layout for selecting the PHY mode on Gen5 and Arria10 was different, please check the datasheets. Of course, the less special-casing, the better.
Yes, the register layout is different. But the reg_shift value takes care of that. Luckily, the bits have the same meaning even if the offset is different.
What remains is the special case for Stratix10. Looking at the Linux driver and the register descriptions, I think we can drop the special cases, but someone would need to test it on Stratix10...
Regards, Simon
On 1/10/19 9:42 PM, Simon Goldschmidt wrote:
Am Do., 10. Jan. 2019, 21:38 hat Marek Vasut <marex@denx.de mailto:marex@denx.de> geschrieben:
On 1/10/19 8:54 PM, Simon Goldschmidt wrote: > Hi Marek, > > Am 10.01.2019 um 20:49 schrieb Simon Goldschmidt: >> This driver was written for Arria10, but it applies to Gen5, too. >> >> The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the >> syscon bits are encoded in the same register, thus an offset is needed. >> >> This offset is already read from the devicetree, but for Arria10 it is >> always 0, which is probably why it has been ignored. By using this >> offset when writing the phy mode into the syscon regiter, we can use >> this driver to set the phy mode for both of the MACs on Gen5. >> >> Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift >> offset is required). >> >> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com <mailto:simon.k.r.goldschmidt@gmail.com>> >> --- >> >> drivers/net/dwmac_socfpga.c | 14 +++++++++----- >> 1 file changed, 9 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c >> index 08fc9677c4..309da69647 100644 >> --- a/drivers/net/dwmac_socfpga.c >> +++ b/drivers/net/dwmac_socfpga.c >> @@ -27,6 +27,7 @@ struct dwmac_socfpga_platdata { >> struct dw_eth_pdata dw_eth_pdata; >> enum dwmac_type type; >> void *phy_intf; >> + u32 reg_shift; >> }; >> static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) >> @@ -63,6 +64,7 @@ static int dwmac_socfpga_ofdata_to_platdata(struct >> udevice *dev) >> } >> pdata->phy_intf = range + args.args[0]; >> + pdata->reg_shift = args.args[1]; >> /* >> * Sadly, the Altera DT bindings don't have SoC-specific >> compatibles, >> @@ -88,9 +90,11 @@ static int dwmac_socfpga_probe(struct udevice *dev) >> struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; >> struct reset_ctl_bulk reset_bulk; >> int ret; >> - u8 modereg; >> + u32 modereg; >> + u32 modemask; >> - if (pdata->type == DWMAC_SOCFPGA_ARRIA10) { >> + if (pdata->type == DWMAC_SOCFPGA_ARRIA10 || >> + pdata->type == DWMAC_SOCFPGA_GEN5) { > > I just checked: the Linux driver does not seem to have special handling > for Gen5/Arria10/Stratix10. Since Gen5 and Arria10 now both work and the > registers for Stratix10 seem the same as for Arria10, could we maybe > drop this special handling? > > That would mean we could drop this whole 'type' and the 'enum > dwmac_type'... I seem to remember the register layout for selecting the PHY mode on Gen5 and Arria10 was different, please check the datasheets. Of course, the less special-casing, the better.Yes, the register layout is different. But the reg_shift value takes care of that. Luckily, the bits have the same meaning even if the offset is different.
Fantastic
What remains is the special case for Stratix10. Looking at the Linux driver and the register descriptions, I think we can drop the special cases, but someone would need to test it on Stratix10...
+CC Joyce.
Enable the socfpga specific designeware ethernet driver for all Gen5 and Arria10 defconfigs. To make it work, enable REGMAP and SYSCON, too.
This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga.
Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
configs/socfpga_arria5_defconfig | 3 +++ configs/socfpga_cyclone5_defconfig | 3 +++ configs/socfpga_dbm_soc1_defconfig | 3 +++ configs/socfpga_de0_nano_soc_defconfig | 3 +++ configs/socfpga_de10_nano_defconfig | 3 +++ configs/socfpga_de1_soc_defconfig | 3 +++ configs/socfpga_is1_defconfig | 3 +++ configs/socfpga_sockit_defconfig | 3 +++ configs/socfpga_socrates_defconfig | 3 +++ configs/socfpga_sr1500_defconfig | 3 +++ configs/socfpga_vining_fpga_defconfig | 3 +++ 11 files changed, 33 insertions(+)
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 0e5e74a621..15cc16b111 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -41,6 +41,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -59,6 +61,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index e8de0f5709..2a432d2007 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -41,6 +41,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -60,6 +62,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index b6f4f8a3dd..e7726dc3cc 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -54,6 +56,7 @@ CONFIG_MTD_DEVICE=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 9a89bb5d68..33a412d340 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_UBI=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -54,6 +56,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index db516891ba..662e895af2 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -37,6 +37,8 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -50,6 +52,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 5bed755723..d02bf1c6cf 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -37,6 +37,8 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y @@ -49,6 +51,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 682e58fdb8..97125efae4 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -38,6 +38,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 CONFIG_FPGA_SOCFPGA=y @@ -54,6 +56,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index abbbcb94d3..a1019d12fc 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -41,6 +41,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -60,6 +62,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 53f8d3c348..4ffce80793 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -42,6 +42,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y @@ -60,6 +62,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 97366cdfff..d4720e5580 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -42,6 +42,8 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 CONFIG_FPGA_SOCFPGA=y @@ -60,6 +62,7 @@ CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 3eba09dcb1..c3d4b815f1 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -47,6 +47,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -76,6 +78,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_SOCFPGA=y CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y
On 1/10/19 8:49 PM, Simon Goldschmidt wrote:
Enable the socfpga specific designeware ethernet driver for all Gen5 and Arria10 defconfigs. To make it work, enable REGMAP and SYSCON, too.
This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga.
Can the Gen5/A10 just "imply" those two options or can the DWMAC driver "select" those two options in Kconfig ?
Am Do., 10. Jan. 2019, 21:40 hat Marek Vasut marex@denx.de geschrieben:
On 1/10/19 8:49 PM, Simon Goldschmidt wrote:
Enable the socfpga specific designeware ethernet driver for all Gen5 and Arria10 defconfigs. To make it work, enable REGMAP and SYSCON, too.
This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga.
Can the Gen5/A10 just "imply" those two options or can the DWMAC driver "select" those two options in Kconfig ?
Hmm, I'll try that.
Regards, Simon
On 1/10/19 9:43 PM, Simon Goldschmidt wrote:
Am Do., 10. Jan. 2019, 21:40 hat Marek Vasut <marex@denx.de mailto:marex@denx.de> geschrieben:
On 1/10/19 8:49 PM, Simon Goldschmidt wrote: > Enable the socfpga specific designeware ethernet driver for all Gen5 > and Arria10 defconfigs. To make it work, enable REGMAP and SYSCON, > too. > > This is required to remove the hacky reset and phy mode handling in > arch/arm/mach-socfpga. Can the Gen5/A10 just "imply" those two options or can the DWMAC driver "select" those two options in Kconfig ?Hmm, I'll try that.
And if you get bored, you can imply as much common stuff from the defconfigs as possible ;-)
The 'designware_socfpga' ETH driver can now get the MACs out of reset via the socfpga reset driver and can set PHY mode via syscon.
This means we can now remove the ad-hoc code to do this from arch/arm/mach-socfpga.
Signed-off-by: Simon Goldschmdit simon.k.r.goldschmidt@gmail.com Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com ---
.../mach-socfpga/include/mach/reset_manager.h | 2 - arch/arm/mach-socfpga/misc.c | 65 ------------------- arch/arm/mach-socfpga/misc_gen5.c | 44 +------------ 3 files changed, 1 insertion(+), 110 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index d9e0b33c60..42beaecdd6 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -10,8 +10,6 @@ void reset_cpu(ulong addr);
void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); -int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, - const u8 phymode));
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 78fbe28724..e1adea143c 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -120,71 +120,6 @@ int arch_cpu_init(void) return 0; }
-#ifdef CONFIG_ETH_DESIGNWARE -static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) -{ - if (!phymode) - return -EINVAL; - - if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - return 0; - } - - if (!strcmp(phymode, "rgmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - return 0; - } - - if (!strcmp(phymode, "rmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - return 0; - } - - return -EINVAL; -} - -int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, - const u8 phymode)) -{ - const void *fdt = gd->fdt_blob; - struct fdtdec_phandle_args args; - const char *phy_mode; - u32 phy_modereg; - int nodes[2]; /* Max. two GMACs */ - int ret, count; - int i, node; - - count = fdtdec_find_aliases_for_id(fdt, "ethernet", - COMPAT_ALTERA_SOCFPGA_DWMAC, - nodes, ARRAY_SIZE(nodes)); - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", - "#reset-cells", 1, 0, - &args); - if (ret || (args.args_count != 1)) { - debug("GMAC%i: Failed to parse DT 'resets'!\n", i); - continue; - } - - phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); - ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); - if (ret) { - debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); - continue; - } - - resetfn(args.args[0], phy_modereg); - } - - return 0; -} -#endif - #ifndef CONFIG_SPL_BUILD static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 04f237d100..6e11ba6cb2 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -54,48 +54,6 @@ static Altera_desc altera_fpga[] = { }, };
-/* - * DesignWare Ethernet initialization - */ -#ifdef CONFIG_ETH_DESIGNWARE -static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode) -{ - u32 physhift, reset; - - if (of_reset_id == EMAC0_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; - reset = SOCFPGA_RESET(EMAC0); - } else if (of_reset_id == EMAC1_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; - reset = SOCFPGA_RESET(EMAC1); - } else { - printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); - return; - } - - /* configure to PHY interface select choosed */ - clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, - phymode << physhift); - - /* Release the EMAC controller from reset */ - socfpga_per_reset(reset, 0); -} - -static int socfpga_eth_reset(void) -{ - /* Put all GMACs into RESET state. */ - socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); - socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); - return socfpga_eth_reset_common(gen5_dwmac_reset); -}; -#else -static int socfpga_eth_reset(void) -{ - return 0; -}; -#endif - static const struct { const u16 pn; const char *name; @@ -178,7 +136,7 @@ int arch_misc_init(void) env_set("bootmode", bsel_str[bsel].mode); if (fpga_id >= 0) env_set("fpgatype", socfpga_fpga_model[fpga_id].var); - return socfpga_eth_reset(); + return 0; } #endif
On 1/10/19 8:49 PM, Simon Goldschmidt wrote:
The 'designware_socfpga' ETH driver can now get the MACs out of reset via the socfpga reset driver and can set PHY mode via syscon.
This means we can now remove the ad-hoc code to do this from arch/arm/mach-socfpga.
Signed-off-by: Simon Goldschmdit simon.k.r.goldschmidt@gmail.com Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
I very much like this patch, except for the dual SoB line.
Am Do., 10. Jan. 2019, 21:40 hat Marek Vasut marex@denx.de geschrieben:
On 1/10/19 8:49 PM, Simon Goldschmidt wrote:
The 'designware_socfpga' ETH driver can now get the MACs out of reset via the socfpga reset driver and can set PHY mode via syscon.
This means we can now remove the ad-hoc code to do this from arch/arm/mach-socfpga.
Signed-off-by: Simon Goldschmdit simon.k.r.goldschmidt@gmail.com Signed-off-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
I very much like this patch, except for the dual SoB line.
D'oh! The first one was may typo, the 2nd one was by patman.
Seems like I need a V2 anyway...
Regards, Simon
On 1/10/19 9:46 PM, Simon Goldschmidt wrote:
Am Do., 10. Jan. 2019, 21:40 hat Marek Vasut <marex@denx.de mailto:marex@denx.de> geschrieben:
On 1/10/19 8:49 PM, Simon Goldschmidt wrote: > The 'designware_socfpga' ETH driver can now get the MACs out of reset > via the socfpga reset driver and can set PHY mode via syscon. > > This means we can now remove the ad-hoc code to do this from > arch/arm/mach-socfpga. > > Signed-off-by: Simon Goldschmdit <simon.k.r.goldschmidt@gmail.com <mailto:simon.k.r.goldschmidt@gmail.com>> > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com <mailto:simon.k.r.goldschmidt@gmail.com>> I very much like this patch, except for the dual SoB line.D'oh! The first one was may typo, the 2nd one was by patman.
Seems like I need a V2 anyway...
I usually use git commit -sm "stuff" or git commit --amend -s
participants (2)
-
Marek Vasut -
Simon Goldschmidt