[U-Boot] mpc83xx: update LCRR register handling

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[U-Boot] [PATCH] OMAP3: Clean up...

Heiko Schocher

25 Aug 2009 25 Aug '09

11:05 a.m.

MPC8379E RM says (10-34): Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. So update this in code. Also define a LCRR mask for processors, which uses not all bits in the LCRR register (as for example mpc832x did).

Signed-off-by: Heiko Schocher hs@denx.de --- cpu/mpc83xx/cpu_init.c | 11 +++++++++-- include/mpc83xx.h | 5 +++++ 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index ea4f2af..b733fce 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -23,8 +23,8 @@ #include <common.h> #include <mpc83xx.h> #include <ioports.h> -#ifdef CONFIG_USB_EHCI_FSL #include <asm/io.h> +#ifdef CONFIG_USB_EHCI_FSL #include <usb/ehci-fsl.h> #endif

@@ -194,7 +194,14 @@ void cpu_init_f (volatile immap_t * im) im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));

/* LCRR - Clock Ratio Register (10.3.1.16) */ - im->lbus.lcrr = CONFIG_SYS_LCRR; + out_be32(&im->lbus.lcrr, ((in_be32(&im->lbus.lcrr) & ~LCRR_MASK) | \ + (CONFIG_SYS_LCRR & LCRR_MASK))); + /* MPC8379E RM 10-34 says after writting this register + * the register should be reread and an isync should be + * executed. + */ + in_be32(&im->lbus.lcrr); + isync();

/* Enable Time Base & Decrimenter ( so we will have udelay() )*/ im->sysconf.spcr |= SPCR_TBEN; diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 44115c9..41bb845 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -198,6 +198,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000

+#define LCRR_MASK 0x0003000f #elif defined(CONFIG_MPC8313) /* SICRL bits - MPC8313 specific */ #define SICRL_LBC 0x30000000 @@ -1200,6 +1201,10 @@

#define PEX_GCLK_RATIO 0x440

+#if !defined(LCRR_MASK) +#define LCRR_MASK 0xFFFFFFFF +#endif + #ifndef __ASSEMBLY__ struct pci_region; void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);

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Liu Dave-R63238

25 Aug 25 Aug

11:14 a.m.

...

MPC8379E RM says (10-34): Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. So update this in code. Also define a LCRR mask for processors, which uses not all bits in the LCRR register (as for example mpc832x did).

Signed-off-by: Heiko Schocher hs@denx.de

cpu/mpc83xx/cpu_init.c | 11 +++++++++-- include/mpc83xx.h | 5 +++++ 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index ea4f2af..b733fce 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -23,8 +23,8 @@ #include <common.h> #include <mpc83xx.h> #include <ioports.h> -#ifdef CONFIG_USB_EHCI_FSL #include <asm/io.h> +#ifdef CONFIG_USB_EHCI_FSL #include <usb/ehci-fsl.h> #endif

@@ -194,7 +194,14 @@ void cpu_init_f (volatile immap_t * im) im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));

/* LCRR - Clock Ratio Register (10.3.1.16) */

im->lbus.lcrr = CONFIG_SYS_LCRR;

out_be32(&im->lbus.lcrr, ((in_be32(&im->lbus.lcrr) &

~LCRR_MASK) | \
	(CONFIG_SYS_LCRR & LCRR_MASK)));
/* MPC8379E RM 10-34 says after writting this register
* the register should be reread and an isync should be
* executed.
*/
in_be32(&im->lbus.lcrr);

isync();

Hi Heiko,

It would be great if you guy can move this code to cpu_init_r.

If we change the local bus clock freq while the code is running from the local bus, it is not safe.

Thanks, Dave

Heiko Schocher

1:31 p.m.

New subject: [U-Boot] [PATCH v2] mpc83xx: update LCRR register handling

Signed-off-by: Heiko Schocher hs@denx.de ---

- added comment from DaveLiu. moved LCRR setting to cpu_init_r()

cpu/mpc83xx/cpu_init.c | 19 +++++++++++++++---- include/mpc83xx.h | 5 +++++ 2 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index ea4f2af..3ca57aa 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -23,8 +23,8 @@ #include <common.h> #include <mpc83xx.h> #include <ioports.h> -#ifdef CONFIG_USB_EHCI_FSL #include <asm/io.h> +#ifdef CONFIG_USB_EHCI_FSL #include <usb/ehci-fsl.h> #endif

@@ -193,9 +193,6 @@ void cpu_init_f (volatile immap_t * im) */ im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));

- /* LCRR - Clock Ratio Register (10.3.1.16) */ - im->lbus.lcrr = CONFIG_SYS_LCRR; - /* Enable Time Base & Decrimenter ( so we will have udelay() )*/ im->sysconf.spcr |= SPCR_TBEN;

@@ -329,8 +326,22 @@ void cpu_init_f (volatile immap_t * im)

int cpu_init_r (void) { + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ +#endif + + /* LCRR - Clock Ratio Register (10.3.1.16) */ + out_be32(&im->lbus.lcrr, ((in_be32(&im->lbus.lcrr) & ~LCRR_MASK) | \ + (CONFIG_SYS_LCRR & LCRR_MASK))); + /* MPC8379E RM 10-34 says after writting this register + * the register should be reread and an isync should be + * executed. + */ + in_be32(&im->lbus.lcrr); + isync(); + +#ifdef CONFIG_QE qe_init(qe_base); qe_reset(); #endif diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 44115c9..41bb845 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -198,6 +198,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000

+#define LCRR_MASK 0x0003000f #elif defined(CONFIG_MPC8313) /* SICRL bits - MPC8313 specific */ #define SICRL_LBC 0x30000000 @@ -1200,6 +1201,10 @@

#define PEX_GCLK_RATIO 0x440

+#if !defined(LCRR_MASK) +#define LCRR_MASK 0xFFFFFFFF +#endif + #ifndef __ASSEMBLY__ struct pci_region; void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);

-- 1.6.0.6 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Liu Dave-R63238

2:19 p.m.

New subject: [U-Boot] [PATCH v2] mpc83xx: update LCRR register handling

...

-----Original Message----- From: Heiko Schocher [mailto:hs@denx.de] Sent: Tuesday, August 25, 2009 7:32 PM To: Liu Dave-R63238 Cc: Phillips Kim-R1AAHA; U-Boot user list Subject: [PATCH v2] mpc83xx: update LCRR register handling

MPC8379E RM says (10-34): Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. So update this in code. Also define a LCRR mask for processors, which uses not all bits in the LCRR register (as for example mpc832x did).

Signed-off-by: Heiko Schocher hs@denx.de

Acked-by: Dave Liu daveliu@freescale.com

Kim Phillips

5:39 p.m.

New subject: [U-Boot] [PATCH v2] mpc83xx: update LCRR register handling

On Tue, 25 Aug 2009 13:31:34 +0200 Heiko Schocher hs@denx.de wrote:

...

MPC8379E RM says (10-34): Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. So update this in code. Also define a LCRR mask for processors, which uses not all bits in the LCRR register (as for example mpc832x did).

Signed-off-by: Heiko Schocher hs@denx.de

thanks for this Heiko...some comments:

...

int cpu_init_r (void) {

volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;

#ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ +#endif
/* LCRR - Clock Ratio Register (10.3.1.16) */

out_be32(&im->lbus.lcrr, ((in_be32(&im->lbus.lcrr) & ~LCRR_MASK) | \
	(CONFIG_SYS_LCRR & LCRR_MASK)));

...

/* MPC8379E RM 10-34 says after writting this register
* the register should be reread and an isync should be
* executed.
*/
in_be32(&im->lbus.lcrr);

isync();

in_be32 and friends does the isync for you. In fact, you can probably do it in one fell swoop by using setbits/clrsetbits?

...

+++ b/include/mpc83xx.h @@ -198,6 +198,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000

+#define LCRR_MASK 0x0003000f

I thought we discussed this - shouldn't this be 0x7fffffff?

Kim

Heiko Schocher

26 Aug 26 Aug

8:28 a.m.

New subject: [U-Boot] [PATCH v2] mpc83xx: update LCRR register handling

Hello Kim,

Kim Phillips wrote:

...

On Tue, 25 Aug 2009 13:31:34 +0200 Heiko Schocher hs@denx.de wrote:

...
MPC8379E RM says (10-34): Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. So update this in code. Also define a LCRR mask for processors, which uses not all bits in the LCRR register (as for example mpc832x did).

Signed-off-by: Heiko Schocher hs@denx.de

thanks for this Heiko...some comments:

...
int cpu_init_r (void) {

volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;

#ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ +#endif
/* LCRR - Clock Ratio Register (10.3.1.16) */

out_be32(&im->lbus.lcrr, ((in_be32(&im->lbus.lcrr) & ~LCRR_MASK) | \
	(CONFIG_SYS_LCRR & LCRR_MASK)));
..

...
/* MPC8379E RM 10-34 says after writting this register
* the register should be reread and an isync should be
* executed.
*/
in_be32(&im->lbus.lcrr);

isync();
in_be32 and friends does the isync for you. In fact, you can probably do it in one fell swoop by using setbits/clrsetbits?

Argh, of course. But I need the in_be32() for rereading the register again, as the RM says.

...

...
+++ b/include/mpc83xx.h @@ -198,6 +198,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000

+#define LCRR_MASK 0x0003000f

I thought we discussed this - shouldn't this be 0x7fffffff?

Hmm.. as I did this mpc832x specific, in my version it is not possible to set reserved 0 bits to 1 ... Ah, I reread your mail again, you wrote:

...

I guess I have a shoot-yourself-in-the-foot philosophy - you're free to find out what happens when setting reserved bits to 1 if you so wish. u-boot protects you up to the point where you veer off into using hardcoded values instead of using the predefined CONFIG_SYS_SCCR_* macros.

I think you mean the LCRR_* defines ...

Hmm... so we can say: "feel free to find out what happens, if setting reserved 1 bits to 0! and can drop this patch" ...

Hmmm, you can use for the mpc832x for example the LCRR_BUFCMDC_1, what is a valid define for mpc83xx, but it is not valid for the mpc832x ... so It is not the problem, that a u-boot user use hard- coded values, instead this processor don;t support all bits valid for other mpc83xx processors.

So I tend to protect an u-boot user from doing wrong things, (setting reserved 0/1 bits to 1/0) if it is easy possible ...

bye Heiko

-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Kim Phillips

27 Aug 27 Aug

12:36 a.m.

New subject: [U-Boot] [PATCH v2] mpc83xx: update LCRR register handling

On Wed, 26 Aug 2009 08:28:37 +0200 Heiko Schocher hs@denx.de wrote:

...

Hello Kim,

Kim Phillips wrote:

...
On Tue, 25 Aug 2009 13:31:34 +0200 Heiko Schocher hs@denx.de wrote:

...
/* MPC8379E RM 10-34 says after writting this register
* the register should be reread and an isync should be
* executed.
*/
in_be32(&im->lbus.lcrr);

isync();
in_be32 and friends does the isync for you. In fact, you can probably do it in one fell swoop by using setbits/clrsetbits?
Argh, of course. But I need the in_be32() for rereading the register again, as the RM says.

right on

...

...
...
+++ b/include/mpc83xx.h @@ -198,6 +198,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000

+#define LCRR_MASK 0x0003000f

I thought we discussed this - shouldn't this be 0x7fffffff?

Hmm.. as I did this mpc832x specific, in my version it is not possible to set reserved 0 bits to 1 ... Ah, I reread your mail again, you wrote:

...
I guess I have a shoot-yourself-in-the-foot philosophy - you're free to find out what happens when setting reserved bits to 1 if you so wish. u-boot protects you up to the point where you veer off into using hardcoded values instead of using the predefined CONFIG_SYS_SCCR_* macros.

I think you mean the LCRR_* defines ...

yes, thank you

...

Hmm... so we can say: "feel free to find out what happens, if setting reserved 1 bits to 0! and can drop this patch" ...

precisely - I'd rather have this kept in the board config file if at all possible - that's how other 83xx boards do it atm.

...

Hmmm, you can use for the mpc832x for example the LCRR_BUFCMDC_1, what is a valid define for mpc83xx, but it is not valid for the mpc832x ... so It is not the problem, that a u-boot user use hard- coded values, instead this processor don;t support all bits valid for other mpc83xx processors.

So I tend to protect an u-boot user from doing wrong things, (setting reserved 0/1 bits to 1/0) if it is easy possible ...

right but:

o LCRR_PDYP, granted dangerous in your case, is obviously a writeable bit (not read-only), and documented as such in later documentation. In fact, there are no non-writeable bits in LCRR.

o the user loses visibility into what is going on if they decide to drop/add sensitive bits such as LCRR_DBYP in their board's CONFIG_SYS_LCRR settings, and there's a mask lurking in the background.

o let's be practical here - in a board port, LCRR settings have to be paid attention to, no matter what hidden behaviours or new bits there are lying underneath - perhaps the form of 'protection' you seek is in the form of a comment in the code?

Kim

Heiko Schocher

8:20 a.m.

New subject: [U-Boot] [PATCH v3] mpc83xx: update LCRR register handling

Signed-off-by: Heiko Schocher hs@denx.de --- changes since v1: - added comment from DaveLiu. moved LCRR setting to cpu_init_r()

changes since v2: - added comment from Kim Phillips changed LCRR_MASK to 0x7fffffff use clrsetbits()

cpu/mpc83xx/cpu_init.c | 17 +++++++++++++---- include/mpc83xx.h | 5 +++++ 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index ea4f2af..c51924f 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -23,8 +23,8 @@ #include <common.h> #include <mpc83xx.h> #include <ioports.h> -#ifdef CONFIG_USB_EHCI_FSL #include <asm/io.h> +#ifdef CONFIG_USB_EHCI_FSL #include <usb/ehci-fsl.h> #endif

@@ -193,9 +193,6 @@ void cpu_init_f (volatile immap_t * im) */ im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));

- /* LCRR - Clock Ratio Register (10.3.1.16) */ - im->lbus.lcrr = CONFIG_SYS_LCRR; - /* Enable Time Base & Decrimenter ( so we will have udelay() )*/ im->sysconf.spcr |= SPCR_TBEN;

@@ -329,8 +326,20 @@ void cpu_init_f (volatile immap_t * im)

int cpu_init_r (void) { + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ +#endif + + /* LCRR - Clock Ratio Register (10.3.1.16) */ + clrsetbits_be32(&im->lbus.lcrr, LCRR_MASK, CONFIG_SYS_LCRR); + /* MPC8379E RM 10-34 says after writting this register + * the register should be reread and an isync should be + * executed. + */ + in_be32(&im->lbus.lcrr); + +#ifdef CONFIG_QE qe_init(qe_base); qe_reset(); #endif diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 44115c9..15440b5 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -198,6 +198,7 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000

+#define LCRR_MASK 0x7fffffff #elif defined(CONFIG_MPC8313) /* SICRL bits - MPC8313 specific */ #define SICRL_LBC 0x30000000 @@ -1200,6 +1201,10 @@

#define PEX_GCLK_RATIO 0x440

+#if !defined(LCRR_MASK) +#define LCRR_MASK 0xFFFFFFFF +#endif + #ifndef __ASSEMBLY__ struct pci_region; void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);

-- 1.6.0.6 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Jerry Van Baren

1:41 p.m.

New subject: [U-Boot] [PATCH v3] mpc83xx: update LCRR register handling

Hi Heiko,

One minor critique, I had problems parsing the comment:

Heiko Schocher wrote:

...

MPC8379E RM says (10-34): Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. So update this in code. Also define a LCRR mask for processors, which uses not all bits

^^^^^^^^^^^^^^^^^^^^^^^ Suggested change: Also define a LCRR mask for processors to prevent setting any reserved bits in the LCRR register (as, for example, mpc832x did).

...

in the LCRR register (as for example mpc832x did).

Signed-off-by: Heiko Schocher hs@denx.de

Thanks, gvb

Kim Phillips

10:53 p.m.

New subject: [U-Boot] [PATCH v3] mpc83xx: update LCRR register handling

On Thu, 27 Aug 2009 08:20:35 +0200 Heiko Schocher hs@denx.de wrote:

...

MPC8379E RM says (10-34): Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. So update this in code. Also define a LCRR mask for processors, which uses not all bits in the LCRR register (as for example mpc832x did).

Signed-off-by: Heiko Schocher hs@denx.de

changes since v1:

added comment from DaveLiu. moved LCRR setting to cpu_init_r()

changes since v2:

added comment from Kim Phillips changed LCRR_MASK to 0x7fffffff use clrsetbits()

Heiko - let's go with the SCCR approach of setting bits in the LCRR, and have board config files only specify values for fields they're modifying from the reset value for their processor (this can be extended to 85xx-world).

Kim

Kumar Gala

16 Sep 16 Sep

6:51 a.m.

New subject: [U-Boot] [PATCH v3] mpc83xx: update LCRR register handling

On Aug 27, 2009, at 3:53 PM, Kim Phillips wrote:

...

On Thu, 27 Aug 2009 08:20:35 +0200 Heiko Schocher hs@denx.de wrote:

...
MPC8379E RM says (10-34): Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. So update this in code. Also define a LCRR mask for processors, which uses not all bits in the LCRR register (as for example mpc832x did).

Signed-off-by: Heiko Schocher hs@denx.de

changes since v1:

added comment from DaveLiu. moved LCRR setting to

cpu_init_r()

changes since v2:

added comment from Kim Phillips changed LCRR_MASK to 0x7fffffff use clrsetbits()

Heiko - let's go with the SCCR approach of setting bits in the LCRR, and have board config files only specify values for fields they're modifying from the reset value for their processor (this can be extended to 85xx-world).

Did you guys ever come to resolution on this? Realizing we have same issue on 85xx & 86xx (we dont actually set LCRR at all in cpu/ code for 85xx or 86xx.)

- k

Kim Phillips

26 Sep 26 Sep

1:19 a.m.

New subject: [U-Boot] [PATCH] mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields (was: Re: [PATCH v3] mpc83xx: update LCRR register handling)

On Tue, 15 Sep 2009 23:51:31 -0500 Kumar Gala galak@kernel.crashing.org wrote:

...

On Aug 27, 2009, at 3:53 PM, Kim Phillips wrote:

...
Heiko - let's go with the SCCR approach of setting bits in the LCRR, and have board config files only specify values for fields they're modifying from the reset value for their processor (this can be extended to 85xx-world).

Did you guys ever come to resolution on this? Realizing we have same issue on 85xx & 86xx (we dont actually set LCRR at all in cpu/ code for 85xx or 86xx.)

this should probably be extended to SICRH, SICRL, etc., but how's this:?

...

From 15d01649e403ec7da20f5fdd25b8d2c1bccb6a8d Mon Sep 17 00:00:00 2001

From: Kim Phillips kim.phillips@freescale.com Date: Fri, 25 Sep 2009 18:07:29 -0500 Subject: [PATCH] mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields

some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM.

Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file.

also start to use i/o accessors.

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 5c930d3..95dbc76 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -23,8 +23,8 @@ #include <common.h> #include <mpc83xx.h> #include <ioports.h> -#ifdef CONFIG_USB_EHCI_FSL #include <asm/io.h> +#ifdef CONFIG_USB_EHCI_FSL #include <usb/ehci-fsl.h> #endif

@@ -63,149 +63,192 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) { - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* system performance tweaking */ - -#ifdef CONFIG_SYS_ACR_PIPE_DEP - /* Arbiter pipeline depth */ - im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); + __be32 acr_mask = +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ + (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | #endif - -#ifdef CONFIG_SYS_ACR_RPTCNT - /* Arbiter repeat count */ - im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ + (ACR_RPTCNT << ACR_RPTCNT_SHIFT) | #endif - + 0; + __be32 acr_val = +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ + (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ + (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | +#endif + 0; + __be32 spcr_mask = +#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ + (SPCR_OPT << SPCR_OPT_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ + (SPCR_TSECEP << SPCR_TSECEP_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ + (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ + (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | +#endif + 0; + __be32 spcr_val = #ifdef CONFIG_SYS_SPCR_OPT - /* Optimize transactions between CSB and other devices */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | - (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); + (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) | #endif - -#ifdef CONFIG_SYS_SPCR_TSECEP - /* all eTSEC's Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | - (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT); +#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ + (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) | #endif - -#ifdef CONFIG_SYS_SPCR_TSEC1EP - /* TSEC1 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | - (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); +#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ + (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | #endif - -#ifdef CONFIG_SYS_SPCR_TSEC2EP - /* TSEC2 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | - (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); +#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ + (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_ENCCM - /* Encryption clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | - (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT); + 0; + __be32 sccr_mask = +#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ + (SCCR_ENCCM << SCCR_ENCCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_PCICM - /* PCI & DMA clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | - (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT); +#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ + (SCCR_PCICM << SCCR_PCICM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSECCM - /* all TSEC's clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) | - (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ + (SCCR_TSECCM << SCCR_TSECCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC1CM - /* TSEC1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | - (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC2CM - /* TSEC2 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | - (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC1ON - /* TSEC1 clock switch */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | - (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ + (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC2ON - /* TSEC2 clock switch */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | - (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ + (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_USBMPHCM - /* USB MPH clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | - (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); +#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ + (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_USBDRCM - /* USB DR clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | - (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT); +#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_SATACM - /* SATA controller clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) | - (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT); +#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (SCCR_SATACM << SCCR_SATACM_SHIFT) | +#endif + 0; + __be32 sccr_val = +#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ + (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ + (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ + (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ + (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ + (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ + (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | +#endif + 0; + __be32 lcrr_mask = +#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ + LCRR_DBYP | +#endif +#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */ + LCRR_EADC | +#endif +#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ + LCRR_CLKDIV | #endif + 0; + __be32 lcrr_val = +#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ + CONFIG_SYS_LCRR_DBYP | +#endif +#ifdef CONFIG_SYS_LCRR_EADC + CONFIG_SYS_LCRR_EADC | +#endif +#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ + CONFIG_SYS_LCRR_CLKDIV | +#endif + 0; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* system performance tweaking */ + clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); + + clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); + + clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);

/* RSR - Reset Status Register - clear all status (4.6.1.3) */ - gd->reset_status = im->reset.rsr; - im->reset.rsr = ~(RSR_RES); + gd->reset_status = __raw_readl(&im->reset.rsr); + __raw_writel(~(RSR_RES), &im->reset.rsr);

/* AER - Arbiter Event Register - store status */ - gd->arbiter_event_attributes = im->arbiter.aeatr; - gd->arbiter_event_address = im->arbiter.aeadr; + gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); + gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);

/* * RMR - Reset Mode Register * contains checkstop reset enable (4.6.1.4) */ - im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT)); + __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);

- /* LCRR - Clock Ratio Register (10.3.1.16) */ - im->lbus.lcrr = CONFIG_SYS_LCRR; + /* LCRR - Clock Ratio Register (10.3.1.16) + * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description + */ + clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val); + __raw_readl(&im->lbus.lcrr); + isync();

- /* Enable Time Base & Decrimenter ( so we will have udelay() )*/ - im->sysconf.spcr |= SPCR_TBEN; + /* Enable Time Base & Decrementer ( so we will have udelay() )*/ + setbits_be32(&im->sysconf.spcr, SPCR_TBEN);

/* System General Purpose Register */ #ifdef CONFIG_SYS_SICRH #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ - im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH; + __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, + &im->sysconf.sicrh); #else - im->sysconf.sicrh = CONFIG_SYS_SICRH; + __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh); #endif #endif #ifdef CONFIG_SYS_SICRL - im->sysconf.sicrl = CONFIG_SYS_SICRL; + __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); #endif - /* DDR control driver register */ -#ifdef CONFIG_SYS_DDRCDR - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; +#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */ + __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); #endif - /* Output buffer impedance register */ -#ifdef CONFIG_SYS_OBIR - im->sysconf.obir = CONFIG_SYS_OBIR; +#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */ + __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); #endif

#ifdef CONFIG_QE @@ -308,7 +351,7 @@ void cpu_init_f (volatile immap_t * im)

/* Wait for clock to stabilize */ do { - temp = in_be32(&ehci->control); + temp = __raw_readl(&ehci->control); udelay(1000); } while (!(temp & PHY_CLK_VALID)); #endif diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 76b7894..5927e76 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -216,7 +216,8 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 84cc9fa..8eaff5d 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -182,7 +182,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000

/* diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c40d3d3..356586c 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -170,7 +170,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000

/* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f16616c..f17f9c7 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -159,7 +159,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000

/* diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 9b2d25a..6361c45 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -206,7 +206,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000

/* diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 3b4e344..eaa59fd 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -317,7 +317,8 @@ boards, we say we have two, but don't display a message if we find only one. */ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000

#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index b072e84..859705a 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -185,7 +185,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000

/* diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index cb0535c..6cee78a 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -177,7 +177,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000

/* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index a190a50..abeb6a2 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -220,7 +220,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000

/* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 89fafe7..7ef92f7 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -243,7 +243,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000

/* diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 9835567..f8b016f 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -137,7 +137,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000

/* LB sdram refresh timer, about 6us */ diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 866ff17..f68d834 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -111,7 +111,9 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index da08b7c..4c909e6 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -52,7 +52,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8

/* board pre init: do not call, nothing to do */ #undef CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 79d8638..bec08da 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -170,7 +170,9 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4

/* * Init Local Bus Memory Controller: diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e961bb3..651deb5 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -182,7 +182,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000

#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 5304ec9..d0690fe 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -178,7 +178,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000

#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */

-- 1.6.4.4

Heiko Schocher

12:37 p.m.

New subject: [U-Boot] [PATCH] mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields

Hello Kim,

Kim Phillips wrote:

...

On Tue, 15 Sep 2009 23:51:31 -0500 Kumar Gala galak@kernel.crashing.org wrote:

...
On Aug 27, 2009, at 3:53 PM, Kim Phillips wrote:

...
Heiko - let's go with the SCCR approach of setting bits in the LCRR, and have board config files only specify values for fields they're modifying from the reset value for their processor (this can be extended to 85xx-world).

Did you guys ever come to resolution on this? Realizing we have same issue on 85xx & 86xx (we dont actually set LCRR at all in cpu/ code for 85xx or 86xx.)

this should probably be extended to SICRH, SICRL, etc., but how's this:?

...
From 15d01649e403ec7da20f5fdd25b8d2c1bccb6a8d Mon Sep 17 00:00:00 2001

From: Kim Phillips kim.phillips@freescale.com Date: Fri, 25 Sep 2009 18:07:29 -0500 Subject: [PATCH] mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields

some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM.

Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file.

also start to use i/o accessors.

Signed-off-by: Kim Phillips kim.phillips@freescale.com

cpu/mpc83xx/cpu_init.c | 255 ++++++++++++++++++++++++----------------- include/configs/MPC8313ERDB.h | 3 +- include/configs/MPC8315ERDB.h | 3 +- include/configs/MPC8323ERDB.h | 3 +- include/configs/MPC832XEMDS.h | 3 +- include/configs/MPC8349EMDS.h | 3 +- include/configs/MPC8349ITX.h | 3 +- include/configs/MPC8360EMDS.h | 3 +- include/configs/MPC8360ERDK.h | 3 +- include/configs/MPC837XEMDS.h | 3 +- include/configs/MPC837XERDB.h | 3 +- include/configs/MVBLM7.h | 3 +- include/configs/SIMPC8313.h | 4 +- include/configs/TQM834x.h | 3 +- include/configs/kmeter1.h | 4 +- include/configs/sbc8349.h | 3 +- include/configs/vme8349.h | 3 +- 17 files changed, 183 insertions(+), 122 deletions(-)

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 5c930d3..95dbc76 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -23,8 +23,8 @@ #include <common.h> #include <mpc83xx.h> #include <ioports.h> -#ifdef CONFIG_USB_EHCI_FSL #include <asm/io.h> +#ifdef CONFIG_USB_EHCI_FSL #include <usb/ehci-fsl.h> #endif

@@ -63,149 +63,192 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) {

/* Pointer is writable since we allocated a register for it */

[...]

...

/* LCRR - Clock Ratio Register (10.3.1.16) */

im->lbus.lcrr = CONFIG_SYS_LCRR;
/* LCRR - Clock Ratio Register (10.3.1.16)
* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
*/
clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);

__raw_readl(&im->lbus.lcrr);

isync();

Hmm.. shouldn;t this be done when running from RAM, as DaveLiu suggested?

bye Heiko

-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Kim Phillips

27 Sep 27 Sep

3:46 a.m.

New subject: [U-Boot] [PATCH] mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields

On Sat, 26 Sep 2009 12:37:40 +0200 Heiko Schocher hs@denx.de wrote:

...

Kim Phillips wrote:

...
/* LCRR - Clock Ratio Register (10.3.1.16) */

im->lbus.lcrr = CONFIG_SYS_LCRR;
/* LCRR - Clock Ratio Register (10.3.1.16)
* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
*/
clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);

__raw_readl(&im->lbus.lcrr);

isync();
Hmm.. shouldn;t this be done when running from RAM, as DaveLiu suggested?

oh, I suppose so ;). here's v2:

From: Kim Phillips kim.phillips@freescale.com Date: Fri, 25 Sep 2009 18:19:44 -0500 Subject: [PATCH] mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields

some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM.

also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified.

also start to use i/o accessors.

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 5c930d3..cd69773 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -23,8 +23,8 @@ #include <common.h> #include <mpc83xx.h> #include <ioports.h> -#ifdef CONFIG_USB_EHCI_FSL #include <asm/io.h> +#ifdef CONFIG_USB_EHCI_FSL #include <usb/ehci-fsl.h> #endif

@@ -63,149 +63,163 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) { - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* system performance tweaking */ - -#ifdef CONFIG_SYS_ACR_PIPE_DEP - /* Arbiter pipeline depth */ - im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); + __be32 acr_mask = +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ + (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | #endif - -#ifdef CONFIG_SYS_ACR_RPTCNT - /* Arbiter repeat count */ - im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ + (ACR_RPTCNT << ACR_RPTCNT_SHIFT) | #endif - + 0; + __be32 acr_val = +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ + (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ + (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | +#endif + 0; + __be32 spcr_mask = +#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ + (SPCR_OPT << SPCR_OPT_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ + (SPCR_TSECEP << SPCR_TSECEP_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ + (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | +#endif +#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ + (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | +#endif + 0; + __be32 spcr_val = #ifdef CONFIG_SYS_SPCR_OPT - /* Optimize transactions between CSB and other devices */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | - (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); + (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) | #endif - -#ifdef CONFIG_SYS_SPCR_TSECEP - /* all eTSEC's Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | - (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT); +#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ + (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) | #endif - -#ifdef CONFIG_SYS_SPCR_TSEC1EP - /* TSEC1 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | - (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); +#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ + (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | #endif - -#ifdef CONFIG_SYS_SPCR_TSEC2EP - /* TSEC2 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | - (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); +#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ + (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_ENCCM - /* Encryption clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | - (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT); + 0; + __be32 sccr_mask = +#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ + (SCCR_ENCCM << SCCR_ENCCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_PCICM - /* PCI & DMA clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | - (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT); +#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ + (SCCR_PCICM << SCCR_PCICM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSECCM - /* all TSEC's clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) | - (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ + (SCCR_TSECCM << SCCR_TSECCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC1CM - /* TSEC1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | - (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC2CM - /* TSEC2 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | - (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC1ON - /* TSEC1 clock switch */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | - (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ + (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_TSEC2ON - /* TSEC2 clock switch */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | - (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); +#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ + (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_USBMPHCM - /* USB MPH clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | - (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); +#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ + (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_USBDRCM - /* USB DR clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | - (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT); +#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | #endif - -#ifdef CONFIG_SYS_SCCR_SATACM - /* SATA controller clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) | - (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT); +#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (SCCR_SATACM << SCCR_SATACM_SHIFT) | +#endif + 0; + __be32 sccr_val = +#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ + (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) | #endif +#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ + (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ + (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ + (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ + (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ + (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | +#endif + 0; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* system performance tweaking */ + clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); + + clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); + + clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);

/* * RMR - Reset Mode Register * contains checkstop reset enable (4.6.1.4) */ - im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT)); - - /* LCRR - Clock Ratio Register (10.3.1.16) */ - im->lbus.lcrr = CONFIG_SYS_LCRR; + __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);

#ifdef CONFIG_QE @@ -308,7 +322,7 @@ void cpu_init_f (volatile immap_t * im)

/* Wait for clock to stabilize */ do { - temp = in_be32(&ehci->control); + temp = __raw_readl(&ehci->control); udelay(1000); } while (!(temp & PHY_CLK_VALID)); #endif @@ -317,6 +331,40 @@ void cpu_init_f (volatile immap_t * im)

int cpu_init_r (void) { + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; +#ifdef CONFIG_QE + uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ +#endif + __be32 lcrr_mask = +#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ + LCRR_DBYP | +#endif +#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */ + LCRR_EADC | +#endif +#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ + LCRR_CLKDIV | +#endif + 0; + __be32 lcrr_val = +#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ + CONFIG_SYS_LCRR_DBYP | +#endif +#ifdef CONFIG_SYS_LCRR_EADC + CONFIG_SYS_LCRR_EADC | +#endif +#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ + CONFIG_SYS_LCRR_CLKDIV | +#endif + 0; + + /* LCRR - Clock Ratio Register (10.3.1.16) + * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description + */ + clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val); + __raw_readl(&im->lbus.lcrr); + isync(); + #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ qe_init(qe_base); diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 76b7894..5927e76 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -216,7 +216,8 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 84cc9fa..8eaff5d 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -182,7 +182,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000

#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 62cf13b..8520155 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -185,7 +185,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000

/* * Init Local Bus Memory Controller: diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6f574ca..bf7cf82 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -197,7 +197,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000

#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */

-- 1.6.3

Kim Phillips

3:54 a.m.

New subject: [U-Boot] [PATCH] mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields

On Sat, 26 Sep 2009 20:46:42 -0500 Kim Phillips kim.phillips@freescale.com wrote:

...

On Sat, 26 Sep 2009 12:37:40 +0200 Heiko Schocher hs@denx.de wrote:

...
Kim Phillips wrote:

...
/* LCRR - Clock Ratio Register (10.3.1.16) */

im->lbus.lcrr = CONFIG_SYS_LCRR;
/* LCRR - Clock Ratio Register (10.3.1.16)
* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
*/
clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);

__raw_readl(&im->lbus.lcrr);

isync();
Hmm.. shouldn;t this be done when running from RAM, as DaveLiu suggested?
oh, I suppose so ;). here's v2:

and now v3 (I had left a qe_base redefinition in v2):

...

From f852b9638cc3f6d52ea0fe42adc277850e0ca359 Mon Sep 17 00:00:00 2001

From: Kim Phillips kim.phillips@freescale.com Date: Fri, 25 Sep 2009 18:19:44 -0500 Subject: [PATCH] mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields

some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM.

also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified.

also start to use i/o accessors.

#ifdef CONFIG_QE @@ -308,7 +322,7 @@ void cpu_init_f (volatile immap_t * im)

#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */

-- 1.6.3

Detlev Zundel

27 Aug 27 Aug

1:11 p.m.

New subject: [U-Boot] [PATCH v2] mpc83xx: update LCRR register handling

Hi Kim,

...

o LCRR_PDYP, granted dangerous in your case, is obviously a writeable bit (not read-only), and documented as such in later documentation. In fact, there are no non-writeable bits in LCRR.

Well, "reserved" != "non-writable" (usually there is a comment that writing reserved bits produces undefined behaviour) so I agree with Heiko that as long the documentation that we have access to, designates bits as reserved, it makes sense to have such a mask.

...

o the user loses visibility into what is going on if they decide to drop/add sensitive bits such as LCRR_DBYP in their board's CONFIG_SYS_LCRR settings, and there's a mask lurking in the background.

o let's be practical here - in a board port, LCRR settings have to be paid attention to, no matter what hidden behaviours or new bits there are lying underneath - perhaps the form of 'protection' you seek is in the form of a comment in the code?

So what is it that you propose? That Heiko uses a LCRR in his board config (over-)writing reserved bits?

Cheers Detlev

-- vi vi vi - the roman numeral of the beast. -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu@denx.de

Kim Phillips

10:49 p.m.

New subject: [U-Boot] [PATCH v2] mpc83xx: update LCRR register handling

On Thu, 27 Aug 2009 13:11:25 +0200 Detlev Zundel dzu@denx.de wrote:

...

Hi Kim,

...
o LCRR_PDYP, granted dangerous in your case, is obviously a writeable bit (not read-only), and documented as such in later documentation. In fact, there are no non-writeable bits in LCRR.

Well, "reserved" != "non-writable" (usually there is a comment that writing reserved bits produces undefined behaviour) so I agree with Heiko that as long the documentation that we have access to, designates bits as reserved, it makes sense to have such a mask.

I think we should allow board-configurable writes to the DBYP bit, which is documented as "reserved" on some 83xx, on the 83xx parts that /do/ implement it. So instead of having a mask, perhaps setting absolute values for CONFIG_SYS_LCRR should be replaced with a better scheme that allows board configs to just set LCRR bits by field, such as what the SCCR setting code does. I.e, deprecate CONFIG_SYS_LCRR and replace with individually-specified CONFIG_SYS_LCRR_{CLKDIV,EADC,ECL,BUDCMDC,DBYP} values.

This will allow the reserved bits, whether 1 on reset or not, to be preserved across all 83xx (and 85xx for that matter).

...

...
o the user loses visibility into what is going on if they decide to drop/add sensitive bits such as LCRR_DBYP in their board's CONFIG_SYS_LCRR settings, and there's a mask lurking in the background.

o let's be practical here - in a board port, LCRR settings have to be paid attention to, no matter what hidden behaviours or new bits there are lying underneath - perhaps the form of 'protection' you seek is in the form of a comment in the code?

So what is it that you propose? That Heiko uses a LCRR in his board config (over-)writing reserved bits?

that's what other boards do (like the 8323erdb), but I do see the problem for the new board porter - they don't see the bit in their documentation, so they omit it.

but I presume the above fix will allow Heiko and other new board porters happy?

I'll send a patch out this weekend unless someone beats me to it.

Kim

Detlev Zundel

28 Aug 28 Aug

12:36 p.m.

New subject: [U-Boot] [PATCH v2] mpc83xx: update LCRR register handling

Hi Kim,

...

On Thu, 27 Aug 2009 13:11:25 +0200 Detlev Zundel dzu@denx.de wrote:

...
Hi Kim,

...
o LCRR_PDYP, granted dangerous in your case, is obviously a writeable bit (not read-only), and documented as such in later documentation. In fact, there are no non-writeable bits in LCRR.

Well, "reserved" != "non-writable" (usually there is a comment that writing reserved bits produces undefined behaviour) so I agree with Heiko that as long the documentation that we have access to, designates bits as reserved, it makes sense to have such a mask.

I think we should allow board-configurable writes to the DBYP bit, which is documented as "reserved" on some 83xx, on the 83xx parts that /do/ implement it. So instead of having a mask, perhaps setting absolute values for CONFIG_SYS_LCRR should be replaced with a better scheme that allows board configs to just set LCRR bits by field, such as what the SCCR setting code does. I.e, deprecate CONFIG_SYS_LCRR and replace with individually-specified CONFIG_SYS_LCRR_{CLKDIV,EADC,ECL,BUDCMDC,DBYP} values.

This will allow the reserved bits, whether 1 on reset or not, to be preserved across all 83xx (and 85xx for that matter).

Hm, you mean like the SCCR stuff in mpc83xx/cpu_init.c? Please don't.

This code is plain ugly - and even more, as I have pointed out multiple times, in not more than 50 lines there are "only" 1024 non-trivially differing c input possibilities coded. This is what I call bad.

Thinking about it, why not do a compromise like e.g. the following:

u32 sccr_mask = 0 \ #ifdef CONFIG_SYS_SCCR_ENCCM | SCCR_ENCCM \ #endif #ifdef CONFIG_SYS_SCCR_PCICM | SCCR_PCICM \ #endif .... #endif ;

u32 sccr_value = 0 \ #ifdef CONFIG_SYS_SCCR_ENCCM | CONFIG_SYS_SCCR_ENCCM \ #endif #ifdef CONFIG_SYS_SCCR_PCICM | CONFIG_SYS_SCCR_PCICM \ #endif .... #endif ;

out_be32(&im->clk.sccr, i(n_be32(&im->clk.sccr) & ~sccr_mask) | sccr_value);

This not only looks a bit nicer, but also (I hope) compiles the *exact* same code for all possibilites, only with changing data values.

Cheers Detlev

-- Or go for generality ... Add a programming language for extensibility and write part of the program in that language. --- GNU Coding Standards -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu@denx.de

Wolfgang Denk

2:02 p.m.

New subject: [U-Boot] [PATCH v2] mpc83xx: update LCRR register handling

Dear Detlev Zundel,

In message m2tyzsw7hr.fsf@ohwell.denx.de you wrote:

...

...
I think we should allow board-configurable writes to the DBYP bit, which is documented as "reserved" on some 83xx, on the 83xx parts that /do/ implement it. So instead of having a mask, perhaps setting absolute values for CONFIG_SYS_LCRR should be replaced with a better scheme that allows board configs to just set LCRR bits by field, such as what the SCCR setting code does. I.e, deprecate CONFIG_SYS_LCRR and replace with individually-specified CONFIG_SYS_LCRR_{CLKDIV,EADC,ECL,BUDCMDC,DBYP} values.

This will allow the reserved bits, whether 1 on reset or not, to be preserved across all 83xx (and 85xx for that matter).

Hm, you mean like the SCCR stuff in mpc83xx/cpu_init.c? Please don't.

This code is plain ugly - and even more, as I have pointed out multiple times, in not more than 50 lines there are "only" 1024 non-trivially differing c input possibilities coded. This is what I call bad.

Agreed.

Kim, the code in mpc83xx/cpu_init.c is *really* ugly.

I hereby suggest that this should be cleaned up ASAP.

...

Thinking about it, why not do a compromise like e.g. the following:

Hm... I don't like the need for duplicated "#ifdef" lists, but don;t know of a better way to write it either.

...

out_be32(&im->clk.sccr, i(n_be32(&im->clk.sccr) & ~sccr_mask) | sccr_value);

Or rather:

clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_value);

...

This not only looks a bit nicer, but also (I hope) compiles the *exact* same code for all possibilites, only with changing data values.

Agreed.

Best regards,

Wolfgang Denk

-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de You got to learn three things. What's real, what's not real, and what's the difference." - Terry Pratchett, _Witches Abroad_

Kim Phillips

6:01 p.m.

New subject: [U-Boot] [PATCH v2] mpc83xx: update LCRR register handling

On Fri, 28 Aug 2009 14:02:15 +0200 Wolfgang Denk wd@denx.de wrote:

...

Dear Detlev Zundel,

In message m2tyzsw7hr.fsf@ohwell.denx.de you wrote:

...
...
I think we should allow board-configurable writes to the DBYP bit, which is documented as "reserved" on some 83xx, on the 83xx parts that /do/ implement it. So instead of having a mask, perhaps setting absolute values for CONFIG_SYS_LCRR should be replaced with a better scheme that allows board configs to just set LCRR bits by field, such as what the SCCR setting code does. I.e, deprecate CONFIG_SYS_LCRR and replace with individually-specified CONFIG_SYS_LCRR_{CLKDIV,EADC,ECL,BUDCMDC,DBYP} values.

This will allow the reserved bits, whether 1 on reset or not, to be preserved across all 83xx (and 85xx for that matter).

Hm, you mean like the SCCR stuff in mpc83xx/cpu_init.c? Please don't.

This code is plain ugly - and even more, as I have pointed out multiple times, in not more than 50 lines there are "only" 1024 non-trivially differing c input possibilities coded. This is what I call bad.

Agreed.

Kim, the code in mpc83xx/cpu_init.c is *really* ugly.

I hereby suggest that this should be cleaned up ASAP.

...
Thinking about it, why not do a compromise like e.g. the following:

Hm... I don't like the need for duplicated "#ifdef" lists, but don;t know of a better way to write it either.

...
out_be32(&im->clk.sccr, i(n_be32(&im->clk.sccr) & ~sccr_mask) | sccr_value);

Or rather:

clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_value);

...
This not only looks a bit nicer, but also (I hope) compiles the *exact* same code for all possibilites, only with changing data values.

Agreed.

agreed, I was already thinking of ways of rewriting the ugly SCCR code, but you beat me to it.

I'll try and get something out this weekend.

Kim

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participants (7)

Detlev Zundel
Heiko Schocher
Jerry Van Baren
Kim Phillips
Kumar Gala
Liu Dave-R63238
Wolfgang Denk