[U-Boot] [PATCH] NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
but that's bogus and did not work anyhow.
Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- doc/README.nand | 2 +- drivers/mtd/nand/nand_base.c | 2 +- drivers/mtd/nand_legacy/nand_legacy.c | 2 +- include/configs/ASH405.h | 1 - include/configs/CATcenter.h | 1 - include/configs/CMS700.h | 1 - include/configs/DU440.h | 1 - include/configs/G2000.h | 1 - include/configs/HH405.h | 1 - include/configs/HUB405.h | 1 - include/configs/IDS8247.h | 1 - include/configs/M5329EVB.h | 1 - include/configs/M5373EVB.h | 1 - include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8360ERDK.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/NC650.h | 1 - include/configs/NETPHONE.h | 1 - include/configs/NETTA.h | 1 - include/configs/NETTA2.h | 1 - include/configs/NETVIA.h | 1 - include/configs/PLU405.h | 1 - include/configs/PMC440.h | 1 - include/configs/PPChameleonEVB.h | 2 -- include/configs/SXNI855T.h | 1 - include/configs/TQM8272.h | 1 - include/configs/TQM85xx.h | 1 - include/configs/VCMA9.h | 1 - include/configs/VOH405.h | 1 - include/configs/WUH405.h | 1 - include/configs/acadia.h | 1 - include/configs/afeb9260.h | 1 - include/configs/alpr.h | 1 - include/configs/at91cap9adk.h | 1 - include/configs/at91rm9200dk.h | 1 - include/configs/at91sam9260ek.h | 1 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9rlek.h | 1 - include/configs/bamboo.h | 1 - include/configs/bf537-stamp.h | 1 - include/configs/canyonlands.h | 1 - include/configs/csb637.h | 1 - include/configs/davinci_dvevm.h | 1 - include/configs/davinci_schmoogie.h | 1 - include/configs/davinci_sffsdr.h | 1 - include/configs/davinci_sonata.h | 1 - include/configs/delta.h | 1 - include/configs/kilauea.h | 1 - include/configs/netstar.h | 1 - include/configs/omap2420h4.h | 1 - include/configs/pdnb3.h | 1 - include/configs/quad100hd.h | 1 - include/configs/sbc2410x.h | 1 - include/configs/sc3.h | 1 - include/configs/sequoia.h | 1 - include/configs/smdk6400.h | 1 - include/configs/socrates.h | 1 - include/configs/stxxtc.h | 1 - include/configs/zylonite.h | 1 - include/linux/mtd/bbm.h | 8 ++++---- include/linux/mtd/nand.h | 9 --------- include/linux/mtd/nand_legacy.h | 5 +++++ 66 files changed, 12 insertions(+), 77 deletions(-)
Index: u-boot-nand/doc/README.nand =================================================================== --- u-boot-nand.orig/doc/README.nand +++ u-boot-nand/doc/README.nand @@ -172,7 +172,7 @@ More Definitions: #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 - #define NAND_MAX_CHIPS 1 + #define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_DAVINCI_BROKEN_ECC Versions of U-Boot <= 1.3.3 and Montavista Linux kernels Index: u-boot-nand/drivers/mtd/nand/nand_base.c =================================================================== --- u-boot-nand.orig/drivers/mtd/nand/nand_base.c +++ u-boot-nand/drivers/mtd/nand/nand_base.c @@ -2144,7 +2144,7 @@ int nand_erase_nand(struct mtd_info *mtd { int page, len, status, pages_per_block, ret, chipnr; struct nand_chip *chip = mtd->priv; - int rewrite_bbt[NAND_MAX_CHIPS]={0}; + int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0}; unsigned int bbt_masked_page = 0xffffffff;
MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", Index: u-boot-nand/drivers/mtd/nand_legacy/nand_legacy.c =================================================================== --- u-boot-nand.orig/drivers/mtd/nand_legacy/nand_legacy.c +++ u-boot-nand/drivers/mtd/nand_legacy/nand_legacy.c @@ -457,7 +457,7 @@ static void NanD_ScanChips(struct nand_c { int floor, chip; int numchips[NAND_MAX_FLOORS]; - int maxchips = NAND_MAX_CHIPS; + int maxchips = CONFIG_SYS_NAND_MAX_CHIPS; int ret = 1;
nand->numchips = 0; Index: u-boot-nand/include/configs/ASH405.h =================================================================== --- u-boot-nand.orig/include/configs/ASH405.h +++ u-boot-nand/include/configs/ASH405.h @@ -150,7 +150,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25
Index: u-boot-nand/include/configs/CATcenter.h =================================================================== --- u-boot-nand.orig/include/configs/CATcenter.h +++ u-boot-nand/include/configs/CATcenter.h @@ -219,7 +219,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ Index: u-boot-nand/include/configs/CMS700.h =================================================================== --- u-boot-nand.orig/include/configs/CMS700.h +++ u-boot-nand/include/configs/CMS700.h @@ -157,7 +157,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25
Index: u-boot-nand/include/configs/DU440.h =================================================================== --- u-boot-nand.orig/include/configs/DU440.h +++ u-boot-nand/include/configs/DU440.h @@ -411,7 +411,6 @@ int du440_phy_addr(int devnum); * NAND FLASH */ #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \ CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS} Index: u-boot-nand/include/configs/G2000.h =================================================================== --- u-boot-nand.orig/include/configs/G2000.h +++ u-boot-nand/include/configs/G2000.h @@ -205,7 +205,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ Index: u-boot-nand/include/configs/HH405.h =================================================================== --- u-boot-nand.orig/include/configs/HH405.h +++ u-boot-nand/include/configs/HH405.h @@ -209,7 +209,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25
Index: u-boot-nand/include/configs/HUB405.h =================================================================== --- u-boot-nand.orig/include/configs/HUB405.h +++ u-boot-nand/include/configs/HUB405.h @@ -149,7 +149,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25
Index: u-boot-nand/include/configs/IDS8247.h =================================================================== --- u-boot-nand.orig/include/configs/IDS8247.h +++ u-boot-nand/include/configs/IDS8247.h @@ -275,7 +275,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define NAND_DISABLE_CE(nand) do \ { \ Index: u-boot-nand/include/configs/M5329EVB.h =================================================================== --- u-boot-nand.orig/include/configs/M5329EVB.h +++ u-boot-nand/include/configs/M5329EVB.h @@ -215,7 +215,6 @@ # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -# define NAND_MAX_CHIPS 1 # define NAND_ALLOW_ERASE_ALL 1 # define CONFIG_JFFS2_NAND 1 # define CONFIG_JFFS2_DEV "nand0" Index: u-boot-nand/include/configs/M5373EVB.h =================================================================== --- u-boot-nand.orig/include/configs/M5373EVB.h +++ u-boot-nand/include/configs/M5373EVB.h @@ -215,7 +215,6 @@ # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -# define NAND_MAX_CHIPS 1 # define NAND_ALLOW_ERASE_ALL 1 # define CONFIG_JFFS2_NAND 1 # define CONFIG_JFFS2_DEV "nand0" Index: u-boot-nand/include/configs/MPC8313ERDB.h =================================================================== --- u-boot-nand.orig/include/configs/MPC8313ERDB.h +++ u-boot-nand/include/configs/MPC8313ERDB.h @@ -232,7 +232,6 @@ #endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 Index: u-boot-nand/include/configs/MPC8315ERDB.h =================================================================== --- u-boot-nand.orig/include/configs/MPC8315ERDB.h +++ u-boot-nand/include/configs/MPC8315ERDB.h @@ -223,7 +223,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ Index: u-boot-nand/include/configs/MPC8360ERDK.h =================================================================== --- u-boot-nand.orig/include/configs/MPC8360ERDK.h +++ u-boot-nand/include/configs/MPC8360ERDK.h @@ -211,7 +211,6 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_UPM 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE Index: u-boot-nand/include/configs/MPC837XEMDS.h =================================================================== --- u-boot-nand.orig/include/configs/MPC837XEMDS.h +++ u-boot-nand/include/configs/MPC837XEMDS.h @@ -271,7 +271,6 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ Index: u-boot-nand/include/configs/MPC8536DS.h =================================================================== --- u-boot-nand.orig/include/configs/MPC8536DS.h +++ u-boot-nand/include/configs/MPC8536DS.h @@ -248,7 +248,6 @@ extern unsigned long get_board_ddr_clk(u CONFIG_SYS_NAND_BASE + 0x80000, \ CONFIG_SYS_NAND_BASE + 0xC0000} #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 Index: u-boot-nand/include/configs/MPC8572DS.h =================================================================== --- u-boot-nand.orig/include/configs/MPC8572DS.h +++ u-boot-nand/include/configs/MPC8572DS.h @@ -267,7 +267,6 @@ extern unsigned long get_board_ddr_clk(u CONFIG_SYS_NAND_BASE + 0x80000,\ CONFIG_SYS_NAND_BASE + 0xC0000} #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 Index: u-boot-nand/include/configs/NC650.h =================================================================== --- u-boot-nand.orig/include/configs/NC650.h +++ u-boot-nand/include/configs/NC650.h @@ -250,7 +250,6 @@ * NAND flash support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1
/*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 Index: u-boot-nand/include/configs/NETPHONE.h =================================================================== --- u-boot-nand.orig/include/configs/NETPHONE.h +++ u-boot-nand/include/configs/NETPHONE.h @@ -514,7 +514,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ #define NAND_DISABLE_CE(nand) \ Index: u-boot-nand/include/configs/NETTA.h =================================================================== --- u-boot-nand.orig/include/configs/NETTA.h +++ u-boot-nand/include/configs/NETTA.h @@ -633,7 +633,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */ #define NAND_DISABLE_CE(nand) \ Index: u-boot-nand/include/configs/NETTA2.h =================================================================== --- u-boot-nand.orig/include/configs/NETTA2.h +++ u-boot-nand/include/configs/NETTA2.h @@ -515,7 +515,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ #define NAND_DISABLE_CE(nand) \ Index: u-boot-nand/include/configs/NETVIA.h =================================================================== --- u-boot-nand.orig/include/configs/NETVIA.h +++ u-boot-nand/include/configs/NETVIA.h @@ -411,7 +411,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define NAND_DISABLE_CE(nand) \ do { \ Index: u-boot-nand/include/configs/PLU405.h =================================================================== --- u-boot-nand.orig/include/configs/PLU405.h +++ u-boot-nand/include/configs/PLU405.h @@ -173,7 +173,6 @@ * NAND-FLASH stuff */ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25
Index: u-boot-nand/include/configs/PMC440.h =================================================================== --- u-boot-nand.orig/include/configs/PMC440.h +++ u-boot-nand/include/configs/PMC440.h @@ -505,7 +505,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_QUIET_TEST 1 Index: u-boot-nand/include/configs/PPChameleonEVB.h =================================================================== --- u-boot-nand.orig/include/configs/PPChameleonEVB.h +++ u-boot-nand/include/configs/PPChameleonEVB.h @@ -224,8 +224,6 @@ #define NAND_BIG_DELAY_US 25 #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
-#define NAND_MAX_CHIPS 1 - #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ Index: u-boot-nand/include/configs/SXNI855T.h =================================================================== --- u-boot-nand.orig/include/configs/SXNI855T.h +++ u-boot-nand/include/configs/SXNI855T.h @@ -206,7 +206,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
/* DFBUSY is available on Port C, bit 12; 0 if busy */ #define NAND_WAIT_READY(nand) \ Index: u-boot-nand/include/configs/TQM8272.h =================================================================== --- u-boot-nand.orig/include/configs/TQM8272.h +++ u-boot-nand/include/configs/TQM8272.h @@ -424,7 +424,6 @@ #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ CONFIG_SYS_NAND1_BASE, \ Index: u-boot-nand/include/configs/TQM85xx.h =================================================================== --- u-boot-nand.orig/include/configs/TQM85xx.h +++ u-boot-nand/include/configs/TQM85xx.h @@ -363,7 +363,6 @@ #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1
#if (CONFIG_SYS_MAX_NAND_DEVICE == 1) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } Index: u-boot-nand/include/configs/VCMA9.h =================================================================== --- u-boot-nand.orig/include/configs/VCMA9.h +++ u-boot-nand/include/configs/VCMA9.h @@ -264,7 +264,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define NAND_WAIT_READY(nand) NF_WaitRB()
Index: u-boot-nand/include/configs/VOH405.h =================================================================== --- u-boot-nand.orig/include/configs/VOH405.h +++ u-boot-nand/include/configs/VOH405.h @@ -159,7 +159,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25
Index: u-boot-nand/include/configs/WUH405.h =================================================================== --- u-boot-nand.orig/include/configs/WUH405.h +++ u-boot-nand/include/configs/WUH405.h @@ -147,7 +147,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25
Index: u-boot-nand/include/configs/acadia.h =================================================================== --- u-boot-nand.orig/include/configs/acadia.h +++ u-boot-nand/include/configs/acadia.h @@ -262,7 +262,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Index: u-boot-nand/include/configs/afeb9260.h =================================================================== --- u-boot-nand.orig/include/configs/afeb9260.h +++ u-boot-nand/include/configs/afeb9260.h @@ -97,7 +97,6 @@ #define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 Index: u-boot-nand/include/configs/alpr.h =================================================================== --- u-boot-nand.orig/include/configs/alpr.h +++ u-boot-nand/include/configs/alpr.h @@ -335,7 +335,6 @@ * NAND-FLASH stuff *-----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \ CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 } Index: u-boot-nand/include/configs/at91cap9adk.h =================================================================== --- u-boot-nand.orig/include/configs/at91cap9adk.h +++ u-boot-nand/include/configs/at91cap9adk.h @@ -118,7 +118,6 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1
/* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 Index: u-boot-nand/include/configs/at91rm9200dk.h =================================================================== --- u-boot-nand.orig/include/configs/at91rm9200dk.h +++ u-boot-nand/include/configs/at91rm9200dk.h @@ -129,7 +129,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ Index: u-boot-nand/include/configs/at91sam9260ek.h =================================================================== --- u-boot-nand.orig/include/configs/at91sam9260ek.h +++ u-boot-nand/include/configs/at91sam9260ek.h @@ -100,7 +100,6 @@ #define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 Index: u-boot-nand/include/configs/at91sam9261ek.h =================================================================== --- u-boot-nand.orig/include/configs/at91sam9261ek.h +++ u-boot-nand/include/configs/at91sam9261ek.h @@ -111,7 +111,6 @@ #define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 Index: u-boot-nand/include/configs/at91sam9263ek.h =================================================================== --- u-boot-nand.orig/include/configs/at91sam9263ek.h +++ u-boot-nand/include/configs/at91sam9263ek.h @@ -123,7 +123,6 @@ #endif
/* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 Index: u-boot-nand/include/configs/at91sam9rlek.h =================================================================== --- u-boot-nand.orig/include/configs/at91sam9rlek.h +++ u-boot-nand/include/configs/at91sam9rlek.h @@ -104,7 +104,6 @@ #define CONFIG_SYS_NO_FLASH 1
/* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 Index: u-boot-nand/include/configs/bamboo.h =================================================================== --- u-boot-nand.orig/include/configs/bamboo.h +++ u-boot-nand/include/configs/bamboo.h @@ -197,7 +197,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 } #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ Index: u-boot-nand/include/configs/bf537-stamp.h =================================================================== --- u-boot-nand.orig/include/configs/bf537-stamp.h +++ u-boot-nand/include/configs/bf537-stamp.h @@ -278,7 +278,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define BFIN_NAND_READY PF3
#define NAND_WAIT_READY(nand) \ Index: u-boot-nand/include/configs/canyonlands.h =================================================================== --- u-boot-nand.orig/include/configs/canyonlands.h +++ u-boot-nand/include/configs/canyonlands.h @@ -234,7 +234,6 @@ * NAND-FLASH related *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Index: u-boot-nand/include/configs/csb637.h =================================================================== --- u-boot-nand.orig/include/configs/csb637.h +++ u-boot-nand/include/configs/csb637.h @@ -131,7 +131,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ Index: u-boot-nand/include/configs/davinci_dvevm.h =================================================================== --- u-boot-nand.orig/include/configs/davinci_dvevm.h +++ u-boot-nand/include/configs/davinci_dvevm.h @@ -127,7 +127,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) Index: u-boot-nand/include/configs/davinci_schmoogie.h =================================================================== --- u-boot-nand.orig/include/configs/davinci_schmoogie.h +++ u-boot-nand/include/configs/davinci_schmoogie.h @@ -89,7 +89,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ /*=====================*/ /* Board related stuff */ Index: u-boot-nand/include/configs/davinci_sffsdr.h =================================================================== --- u-boot-nand.orig/include/configs/davinci_sffsdr.h +++ u-boot-nand/include/configs/davinci_sffsdr.h @@ -85,7 +85,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ /* I2C switch definitions for PCA9543 chip */ #define CONFIG_SYS_I2C_PCA9543_ADDR 0x70 Index: u-boot-nand/include/configs/davinci_sonata.h =================================================================== --- u-boot-nand.orig/include/configs/davinci_sonata.h +++ u-boot-nand/include/configs/davinci_sonata.h @@ -122,7 +122,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) Index: u-boot-nand/include/configs/delta.h =================================================================== --- u-boot-nand.orig/include/configs/delta.h +++ u-boot-nand/include/configs/delta.h @@ -258,7 +258,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NO_FLASH 1
Index: u-boot-nand/include/configs/kilauea.h =================================================================== --- u-boot-nand.orig/include/configs/kilauea.h +++ u-boot-nand/include/configs/kilauea.h @@ -214,7 +214,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Index: u-boot-nand/include/configs/netstar.h =================================================================== --- u-boot-nand.orig/include/configs/netstar.h +++ u-boot-nand/include/configs/netstar.h @@ -120,7 +120,6 @@ * NAND flash */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23) #define NAND_ALLOW_ERASE_ALL 1
Index: u-boot-nand/include/configs/omap2420h4.h =================================================================== --- u-boot-nand.orig/include/configs/omap2420h4.h +++ u-boot-nand/include/configs/omap2420h4.h @@ -163,7 +163,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) #define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) Index: u-boot-nand/include/configs/pdnb3.h =================================================================== --- u-boot-nand.orig/include/configs/pdnb3.h +++ u-boot-nand/include/configs/pdnb3.h @@ -264,7 +264,6 @@ * NAND-FLASH stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ #endif
Index: u-boot-nand/include/configs/quad100hd.h =================================================================== --- u-boot-nand.orig/include/configs/quad100hd.h +++ u-boot-nand/include/configs/quad100hd.h @@ -224,7 +224,6 @@ #define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */ #define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */ #define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #endif
Index: u-boot-nand/include/configs/sbc2410x.h =================================================================== --- u-boot-nand.orig/include/configs/sbc2410x.h +++ u-boot-nand/include/configs/sbc2410x.h @@ -209,7 +209,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define NAND_WAIT_READY(nand) NF_WaitRB() #define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) Index: u-boot-nand/include/configs/sc3.h =================================================================== --- u-boot-nand.orig/include/configs/sc3.h +++ u-boot-nand/include/configs/sc3.h @@ -424,7 +424,6 @@ extern unsigned long offsetOfEnvironment * NAND-FLASH stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE 0x77D00000
Index: u-boot-nand/include/configs/sequoia.h =================================================================== --- u-boot-nand.orig/include/configs/sequoia.h +++ u-boot-nand/include/configs/sequoia.h @@ -373,7 +373,6 @@ * NAND FLASH */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Index: u-boot-nand/include/configs/smdk6400.h =================================================================== --- u-boot-nand.orig/include/configs/smdk6400.h +++ u-boot-nand/include/configs/smdk6400.h @@ -227,7 +227,6 @@ /* NAND configuration */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x70200010 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_S3C_NAND_HWECC
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ Index: u-boot-nand/include/configs/socrates.h =================================================================== --- u-boot-nand.orig/include/configs/socrates.h +++ u-boot-nand/include/configs/socrates.h @@ -186,7 +186,6 @@
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_CMD_NAND
/* LIME GDC */ Index: u-boot-nand/include/configs/stxxtc.h =================================================================== --- u-boot-nand.orig/include/configs/stxxtc.h +++ u-boot-nand/include/configs/stxxtc.h @@ -464,7 +464,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */ #define NAND_DISABLE_CE(nand) \ Index: u-boot-nand/include/configs/zylonite.h =================================================================== --- u-boot-nand.orig/include/configs/zylonite.h +++ u-boot-nand/include/configs/zylonite.h @@ -227,7 +227,6 @@
#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NO_FLASH 1
Index: u-boot-nand/include/linux/mtd/bbm.h =================================================================== --- u-boot-nand.orig/include/linux/mtd/bbm.h +++ u-boot-nand/include/linux/mtd/bbm.h @@ -18,8 +18,8 @@ #define __LINUX_MTD_BBM_H
/* The maximum number of NAND chips in an array */ -#ifndef NAND_MAX_CHIPS -#define NAND_MAX_CHIPS 8 +#ifndef CONFIG_SYS_NAND_MAX_CHIPS +#define CONFIG_SYS_NAND_MAX_CHIPS 1 #endif
/** @@ -48,10 +48,10 @@ */ struct nand_bbt_descr { int options; - int pages[NAND_MAX_CHIPS]; + int pages[CONFIG_SYS_NAND_MAX_CHIPS]; int offs; int veroffs; - uint8_t version[NAND_MAX_CHIPS]; + uint8_t version[CONFIG_SYS_NAND_MAX_CHIPS]; int len; int maxblocks; int reserved_block_code; Index: u-boot-nand/include/linux/mtd/nand.h =================================================================== --- u-boot-nand.orig/include/linux/mtd/nand.h +++ u-boot-nand/include/linux/mtd/nand.h @@ -46,11 +46,6 @@ extern void nand_release (struct mtd_inf /* Internal helper for board drivers which need to override command function */ extern void nand_wait_ready(struct mtd_info *mtd);
-/* The maximum number of NAND chips in an array */ -#ifndef NAND_MAX_CHIPS -#define NAND_MAX_CHIPS 8 -#endif - /* This constant declares the max. oobsize / page, which * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. @@ -477,10 +472,6 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[];
-#ifndef NAND_MAX_CHIPS -#define NAND_MAX_CHIPS 8 -#endif - extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); extern int nand_default_bbt(struct mtd_info *mtd); Index: u-boot-nand/include/linux/mtd/nand_legacy.h =================================================================== --- u-boot-nand.orig/include/linux/mtd/nand_legacy.h +++ u-boot-nand/include/linux/mtd/nand_legacy.h @@ -40,6 +40,11 @@ #error This module is for the legacy NAND support #endif
+/* The maximum number of NAND chips in an array */ +#ifndef CONFIG_SYS_NAND_MAX_CHIPS +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#endif + /* * Standard NAND flash commands */
On Fri, Jan 16, 2009 at 06:55:54PM +0100, Wolfgang Grandegger wrote:
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
but that's bogus and did not work anyhow.
Signed-off-by: Wolfgang Grandegger wg@grandegger.com
Applied to u-boot-nand-flash/next
-Scott
participants (2)
-
Scott Wood -
Wolfgang Grandegger