[PATCH v2 0/7] Add Cortina Access basic DM drivers
Cortina Access management has decided that we want to add formal upstream support of u-boot going forward for our line of SoCs and evaluation boards.
Our line of SoC’s all begin with the “CA” designation followed by 4 digits. i.e. CAxxxx. The CAxxxx series supports both ARM and MIPS ISA based custom cores.
All our drivers have cross platform support for both CPU ISAs. They will be placed in the normal drivers tree in u-boot.
In addition, our SoCs and development boards share common Cortina specific features which are not driver related. Those changes will be maintained in board/cortina/common. While specific development boards will be in board/cortina/board_name.
We would like to have a git-mailrc alias of "cortina" to allow us to better maintain and support our boards and common features found in the board/cortina subtree.
Changes in v2: - Modified filepath for CA ARM and MIPS per trini's recommendation - Rename driver in DT namespace for consistency between all CA drivers. - Remove blank line after SPDX identifier - Remove Authorship as it is already recorded within Git and is redundant - Replace printf() as debug() - Rename driver in DT namespace for consistency between all CA drivers. - Remove blank line after SPDX identifier - Remove authorship comment as it is already recorded within Git and is redundant - Use setbits_32() for read-modify-write operation. - Rename driver in DT namespace for consistency between all CA drivers. - Remove blank line after SPDX identifier - Remove authorship comment as it is already recorded within Git and is redundant - Merge serial_cortina.h reg defines into serial_cortina.c - Modify ca_serial_pending() and API to get resource.
Alex Nemirovsky (3): MAINTAINERS, git-mailrc: cortina: add Custodian for Cortina Access Inc. cortina: common: armv8: add custom init for CA ARMv8 based SoCs board: presidio-asic: Add basic G3 engr. development board support
Jason Li (4): gpio: do not include <asm/arch/gpio.h> for Cortina CAxxxx SoCs gpio: cortina_gpio: add DM_GPIO driver for CAxxxx SoCs watchdog: cortina_wdt: add support for HW WDT on CAxxxx SoCs serial: serial_cortina: add UART DM driver for CAxxxx SoCs
MAINTAINERS | 18 +++ arch/arm/Kconfig | 5 + arch/arm/dts/Makefile | 2 + arch/arm/dts/ca-presidio-engboard.dts | 69 +++++++++++ arch/arm/include/asm/gpio.h | 2 +- board/cortina/common/Kconfig | 5 + board/cortina/common/armv8/ca7774_regs.h | 18 +++ board/cortina/common/armv8/lowlevel_init.S | 87 ++++++++++++++ board/cortina/presidio-asic/Kconfig | 20 ++++ board/cortina/presidio-asic/MAINTAINERS | 6 + board/cortina/presidio-asic/Makefile | 8 ++ board/cortina/presidio-asic/presidio.c | 126 ++++++++++++++++++++ configs/cortina_presidio-asic-base_defconfig | 45 ++++++++ doc/git-mailrc | 2 + drivers/gpio/Kconfig | 8 ++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 111 ++++++++++++++++++ drivers/serial/Kconfig | 7 ++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 164 +++++++++++++++++++++++++++ drivers/watchdog/Kconfig | 8 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 138 ++++++++++++++++++++++ include/configs/presidio_asic.h | 123 ++++++++++++++++++++ 24 files changed, 974 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/ca-presidio-engboard.dts create mode 100644 board/cortina/common/Kconfig create mode 100644 board/cortina/common/armv8/ca7774_regs.h create mode 100644 board/cortina/common/armv8/lowlevel_init.S create mode 100644 board/cortina/presidio-asic/Kconfig create mode 100644 board/cortina/presidio-asic/MAINTAINERS create mode 100644 board/cortina/presidio-asic/Makefile create mode 100644 board/cortina/presidio-asic/presidio.c create mode 100644 configs/cortina_presidio-asic-base_defconfig create mode 100644 drivers/gpio/cortina_gpio.c create mode 100644 drivers/serial/serial_cortina.c create mode 100644 drivers/watchdog/cortina_wdt.c create mode 100644 include/configs/presidio_asic.h
Assign Alex Nemirovsky as custodian for all Cortina Access (CA) for ARM and MIPS based SoCs.
Currently Cortina Access CAxxxx family of SoCs support both ARM and MIPS ISA. Drivers have cross platform support for both architectures.
Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com ---
Changes in v2: - Modified filepath for CA ARM and MIPS per trini's recommendation
MAINTAINERS | 18 ++++++++++++++++++ board/cortina/common/Kconfig | 5 +++++ doc/git-mailrc | 2 ++ 3 files changed, 25 insertions(+) create mode 100644 board/cortina/common/Kconfig
diff --git a/MAINTAINERS b/MAINTAINERS index 438fb22..4649b97 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -173,6 +173,15 @@ F: doc/README.bcm7xxx F: drivers/mmc/bcmstb_sdhci.c F: drivers/spi/bcmstb_spi.c
+ARM CORTINA ACCESS CAxxxx +M: Alex Nemirovsky alex.nemirovsky@cortina-access.com +S: Supported +F: board/cortina/common/ +F: board/cortina/common/armv8/ +F: drivers/gpio/cortina_gpio.c +F: drivers/watchdog/cortina_wdt.c +F: drivers/serial/serial_cortina.c + ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun marek.behun@nic.cz S: Maintained @@ -647,6 +656,15 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mips.git F: arch/mips/
+MIPS CORTINA ACCESS CAxxxx +M: Alex Nemirovsky alex.nemirovsky@cortina-access.com +S: Supported +F: board/cortina/common/ +F: board/cortina/common/mips/ +F: drivers/gpio/cortina_gpio.c +F: drivers/watchdog/cortina_wdt.c +F: drivers/serial/serial_cortina.c + MIPS MSCC M: Gregory CLEMENT gregory.clement@bootlin.com M: Lars Povlsen lars.povlsen@microchip.com diff --git a/board/cortina/common/Kconfig b/board/cortina/common/Kconfig new file mode 100644 index 0000000..a3d361e --- /dev/null +++ b/board/cortina/common/Kconfig @@ -0,0 +1,5 @@ +config CORTINA_PLATFORM + bool "Cortina-Access Platform" + default y + help + Select this option for Cortina-Access platform. diff --git a/doc/git-mailrc b/doc/git-mailrc index d29416a..33d1814 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -15,6 +15,7 @@ alias abrodkin Alexey Brodkin alexey.brodkin@synopsys.com alias afleming Andy Fleming afleming@gmail.com alias ag Anatolij Gustschin agust@denx.de alias agraf Alexander Graf agraf@csgraf.de +alias alexnemirovsky Alex Nemirovsky alex.nemirovsky@cortina-access.com alias alisonwang Alison Wang alison.wang@nxp.com alias angelo_ts Angelo Dureghello angelo@sysam.it alias bmeng Bin Meng bmeng.cn@gmail.com @@ -56,6 +57,7 @@ alias arc uboot, abrodkin
alias arm uboot, trini alias at91 uboot, abiessmann +alias cortina uboot, alexnemirovsky alias davinci ti alias imx uboot, sbabic alias kirkwood uboot, stroese
Cortina Access ARMv8 boards share common custom ARMV8 init routines.
Add common board init code for Cortina Access SoC ARMv8 based SoCs
Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com ---
Changes in v2: None
board/cortina/common/armv8/lowlevel_init.S | 87 ++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 board/cortina/common/armv8/lowlevel_init.S
diff --git a/board/cortina/common/armv8/lowlevel_init.S b/board/cortina/common/armv8/lowlevel_init.S new file mode 100644 index 0000000..702611b --- /dev/null +++ b/board/cortina/common/armv8/lowlevel_init.S @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Cortina-Access + * + */ + + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> +#include <asm/armv8/mmu.h> + + .globl lowlevel_init +lowlevel_init: + mov x29, lr /* Save LR */ + +#if defined(CONFIG_CA77XX) + /* Enable SMPEN in CPUECTLR */ + mrs x0, s3_1_c15_c2_1 + tst x0, #0x40 + b.ne skip_smp_setup + orr x0, x0, #0x40 + msr s3_1_c15_c2_1, x0 +skip_smp_setup: +#endif + +#if defined(CONFIG_CA8277B) + /* Enable CPU Timer */ + ldr x0, =CONFIG_SYS_TIMER_BASE + mov x1, #1 + str w1, [x0] +#endif + +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + branch_if_slave x0, 1f +#ifndef CONFIG_TARGET_VENUS + ldr x0, =GICD_BASE + bl gic_init_secure +#endif +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + +#ifdef CONFIG_ARMV8_MULTIENTRY + branch_if_master x0, x1, 2f + + /* + * Slave should wait for master clearing spin table. + * This sync prevent salves observing incorrect + * value of spin table and jumping to wrong place. + */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif + + /* + * All slaves will enter EL2 and optionally EL1. + */ + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el2 + +lowlevel_in_el2: +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 + bl armv8_switch_to_el1 + +lowlevel_in_el1: +#endif + +#endif /* CONFIG_ARMV8_MULTIENTRY */ + +2: + mov lr, x29 /* Restore LR */ + ret
From: Jason Li jason.li@cortina-access.com
The Cortina CAxxxx GPIO driver maintains DM_GPIO support across different CPU ISA in the CAxxxx Soc Family; Not just ARM. Therefore, it is not desirable to split out and maintain separete gpio header file for each CPU architecture.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
---
Changes in v2: None
arch/arm/include/asm/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 6ff5f42..10af1e1 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -3,7 +3,7 @@ !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \ !defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1028A) && \ !defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A) && \ - !defined(CONFIG_ARCH_ASPEED) + !defined(CONFIG_ARCH_ASPEED) && !defined(CONFIG_CORTINA_PLATFORM) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h>
From: Jason Li jason.li@cortina-access.com
DM_GPIO based GPIO controller driver for CAxxxx SoCs. This driver support multiple CPU architectures and Cortina Access SoC platforms.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
---
Changes in v2: - Rename driver in DT namespace for consistency between all CA drivers. - Remove blank line after SPDX identifier - Remove Authorship as it is already recorded within Git and is redundant - Replace printf() as debug()
drivers/gpio/Kconfig | 8 ++++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 111 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 120 insertions(+) create mode 100644 drivers/gpio/cortina_gpio.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1de6f52..8a7aa5a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -59,6 +59,14 @@ config BCM6345_GPIO help This driver supports the GPIO banks on BCM6345 SoCs.
+config CORTINA_GPIO + bool "Cortina-Access GPIO driver" + depends on DM_GPIO && CORTINA_PLATFORM + help + Enable support for the GPIO controller in Cortina CAxxxx SoCs. + This driver supports all CPU ISA variants supported by Cortina + Access CAxxxx SoCs. + config DWAPB_GPIO bool "DWAPB GPIO driver" depends on DM && DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 449046b..ceae612 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o +obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o diff --git a/drivers/gpio/cortina_gpio.c b/drivers/gpio/cortina_gpio.c new file mode 100644 index 0000000..e2374ce --- /dev/null +++ b/drivers/gpio/cortina_gpio.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Cortina-Access + * + * GPIO Driver for Cortina Access CAxxxx Line of SoCs + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/compat.h> +#include <linux/compiler.h> + +/* GPIO Register Map */ +#define CORTINA_GPIO_CFG 0x00 +#define CORTINA_GPIO_OUT 0x04 +#define CORTINA_GPIO_IN 0x08 +#define CORTINA_GPIO_LVL 0x0C +#define CORTINA_GPIO_EDGE 0x10 +#define CORTINA_GPIO_BOTHEDGE 0x14 +#define CORTINA_GPIO_IE 0x18 +#define CORTINA_GPIO_INT 0x1C +#define CORTINA_GPIO_STAT 0x20 + +struct cortina_gpio_bank { + void __iomem *base; +}; + +#ifdef CONFIG_DM_GPIO +static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + setbits_32(priv->base, BIT(offset)); + return 0; +} + +static int +ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + clrbits_32(priv->base, BIT(offset)); + return 0; +} + +static int ca_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset); +} + +static int ca_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset)); + return 0; +} + +static int ca_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + if (readl(priv->base) & BIT(offset)) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops gpio_cortina_ops = { + .direction_input = ca_gpio_direction_input, + .direction_output = ca_gpio_direction_output, + .get_value = ca_gpio_get_value, + .set_value = ca_gpio_set_value, + .get_function = ca_gpio_get_function, +}; + +static int ca_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32); + uc_priv->bank_name = dev->name; + + debug("Done Cortina GPIO init\n"); + return 0; +} + +static const struct udevice_id ca_gpio_ids[] = { + {.compatible = "cortina,ca-gpio"}, + {} +}; + +U_BOOT_DRIVER(cortina_gpio) = { + .name = "cortina-gpio", + .id = UCLASS_GPIO, + .ops = &gpio_cortina_ops, + .probe = ca_gpio_probe, + .priv_auto_alloc_size = sizeof(struct cortina_gpio_bank), + .of_match = ca_gpio_ids, +}; +#endif /* CONFIG_DM_GPIO */
Am 21.01.20 um 11:19 schrieb Alex Nemirovsky:
From: Jason Li jason.li@cortina-access.com
DM_GPIO based GPIO controller driver for CAxxxx SoCs. This driver support multiple CPU architectures and Cortina Access SoC platforms.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
Changes in v2:
- Rename driver in DT namespace for consistency between all CA drivers.
- Remove blank line after SPDX identifier
- Remove Authorship as it is already recorded within Git and is redundant
- Replace printf() as debug()
drivers/gpio/Kconfig | 8 ++++ drivers/gpio/Makefile | 1 + drivers/gpio/cortina_gpio.c | 111 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 120 insertions(+) create mode 100644 drivers/gpio/cortina_gpio.c
Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com
From: Jason Li jason.li@cortina-access.com
Add support for hardware watchdog timer on all Cortina Access CAxxxx family of SoCs.
Reviewed-by: Stefan Roese sr@denx.de Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
---
Changes in v2: - Rename driver in DT namespace for consistency between all CA drivers. - Remove blank line after SPDX identifier - Remove authorship comment as it is already recorded within Git and is redundant - Use setbits_32() for read-modify-write operation.
drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 138 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 147 insertions(+) create mode 100644 drivers/watchdog/cortina_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8c16d69..2f7dedb 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -99,6 +99,14 @@ config WDT_CDNS Select this to enable Cadence watchdog timer, which can be found on some Xilinx Microzed Platform.
+config WDT_CORTINA + bool "Cortina Access CAxxxx watchdog timer support" + depends on WDT + help + Cortina Access CAxxxx watchdog timer support. + This driver support all CPU ISAs supported by Cortina + Access CAxxxx SoCs. + config WDT_MPC8xx bool "MPC8xx watchdog timer support" depends on WDT && MPC8xx diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 955caef..87f92a4 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o +obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o diff --git a/drivers/watchdog/cortina_wdt.c b/drivers/watchdog/cortina_wdt.c new file mode 100644 index 0000000..f6a0e70 --- /dev/null +++ b/drivers/watchdog/cortina_wdt.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Cortina-Access + * + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <wdt.h> +#include <linux/bitops.h> + +#define CA_WDT_CTRL 0x00 +#define CA_WDT_PS 0x04 +#define CA_WDT_DIV 0x08 +#define CA_WDT_LD 0x0C +#define CA_WDT_LOADE 0x10 +#define CA_WDT_CNT 0x14 +#define CA_WDT_IE 0x18 +#define CA_WDT_INT 0x1C +#define CA_WDT_STAT 0x20 + +/* CA_WDT_CTRL */ +#define CTL_WDT_EN BIT(0) +#define CTL_WDT_RSTEN BIT(1) +#define CTL_WDT_CLK_SEL BIT(2) +/* CA_WDT_LOADE */ +#define WDT_UPD BIT(0) +#define WDT_UPD_PS BIT(1) + +/* Global config */ +#define WDT_RESET_SUB BIT(4) +#define WDT_RESET_ALL_BLOCK BIT(6) +#define WDT_RESET_REMAP BIT(7) +#define WDT_EXT_RESET BIT(8) +#define WDT_RESET_DEFAULT (WDT_EXT_RESET | WDT_RESET_REMAP | \ + WDT_RESET_ALL_BLOCK | WDT_RESET_SUB) + +struct ca_wdt_priv { + void __iomem *base; + void __iomem *global_config; +}; + +static void cortina_wdt_set_timeout(struct udevice *dev, u64 timeout_ms) +{ + struct ca_wdt_priv *priv = dev_get_priv(dev); + + /* Prescale using millisecond unit */ + writel(CORTINA_PER_IO_FREQ / 1000, priv->base + CA_WDT_PS); + + /* Millisecond */ + writel(1, priv->base + CA_WDT_DIV); + + writel(timeout_ms, priv->base + CA_WDT_LD); + writel(WDT_UPD | WDT_UPD_PS, priv->base + CA_WDT_LOADE); +} + +static int cortina_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct ca_wdt_priv *priv = dev_get_priv(dev); + + cortina_wdt_set_timeout(dev, timeout); + + /* WDT Reset option */ + setbits_32(priv->global_config, WDT_RESET_DEFAULT); + + /* Enable WDT */ + setbits_32(priv->base, CTL_WDT_EN | CTL_WDT_RSTEN | CTL_WDT_CLK_SEL); + + return 0; +} + +static int cortina_wdt_stop(struct udevice *dev) +{ + struct ca_wdt_priv *priv = dev_get_priv(dev); + + /* Disable WDT */ + writel(0, priv->base); + + return 0; +} + +static int cortina_wdt_reset(struct udevice *dev) +{ + struct ca_wdt_priv *priv = dev_get_priv(dev); + + /* Reload WDT counter */ + writel(WDT_UPD, priv->base + CA_WDT_LOADE); + + return 0; +} + +static int cortina_wdt_expire_now(struct udevice *dev, ulong flags) +{ + /* Set 1ms timeout to reset system */ + cortina_wdt_set_timeout(dev, 1); + hang(); + + return 0; +} + +static int cortina_wdt_probe(struct udevice *dev) +{ + struct ca_wdt_priv *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -ENOENT; + + priv->global_config = dev_remap_addr_index(dev, 1); + if (!priv->global_config) + return -ENOENT; + + /* Stop WDT */ + cortina_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops cortina_wdt_ops = { + .start = cortina_wdt_start, + .reset = cortina_wdt_reset, + .stop = cortina_wdt_stop, + .expire_now = cortina_wdt_expire_now, +}; + +static const struct udevice_id cortina_wdt_ids[] = { + {.compatible = "cortina,ca-wdt"}, + {} +}; + +U_BOOT_DRIVER(cortina_wdt) = { + .name = "cortina_wdt", + .id = UCLASS_WDT, + .probe = cortina_wdt_probe, + .of_match = cortina_wdt_ids, + .ops = &cortina_wdt_ops, +};
Am 21.01.20 um 11:19 schrieb Alex Nemirovsky:
From: Jason Li jason.li@cortina-access.com
Add support for hardware watchdog timer on all Cortina Access CAxxxx family of SoCs.
Reviewed-by: Stefan Roese sr@denx.de Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
Changes in v2:
- Rename driver in DT namespace for consistency between all CA drivers.
- Remove blank line after SPDX identifier
- Remove authorship comment as it is already recorded within Git and is redundant
- Use setbits_32() for read-modify-write operation.
drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cortina_wdt.c | 138 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 147 insertions(+) create mode 100644 drivers/watchdog/cortina_wdt.c
Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com
From: Jason Li jason.li@cortina-access.com
Add serial UART driver support for all Cortina Access CAxxxx family of SoCs.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
---
Changes in v2: - Rename driver in DT namespace for consistency between all CA drivers. - Remove blank line after SPDX identifier - Remove authorship comment as it is already recorded within Git and is redundant - Merge serial_cortina.h reg defines into serial_cortina.c - Modify ca_serial_pending() and API to get resource.
drivers/serial/Kconfig | 7 ++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 164 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+), 1 deletion(-) create mode 100644 drivers/serial/serial_cortina.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ece7d87..9f76596 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -539,6 +539,13 @@ config BCM6345_SERIAL help Select this to enable UART on BCM6345 SoCs.
+config CORTINA_UART + bool "Cortina UART support" + depends on DM_SERIAL + help + Select this to enable UART support for Cortina-Access UART devices + found on CAxxxx SoCs. + config FSL_LINFLEXUART bool "Freescale Linflex UART support" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 06ee306..c8f2db4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -28,13 +28,13 @@ obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o endif - obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o +obj-$(CONFIG_CORTINA_UART) += serial_cortina.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c new file mode 100644 index 0000000..3af64ba --- /dev/null +++ b/drivers/serial/serial_cortina.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 + * Cortina-Access Ltd. + * + */ + +/* Common UART Driver for Cortina Access CAxxxx line of SoCs */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <watchdog.h> +#include <asm/io.h> +#include <serial.h> +#include <linux/compiler.h> + +/* Register definitions */ +#define UCFG 0x00 /* UART config register */ +#define UFC 0x04 /* Flow Control */ +#define URX_SAMPLE 0x08 /* UART RX Sample register */ +#define URT_TUNE 0x0C /* Fine tune of UART clk */ +#define UTX_DATA 0x10 /* UART TX Character data */ +#define URX_DATA 0x14 /* UART RX Character data */ +#define UINFO 0x18 /* UART Info */ +#define UINT_EN0 0x1C /* UART Interrupt enable 0 */ +#define UINT_EN1 0x20 /* UART Interrupt enable 1 */ +#define UINT0 0x24 /* UART Interrupt 0 setting/clearing */ +#define UINT1 0x28 /* UART Interrupt 1 setting/clearing */ +#define UINT_STAT 0x2C /* UART Interrupt Status */ + +/* UART Control Register Bit Fields */ +#define UCFG_BAUD_COUNT BIT(8) +#define UCFG_EN BIT(7) +#define UCFG_RX_EN BIT(6) +#define UCFG_TX_EN BIT(5) +#define UCFG_PARITY_EN BIT(4) +#define UCFG_PARITY_SEL BIT(3) +#define UCFG_2STOP_BIT BIT(2) +#define UCFG_CNT1 BIT(1) +#define UCFG_CNT0 BIT(0) +#define UCFG_CHAR_5 0 +#define UCFG_CHAR_6 1 +#define UCFG_CHAR_7 2 +#define UCFG_CHAR_8 3 + +#define UINFO_TX_FIFO_EMPTY BIT(3) +#define UINFO_TX_FIFO_FULL BIT(2) +#define UINFO_RX_FIFO_EMPTY BIT(1) +#define UINFO_RX_FIFO_FULL BIT(0) + +#define UINT_RX_NON_EMPTY BIT(6) +#define UINT_TX_EMPTY BIT(5) +#define UINT_RX_UNDERRUN BIT(4) +#define UINT_RX_OVERRUN BIT(3) +#define UINT_RX_PARITY_ERR BIT(2) +#define UINT_RX_STOP_ERR BIT(1) +#define UINT_TX_OVERRUN BIT(0) +#define UINT_MASK_ALL 0x7F + +struct ca_uart_priv { + void __iomem *base; +}; + +int ca_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + unsigned int uart_ctrl, baud, sample; + + baud = CORTINA_UART_CLOCK / baudrate; + + uart_ctrl = readl(priv->base + UCFG); + uart_ctrl |= (baud << 8); + writel(uart_ctrl, priv->base + UCFG); + + sample = baud / 2; + sample = (sample < 7) ? 7 : sample; + writel(sample, priv->base + URX_SAMPLE); + + return 0; +} + +static int ca_serial_getc(struct udevice *dev) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + int ch; + + ch = readl(priv->base + URX_DATA) & 0xFF; + + return (int)ch; +} + +static int ca_serial_putc(struct udevice *dev, const char ch) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + unsigned int status; + + /* Retry if TX FIFO full */ + status = readl(priv->base + UINFO); + if (status & UINFO_TX_FIFO_FULL) + return -EAGAIN; + + writel(ch, priv->base + UTX_DATA); + + return 0; +} + +static int ca_serial_pending(struct udevice *dev, bool input) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + unsigned int status; + + status = readl(priv->base + UINFO); + + if (input) + return (status & UINFO_RX_FIFO_EMPTY) ? 0 : 1; + else + return (status & UINFO_TX_FIFO_FULL) ? 1 : 0; +} + +static int ca_serial_probe(struct udevice *dev) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + u32 uart_ctrl; + + /* Set data, parity and stop bits */ + uart_ctrl = UCFG_EN | UCFG_TX_EN | UCFG_RX_EN | UCFG_CHAR_8; + writel(uart_ctrl, priv->base + UCFG); + + return 0; +} + +static int ca_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ca_uart_priv *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -ENOENT; + + return 0; +} + +static const struct dm_serial_ops ca_serial_ops = { + .putc = ca_serial_putc, + .pending = ca_serial_pending, + .getc = ca_serial_getc, + .setbrg = ca_serial_setbrg, +}; + +static const struct udevice_id ca_serial_ids[] = { + {.compatible = "cortina,ca-uart"}, + {} +}; + +U_BOOT_DRIVER(serial_cortina) = { + .name = "serial_cortina", + .id = UCLASS_SERIAL, + .of_match = ca_serial_ids, + .ofdata_to_platdata = ca_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct ca_uart_priv), + .probe = ca_serial_probe, + .ops = &ca_serial_ops +};
Am 21.01.20 um 11:19 schrieb Alex Nemirovsky:
From: Jason Li jason.li@cortina-access.com
Add serial UART driver support for all Cortina Access CAxxxx family of SoCs.
Signed-off-by: Jason Li jason.li@cortina-access.com Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
Changes in v2:
- Rename driver in DT namespace for consistency between all CA drivers.
- Remove blank line after SPDX identifier
- Remove authorship comment as it is already recorded within Git and is redundant
- Merge serial_cortina.h reg defines into serial_cortina.c
- Modify ca_serial_pending() and API to get resource.
drivers/serial/Kconfig | 7 ++ drivers/serial/Makefile | 2 +- drivers/serial/serial_cortina.c | 164 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+), 1 deletion(-) create mode 100644 drivers/serial/serial_cortina.c
Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com
nits below
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ece7d87..9f76596 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -539,6 +539,13 @@ config BCM6345_SERIAL help Select this to enable UART on BCM6345 SoCs.
+config CORTINA_UART
- bool "Cortina UART support"
- depends on DM_SERIAL
- help
Select this to enable UART support for Cortina-Access UART devicesfound on CAxxxx SoCs.config FSL_LINFLEXUART bool "Freescale Linflex UART support" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 06ee306..c8f2db4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -28,13 +28,13 @@ obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o endif
obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o +obj-$(CONFIG_CORTINA_UART) += serial_cortina.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += mcfuart.o diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c new file mode 100644 index 0000000..3af64ba --- /dev/null +++ b/drivers/serial/serial_cortina.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- (C) Copyright 2020
- Cortina-Access Ltd.
I think this should be on one line
- */
+/* Common UART Driver for Cortina Access CAxxxx line of SoCs */
this should be moved to the previous comment block
+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <watchdog.h> +#include <asm/io.h> +#include <serial.h> +#include <linux/compiler.h>
+/* Register definitions */ +#define UCFG 0x00 /* UART config register */ +#define UFC 0x04 /* Flow Control */ +#define URX_SAMPLE 0x08 /* UART RX Sample register */ +#define URT_TUNE 0x0C /* Fine tune of UART clk */ +#define UTX_DATA 0x10 /* UART TX Character data */ +#define URX_DATA 0x14 /* UART RX Character data */ +#define UINFO 0x18 /* UART Info */ +#define UINT_EN0 0x1C /* UART Interrupt enable 0 */ +#define UINT_EN1 0x20 /* UART Interrupt enable 1 */ +#define UINT0 0x24 /* UART Interrupt 0 setting/clearing */ +#define UINT1 0x28 /* UART Interrupt 1 setting/clearing */ +#define UINT_STAT 0x2C /* UART Interrupt Status */
+/* UART Control Register Bit Fields */ +#define UCFG_BAUD_COUNT BIT(8) +#define UCFG_EN BIT(7) +#define UCFG_RX_EN BIT(6) +#define UCFG_TX_EN BIT(5) +#define UCFG_PARITY_EN BIT(4) +#define UCFG_PARITY_SEL BIT(3) +#define UCFG_2STOP_BIT BIT(2) +#define UCFG_CNT1 BIT(1) +#define UCFG_CNT0 BIT(0) +#define UCFG_CHAR_5 0 +#define UCFG_CHAR_6 1 +#define UCFG_CHAR_7 2 +#define UCFG_CHAR_8 3
+#define UINFO_TX_FIFO_EMPTY BIT(3) +#define UINFO_TX_FIFO_FULL BIT(2) +#define UINFO_RX_FIFO_EMPTY BIT(1) +#define UINFO_RX_FIFO_FULL BIT(0)
+#define UINT_RX_NON_EMPTY BIT(6) +#define UINT_TX_EMPTY BIT(5) +#define UINT_RX_UNDERRUN BIT(4) +#define UINT_RX_OVERRUN BIT(3) +#define UINT_RX_PARITY_ERR BIT(2) +#define UINT_RX_STOP_ERR BIT(1) +#define UINT_TX_OVERRUN BIT(0) +#define UINT_MASK_ALL 0x7F
+struct ca_uart_priv {
- void __iomem *base;
+};
+int ca_serial_setbrg(struct udevice *dev, int baudrate) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- unsigned int uart_ctrl, baud, sample;
- baud = CORTINA_UART_CLOCK / baudrate;
- uart_ctrl = readl(priv->base + UCFG);
- uart_ctrl |= (baud << 8);
- writel(uart_ctrl, priv->base + UCFG);
you should clear the old baud value at first before writing a new one. AFAIK _setbrg() is supposed to be able to be called multiple times. With or'ing only you would possibly end up with a wrong value. clrsetbits_32() should do the job.
- sample = baud / 2;
- sample = (sample < 7) ? 7 : sample;
- writel(sample, priv->base + URX_SAMPLE);
- return 0;
+}
+static int ca_serial_getc(struct udevice *dev) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- int ch;
- ch = readl(priv->base + URX_DATA) & 0xFF;
- return (int)ch;
+}
+static int ca_serial_putc(struct udevice *dev, const char ch) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- unsigned int status;
- /* Retry if TX FIFO full */
- status = readl(priv->base + UINFO);
- if (status & UINFO_TX_FIFO_FULL)
return -EAGAIN;- writel(ch, priv->base + UTX_DATA);
- return 0;
+}
+static int ca_serial_pending(struct udevice *dev, bool input) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- unsigned int status;
- status = readl(priv->base + UINFO);
- if (input)
return (status & UINFO_RX_FIFO_EMPTY) ? 0 : 1;- else
return (status & UINFO_TX_FIFO_FULL) ? 1 : 0;+}
+static int ca_serial_probe(struct udevice *dev) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- u32 uart_ctrl;
- /* Set data, parity and stop bits */
- uart_ctrl = UCFG_EN | UCFG_TX_EN | UCFG_RX_EN | UCFG_CHAR_8;
- writel(uart_ctrl, priv->base + UCFG);
- return 0;
+}
+static int ca_serial_ofdata_to_platdata(struct udevice *dev) +{
- struct ca_uart_priv *priv = dev_get_priv(dev);
- priv->base = dev_remap_addr_index(dev, 0);
- if (!priv->base)
return -ENOENT;- return 0;
+}
+static const struct dm_serial_ops ca_serial_ops = {
- .putc = ca_serial_putc,
- .pending = ca_serial_pending,
- .getc = ca_serial_getc,
- .setbrg = ca_serial_setbrg,
+};
+static const struct udevice_id ca_serial_ids[] = {
- {.compatible = "cortina,ca-uart"},
- {}
+};
+U_BOOT_DRIVER(serial_cortina) = {
- .name = "serial_cortina",
- .id = UCLASS_SERIAL,
- .of_match = ca_serial_ids,
- .ofdata_to_platdata = ca_serial_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct ca_uart_priv),
- .probe = ca_serial_probe,
- .ops = &ca_serial_ops
+};
Add basic Presidio G3 engineering board support
Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com ---
Changes in v2: None
arch/arm/Kconfig | 5 ++ arch/arm/dts/Makefile | 2 + arch/arm/dts/ca-presidio-engboard.dts | 69 +++++++++++++++ board/cortina/common/armv8/ca7774_regs.h | 18 ++++ board/cortina/presidio-asic/Kconfig | 20 +++++ board/cortina/presidio-asic/MAINTAINERS | 6 ++ board/cortina/presidio-asic/Makefile | 8 ++ board/cortina/presidio-asic/presidio.c | 126 +++++++++++++++++++++++++++ configs/cortina_presidio-asic-base_defconfig | 45 ++++++++++ include/configs/presidio_asic.h | 123 ++++++++++++++++++++++++++ 10 files changed, 422 insertions(+) create mode 100644 arch/arm/dts/ca-presidio-engboard.dts create mode 100644 board/cortina/common/armv8/ca7774_regs.h create mode 100644 board/cortina/presidio-asic/Kconfig create mode 100644 board/cortina/presidio-asic/MAINTAINERS create mode 100644 board/cortina/presidio-asic/Makefile create mode 100644 board/cortina/presidio-asic/presidio.c create mode 100644 configs/cortina_presidio-asic-base_defconfig create mode 100644 include/configs/presidio_asic.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 36c9c2f..6d95cde 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1638,6 +1638,10 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie.
+config TARGET_PRESIDIO_ASIC + bool "Support Cortina Presidio ASIC Platform" + select ARM64 + endchoice
config ARCH_SUPPORT_TFABOOT @@ -1782,6 +1786,7 @@ source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/cortina/presidio-asic/Kconfig" source "board/broadcom/bcm23550_w1d/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcm963158/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0127a91..81db1e6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -849,6 +849,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
+dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb + targets += $(dtb-y)
# Add any required device tree compiler flags here diff --git a/arch/arm/dts/ca-presidio-engboard.dts b/arch/arm/dts/ca-presidio-engboard.dts new file mode 100644 index 0000000..ef371b0 --- /dev/null +++ b/arch/arm/dts/ca-presidio-engboard.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Cortina Access Inc. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + + mmc0: mmc@f4400000 { + compatible = "snps,dw-cortina"; + reg = <0x0 0xf4400000 0x1000>; + bus-width = <4>; + io_ds = <0x77>; + fifo-mode; + sd_dll_ctrl = <0xf43200e8>; + io_drv_ctrl = <0xf432004c>; + }; + + gpio0: gpio-controller@0xf4329280 { + compatible = "cortina,ca-gpio"; + reg = <0x0 0xf4329280 0x24>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + gpio1: gpio-controller@0xf43292a4 { + compatible = "cortina,ca-gpio"; + reg = <0x0 0xf43292a4 0x24>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + watchdog: watchdog@0xf432901c { + compatible = "cortina,ca-wdt"; + reg = <0x0 0xf432901c 0x34>, + <0x0 0xf4320020 0x04>; + status = "okay"; + }; + + uart0: serial@0xf4329148 { + u-boot,dm-pre-reloc; + compatible = "cortina,ca-uart"; + reg = <0x0 0xf4329148 0x30>; + status = "okay"; + }; + + i2c: i2c@f4329120 { + compatible = "cortina,ca-i2c"; + reg = <0x0 0xf4329120 0x28>; + clock-frequency = <400000>; + }; + + sflash: sflash-controller@f4324000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "cortina,ca-sflash"; + reg = <0x0 0xf4324000 0x50>; + reg-names = "sflash-regs"; + flash@0 { + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <1>; + spi-max-frequency = <108000000>; + }; + }; +}; diff --git a/board/cortina/common/armv8/ca7774_regs.h b/board/cortina/common/armv8/ca7774_regs.h new file mode 100644 index 0000000..d997155 --- /dev/null +++ b/board/cortina/common/armv8/ca7774_regs.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015-2020, Cortina-Access Incorporation. + */ + +#ifndef _CA7774_H_ +#define _CA7774_H_ + +#define CA_PERIPH_BASE 0xE0000000UL +#define CA_PERIPH_SIZE 0x20000000UL +#define CA_GLOBAL_BASE 0xf4320000 +#define CA_GLOBAL_JTAG_ID 0xf4320000 +#define CA_GLOBAL_BLOCK_RESET 0xf4320004 +#define CA_GLOBAL_BLOCK_RESET_RESET_DMA BIT(16) +#define CA_DMA_SEC_SSP_BAUDRATE_CTRL 0xf7001b94 +#define CA_DMA_SEC_SSP_ID 0xf7001b80 + +#endif /* _CA7774_H_ */ diff --git a/board/cortina/presidio-asic/Kconfig b/board/cortina/presidio-asic/Kconfig new file mode 100644 index 0000000..8b3f3fd --- /dev/null +++ b/board/cortina/presidio-asic/Kconfig @@ -0,0 +1,20 @@ +if TARGET_PRESIDIO_ASIC +config BIT64 + bool + default y + +config CA77XX + bool + default y + +config SYS_BOARD + default "presidio-asic" + +config SYS_VENDOR + default "cortina" + +config SYS_CONFIG_NAME + default "presidio_asic" + +source "board/cortina/common/Kconfig" +endif diff --git a/board/cortina/presidio-asic/MAINTAINERS b/board/cortina/presidio-asic/MAINTAINERS new file mode 100644 index 0000000..9db17bd --- /dev/null +++ b/board/cortina/presidio-asic/MAINTAINERS @@ -0,0 +1,6 @@ +Cortina Presidio ASIC G3 Engineering BOARD +M: Alex Nemirovsky alex.nemirovsky@cortina-access.com +S: Supported +F: board/cortina/presidio-asic/ +F: include/configs/presidio_asic.h +F: configs/cortina_presidio-asic*defconfig diff --git a/board/cortina/presidio-asic/Makefile b/board/cortina/presidio-asic/Makefile new file mode 100644 index 0000000..33f8e7c --- /dev/null +++ b/board/cortina/presidio-asic/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2020 Cortina-Access.Inc. +# +# + +obj-y := presidio.o +obj-y += ../common/armv8/lowlevel_init.o diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c new file mode 100644 index 0000000..1bebe28 --- /dev/null +++ b/board/cortina/presidio-asic/presidio.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 - Cortina Access Inc. + * + */ +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <asm/io.h> +#include <linux/compiler.h> +#include <configs/presidio_asic.h> +#include <linux/psci.h> +#include <asm/psci.h> +#include <cpu_func.h> +#include <asm/armv8/mmu.h> +#include "../common/armv8/ca7774_regs.h" + +DECLARE_GLOBAL_DATA_PTR; + +int print_cpuinfo(void) +{ + printf("CPU: Cortina Presidio G3\n"); + return 0; +} + +static struct mm_region presidio_mem_map[] = { + { + .virt = DDR_BASE, + .phys = DDR_BASE, + .size = PHYS_SDRAM_1_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, + { + .virt = CA_PERIPH_BASE, + .phys = CA_PERIPH_BASE, + .size = CA_PERIPH_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = presidio_mem_map; + +static noinline int invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1, + u64 arg2) +{ + asm volatile("mov x0, %0\n" + "mov x1, %1\n" + "mov x2, %2\n" + "mov x3, %3\n" + "smc #0\n" + : "+r" (function_id) + : "r" (arg0), "r" (arg1), "r" (arg2) + ); + + return function_id; +} + +int board_early_init_r(void) +{ + dcache_disable(); + return 0; +} + +int board_init(void) +{ + unsigned int reg_data, jtag_id; + + /* Enable timer */ + writel(1, CONFIG_SYS_TIMER_BASE); + + /* Enable snoop in CCI400 slave port#4 */ + writel(3, 0xF5595000); + + jtag_id = readl(CA_GLOBAL_JTAG_ID); + + /* If this is HGU variant then do not use + * the Saturn daughter card ref. clk + */ + if (jtag_id == 0x1010D8F3) { + reg_data = readl(0xF3100064); + /* change multifunc. REF CLK pin to + * a simple GPIO pin + */ + reg_data |= (1 << 1); + writel(reg_data, 0xf3100064); + } + + return 0; +} + +int dram_init(void) +{ + unsigned int ddr_size; + + ddr_size = readl(0x111100c); + gd->ram_size = ddr_size * 0x100000; + return 0; +} + +void reset_cpu(ulong addr) +{ + invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0); +} + +#ifdef CONFIG_LAST_STAGE_INIT +int last_stage_init(void) +{ + u32 val; + + val = readl(CA_GLOBAL_BLOCK_RESET); + val &= ~CA_GLOBAL_BLOCK_RESET_RESET_DMA; + writel(val, CA_GLOBAL_BLOCK_RESET); + + /* reduce output pclk ~3.7Hz to save power consumption */ + writel(0x000000FF, CA_DMA_SEC_SSP_BAUDRATE_CTRL); + + return 0; +} +#endif diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig new file mode 100644 index 0000000..45b911c --- /dev/null +++ b/configs/cortina_presidio-asic-base_defconfig @@ -0,0 +1,45 @@ +# Cortina-Access Ltd. Presidio ASIC Board +CONFIG_CORTINA_PLATFORM=y +CONFIG_ARM=y +CONFIG_SYS_ARCH_TIMER=n +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_TEXT_BASE=0x04000000 +CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="G3#" +CONFIG_NR_DRAM_BANKS=1 +CONFIG_CONS_INDEX=0 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_BOOTP_VCI_STRING="U-boot.armv8.presidio" +CONFIG_OF_LIBFDT=y + +CONFIG_MENU=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y + +CONFIG_DM=y +CONFIG_CORTINA_UART=y +CONFIG_REQUIRE_SERIAL_CONSOLE=y +CONFIG_DM_SERIAL=y + +CONFIG_DM_GPIO=y +CONFIG_CORTINA_GPIO=y + +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 +CONFIG_WDT=y +CONFIG_WDT_CORTINA=y +CONFIG_CMD_WDT=y + +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" + +CONFIG_MMC=n +CONFIG_NET=n +CONFIG_NETDEVICES=n diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h new file mode 100644 index 0000000..d4f7888 --- /dev/null +++ b/include/configs/presidio_asic.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Cortina Access Inc. + * + * Configuration for Cortina-Access Presidio board. + */ + +#ifndef __PRESIDIO_ASIC_H +#define __PRESIDIO_ASIC_H + +#define CONFIG_BIT64 1 + +//#include <generated/autoconf.h> + +#define CA_REG_READ(addr) readl((u64)addr) +#define CA_REG_WRITE(value, addr) writel(value, (u64)addr) + +#define CONFIG_CA77XX 1 + +#define CONFIG_REMAKE_ELF + +#define CONFIG_GICV2 + +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_ARMV8_MULTIENTRY + +/* SMP jump address in DRAM */ +#define CPU_RELEASE_ADDR 0x0740fff8 + +#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 +#define CONFIG_SYS_BOOTM_LEN 0x00c00000 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 +#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY +#define CONFIG_SYS_TIMER_COUNTER 0xf4321008 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xf7011000 +#define GICC_BASE 0xf7012000 + +#define CONFIG_SYS_MEMTEST_SCRATCH 0x00100000 +#define CONFIG_SYS_MEMTEST_START 0x05000000 +#define CONFIG_SYS_MEMTEST_END 0x0D000000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) + +#define CONFIG_SYS_TIMER_BASE 0xf4321000 + +/* Use external clock source */ +#define PRESIDIO_APB_CLK 125000000 +#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK + +/* Cortina Serial Configuration */ +#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) +#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_SERIAL0 PER_UART0_CFG +#define CONFIG_SYS_SERIAL1 PER_UART1_CFG + +/* BLOCK Reset Definitions */ +#define RESET_OTPROM BIT(29) +#define RESET_SD BIT(28) +#define RESET_EAXI BIT(27) +#define RESET_FBM BIT(26) +#define RESET_LDMA BIT(25) +#define RESET_RCRYPTO BIT(24) +#define RESET_SADB BIT(22) +#define RESET_RCPU1 BIT(21) +#define RESET_RCPU0 BIT(20) +#define RESET_PE1 BIT(19) +#define RESET_PE0 BIT(18) +#define RESET_RTC BIT(17) +#define RESET_DMA BIT(16) +#define RESET_PER BIT(15) +#define RESET_FLASH BIT(14) +#define RESET_GIC400 BIT(10) +#define RESET_SATA BIT(9) +#define RESET_PCIE2 BIT(8) +#define RESET_PCIE1 BIT(7) +#define RESET_PCIE0 BIT(6) +#define RESET_TQM BIT(5) +#define RESET_SDRAM BIT(4) +#define RESET_L3FE BIT(3) +#define RESET_L2TM BIT(2) +#define RESET_L2FE BIT(1) +#define RESET_NI BIT(0) + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Miscellaneous configurable options */ +#define DDR_BASE 0x00000000 +#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000) +#define CONFIG_LAST_STAGE_INIT + +/* Physical Memory Map */ + +/* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 DDR_BASE +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Initial environment variables */ + +#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" +#define CONFIG_BOOTARGS "earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0" + +/* Monitor Command Prompt */ + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* max command args */ +#define CONFIG_SYS_MAXARGS 64 + +#endif /* __PRESIDIO_ASIC_H */
Am 21.01.20 um 11:19 schrieb Alex Nemirovsky:
Add basic Presidio G3 engineering board support
Signed-off-by: Alex Nemirovsky alex.nemirovsky@cortina-access.com
Changes in v2: None
arch/arm/Kconfig | 5 ++ arch/arm/dts/Makefile | 2 + arch/arm/dts/ca-presidio-engboard.dts | 69 +++++++++++++++ board/cortina/common/armv8/ca7774_regs.h | 18 ++++ board/cortina/presidio-asic/Kconfig | 20 +++++ board/cortina/presidio-asic/MAINTAINERS | 6 ++ board/cortina/presidio-asic/Makefile | 8 ++ board/cortina/presidio-asic/presidio.c | 126 +++++++++++++++++++++++++++ configs/cortina_presidio-asic-base_defconfig | 45 ++++++++++ include/configs/presidio_asic.h | 123 ++++++++++++++++++++++++++ 10 files changed, 422 insertions(+) create mode 100644 arch/arm/dts/ca-presidio-engboard.dts create mode 100644 board/cortina/common/armv8/ca7774_regs.h create mode 100644 board/cortina/presidio-asic/Kconfig create mode 100644 board/cortina/presidio-asic/MAINTAINERS create mode 100644 board/cortina/presidio-asic/Makefile create mode 100644 board/cortina/presidio-asic/presidio.c create mode 100644 configs/cortina_presidio-asic-base_defconfig create mode 100644 include/configs/presidio_asic.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 36c9c2f..6d95cde 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1638,6 +1638,10 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie.
+config TARGET_PRESIDIO_ASIC
- bool "Support Cortina Presidio ASIC Platform"
- select ARM64
endchoice
config ARCH_SUPPORT_TFABOOT @@ -1782,6 +1786,7 @@ source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/cortina/presidio-asic/Kconfig" source "board/broadcom/bcm23550_w1d/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcm963158/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0127a91..81db1e6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -849,6 +849,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
+dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
targets += $(dtb-y)
# Add any required device tree compiler flags here diff --git a/arch/arm/dts/ca-presidio-engboard.dts b/arch/arm/dts/ca-presidio-engboard.dts new file mode 100644 index 0000000..ef371b0 --- /dev/null +++ b/arch/arm/dts/ca-presidio-engboard.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2020, Cortina Access Inc.
- */
+/dts-v1/;
+/ {
- #address-cells = <2>;
- #size-cells = <1>;
- mmc0: mmc@f4400000 {
compatible = "snps,dw-cortina";reg = <0x0 0xf4400000 0x1000>;bus-width = <4>;io_ds = <0x77>;fifo-mode;sd_dll_ctrl = <0xf43200e8>;io_drv_ctrl = <0xf432004c>;- };
- gpio0: gpio-controller@0xf4329280 {
compatible = "cortina,ca-gpio";reg = <0x0 0xf4329280 0x24>;gpio-controller;#gpio-cells = <2>;status = "okay";- };
- gpio1: gpio-controller@0xf43292a4 {
compatible = "cortina,ca-gpio";reg = <0x0 0xf43292a4 0x24>;gpio-controller;#gpio-cells = <2>;status = "disabled";- };
- watchdog: watchdog@0xf432901c {
compatible = "cortina,ca-wdt";reg = <0x0 0xf432901c 0x34>,<0x0 0xf4320020 0x04>;status = "okay";- };
- uart0: serial@0xf4329148 {
u-boot,dm-pre-reloc;compatible = "cortina,ca-uart";reg = <0x0 0xf4329148 0x30>;status = "okay";- };
- i2c: i2c@f4329120 {
compatible = "cortina,ca-i2c";reg = <0x0 0xf4329120 0x28>;clock-frequency = <400000>;- };
- sflash: sflash-controller@f4324000 {
#address-cells = <2>;#size-cells = <1>;compatible = "cortina,ca-sflash";reg = <0x0 0xf4324000 0x50>;reg-names = "sflash-regs";flash@0 {compatible = "jedec,spi-nor";spi-rx-bus-width = <1>;spi-max-frequency = <108000000>;};
closing bracket is incorrectly indented
- };
+}; diff --git a/board/cortina/common/armv8/ca7774_regs.h b/board/cortina/common/armv8/ca7774_regs.h new file mode 100644 index 0000000..d997155 --- /dev/null +++ b/board/cortina/common/armv8/ca7774_regs.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2015-2020, Cortina-Access Incorporation.
- */
+#ifndef _CA7774_H_ +#define _CA7774_H_
+#define CA_PERIPH_BASE 0xE0000000UL +#define CA_PERIPH_SIZE 0x20000000UL +#define CA_GLOBAL_BASE 0xf4320000 +#define CA_GLOBAL_JTAG_ID 0xf4320000 +#define CA_GLOBAL_BLOCK_RESET 0xf4320004 +#define CA_GLOBAL_BLOCK_RESET_RESET_DMA BIT(16) +#define CA_DMA_SEC_SSP_BAUDRATE_CTRL 0xf7001b94 +#define CA_DMA_SEC_SSP_ID 0xf7001b80
+#endif /* _CA7774_H_ */ diff --git a/board/cortina/presidio-asic/Kconfig b/board/cortina/presidio-asic/Kconfig new file mode 100644 index 0000000..8b3f3fd --- /dev/null +++ b/board/cortina/presidio-asic/Kconfig @@ -0,0 +1,20 @@ +if TARGET_PRESIDIO_ASIC +config BIT64
- bool
- default y
+config CA77XX
- bool
- default y
+config SYS_BOARD
- default "presidio-asic"
+config SYS_VENDOR
- default "cortina"
+config SYS_CONFIG_NAME
- default "presidio_asic"
+source "board/cortina/common/Kconfig" +endif diff --git a/board/cortina/presidio-asic/MAINTAINERS b/board/cortina/presidio-asic/MAINTAINERS new file mode 100644 index 0000000..9db17bd --- /dev/null +++ b/board/cortina/presidio-asic/MAINTAINERS @@ -0,0 +1,6 @@ +Cortina Presidio ASIC G3 Engineering BOARD +M: Alex Nemirovsky alex.nemirovsky@cortina-access.com +S: Supported +F: board/cortina/presidio-asic/ +F: include/configs/presidio_asic.h +F: configs/cortina_presidio-asic*defconfig diff --git a/board/cortina/presidio-asic/Makefile b/board/cortina/presidio-asic/Makefile new file mode 100644 index 0000000..33f8e7c --- /dev/null +++ b/board/cortina/presidio-asic/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2020 Cortina-Access.Inc. +# +#
+obj-y := presidio.o +obj-y += ../common/armv8/lowlevel_init.o diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c new file mode 100644 index 0000000..1bebe28 --- /dev/null +++ b/board/cortina/presidio-asic/presidio.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- (C) Copyright 2020 - Cortina Access Inc.
- */
+#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <asm/io.h> +#include <linux/compiler.h> +#include <configs/presidio_asic.h> +#include <linux/psci.h> +#include <asm/psci.h> +#include <cpu_func.h> +#include <asm/armv8/mmu.h> +#include "../common/armv8/ca7774_regs.h"
+DECLARE_GLOBAL_DATA_PTR;
+int print_cpuinfo(void) +{
- printf("CPU: Cortina Presidio G3\n");
- return 0;
+}
+static struct mm_region presidio_mem_map[] = {
- {
- .virt = DDR_BASE,
- .phys = DDR_BASE,
- .size = PHYS_SDRAM_1_SIZE,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE- },
- {
- .virt = CA_PERIPH_BASE,
- .phys = CA_PERIPH_BASE,
- .size = CA_PERIPH_SIZE,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE- },
- {
- /* List terminator */
- 0,
- }
+};
+struct mm_region *mem_map = presidio_mem_map;
+static noinline int invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
u64 arg2)+{
- asm volatile("mov x0, %0\n"
"mov x1, %1\n""mov x2, %2\n""mov x3, %3\n""smc #0\n": "+r" (function_id): "r" (arg0), "r" (arg1), "r" (arg2));- return function_id;
+}
+int board_early_init_r(void) +{
- dcache_disable();
- return 0;
+}
+int board_init(void) +{
- unsigned int reg_data, jtag_id;
- /* Enable timer */
- writel(1, CONFIG_SYS_TIMER_BASE);
- /* Enable snoop in CCI400 slave port#4 */
- writel(3, 0xF5595000);
- jtag_id = readl(CA_GLOBAL_JTAG_ID);
- /* If this is HGU variant then do not use
* the Saturn daughter card ref. clk*/- if (jtag_id == 0x1010D8F3) {
reg_data = readl(0xF3100064);/* change multifunc. REF CLK pin to* a simple GPIO pin*/reg_data |= (1 << 1);writel(reg_data, 0xf3100064);- }
- return 0;
+}
+int dram_init(void) +{
- unsigned int ddr_size;
- ddr_size = readl(0x111100c);
- gd->ram_size = ddr_size * 0x100000;
- return 0;
+}
+void reset_cpu(ulong addr) +{
- invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
+}
+#ifdef CONFIG_LAST_STAGE_INIT +int last_stage_init(void) +{
- u32 val;
- val = readl(CA_GLOBAL_BLOCK_RESET);
- val &= ~CA_GLOBAL_BLOCK_RESET_RESET_DMA;
- writel(val, CA_GLOBAL_BLOCK_RESET);
- /* reduce output pclk ~3.7Hz to save power consumption */
- writel(0x000000FF, CA_DMA_SEC_SSP_BAUDRATE_CTRL);
- return 0;
+} +#endif diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig new file mode 100644 index 0000000..45b911c --- /dev/null +++ b/configs/cortina_presidio-asic-base_defconfig @@ -0,0 +1,45 @@ +# Cortina-Access Ltd. Presidio ASIC Board
the defconfig file must not created manually, try this:
make savedefconfig cp defconfig configs/cortina_presidio-asic-base_defconfig
+CONFIG_CORTINA_PLATFORM=y +CONFIG_ARM=y +CONFIG_SYS_ARCH_TIMER=n +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_TEXT_BASE=0x04000000 +CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="G3#" +CONFIG_NR_DRAM_BANKS=1 +CONFIG_CONS_INDEX=0 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_BOOTP_VCI_STRING="U-boot.armv8.presidio" +CONFIG_OF_LIBFDT=y
+CONFIG_MENU=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y
+CONFIG_DM=y +CONFIG_CORTINA_UART=y +CONFIG_REQUIRE_SERIAL_CONSOLE=y +CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y +CONFIG_CORTINA_GPIO=y
+CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 +CONFIG_WDT=y +CONFIG_WDT_CORTINA=y +CONFIG_CMD_WDT=y
+CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
+CONFIG_MMC=n +CONFIG_NET=n +CONFIG_NETDEVICES=n diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h new file mode 100644 index 0000000..d4f7888 --- /dev/null +++ b/include/configs/presidio_asic.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2020 Cortina Access Inc.
- Configuration for Cortina-Access Presidio board.
- */
+#ifndef __PRESIDIO_ASIC_H +#define __PRESIDIO_ASIC_H
+#define CONFIG_BIT64 1
+//#include <generated/autoconf.h>
remove dead code
+#define CA_REG_READ(addr) readl((u64)addr) +#define CA_REG_WRITE(value, addr) writel(value, (u64)addr)
don't use custom I/O accessors
+#define CONFIG_CA77XX 1
new config options should be added in Kconfig
+#define CONFIG_REMAKE_ELF
+#define CONFIG_GICV2
+#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_ARMV8_MULTIENTRY
+/* SMP jump address in DRAM */ +#define CPU_RELEASE_ADDR 0x0740fff8
+#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 +#define CONFIG_SYS_BOOTM_LEN 0x00c00000
+/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 +#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY +#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
+/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xf7011000 +#define GICC_BASE 0xf7012000
don't put register addresses in the config file. Those should come from device-tree anyway. The config file should only set the legacy config options which aren't yet migrated to Kconfig. If you need that in low-level code or so, put the defines there or create a small header file
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x00100000 +#define CONFIG_SYS_MEMTEST_START 0x05000000 +#define CONFIG_SYS_MEMTEST_END 0x0D000000
+/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
+#define CONFIG_SYS_TIMER_BASE 0xf4321000
+/* Use external clock source */ +#define PRESIDIO_APB_CLK 125000000 +#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK
+/* Cortina Serial Configuration */ +#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) +#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1}+#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_SERIAL0 PER_UART0_CFG +#define CONFIG_SYS_SERIAL1 PER_UART1_CFG
+/* BLOCK Reset Definitions */ +#define RESET_OTPROM BIT(29) +#define RESET_SD BIT(28) +#define RESET_EAXI BIT(27) +#define RESET_FBM BIT(26) +#define RESET_LDMA BIT(25) +#define RESET_RCRYPTO BIT(24) +#define RESET_SADB BIT(22) +#define RESET_RCPU1 BIT(21) +#define RESET_RCPU0 BIT(20) +#define RESET_PE1 BIT(19) +#define RESET_PE0 BIT(18) +#define RESET_RTC BIT(17) +#define RESET_DMA BIT(16) +#define RESET_PER BIT(15) +#define RESET_FLASH BIT(14) +#define RESET_GIC400 BIT(10) +#define RESET_SATA BIT(9) +#define RESET_PCIE2 BIT(8) +#define RESET_PCIE1 BIT(7) +#define RESET_PCIE0 BIT(6) +#define RESET_TQM BIT(5) +#define RESET_SDRAM BIT(4) +#define RESET_L3FE BIT(3) +#define RESET_L2TM BIT(2) +#define RESET_L2FE BIT(1) +#define RESET_NI BIT(0)
+/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE
+/* Miscellaneous configurable options */ +#define DDR_BASE 0x00000000 +#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000) +#define CONFIG_LAST_STAGE_INIT
+/* Physical Memory Map */
+/* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 DDR_BASE +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" +#define CONFIG_BOOTARGS "earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* max command args */ +#define CONFIG_SYS_MAXARGS 64
+#endif /* __PRESIDIO_ASIC_H */
Hi Daniel, Thanks for your feedback and guidance. I grok all except the recommendation about migrating out the definition of GICD_BASE and GIDCC_BASE.
your comment was: +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xf7011000 +#define GICC_BASE 0xf7012000
don't put register addresses in the config file. Those should come from device-tree anyway. The config file should only set the legacy config options which aren't yet migrated to Kconfig. If you need that in low-level code or so, put the defines there or create a small header file
However, I think this may be wider concern than just our new ARMv8 board submission.
ARMv8 core components such as:
arch/arm/lib/gic_64.S arch/arm/cpu/armv8/start.S
reference these ARM GIC symbols without going through DT. As a result, many boards define them in their configs/board.h files.
Perhaps this needs to be solved at a later time in bulk for all ARMv8 boards?
see below:
uboot@78d4bae197f9:/build$ find . -type f -exec grep -H GICC_BASE {} ; ./board/cortina/common/armv8/lowlevel_init.S: ldr x1, =GICC_BASE ./board/cortina/common/armv8/lowlevel_init.S: ldr x0, =GICC_BASE ./include/configs/rcar-gen3-common.h:#define GICC_BASE 0xF1020000 ./include/configs/px30_common.h:#define GICC_BASE 0xff132000 ./include/configs/vexpress_aemv8a.h:#define GICC_BASE (0x2c000000) ./include/configs/vexpress_aemv8a.h:#define GICC_BASE (0x2C02f000) ./include/configs/meson64.h:#define GICC_BASE 0xffc02000 ./include/configs/meson64.h:#define GICC_BASE 0xc4302000 ./include/configs/s32v234evb.h:#define GICC_BASE 0x7D002000 ./include/configs/hikey960.h:#define GICC_BASE 0xe82b2000 ./include/configs/hikey.h:#define GICC_BASE 0xf6802000 ./include/configs/sun50i.h:#define GICC_BASE 0x1c82000 ./include/configs/sun50i.h:#define GICC_BASE 0x3022000 ./include/configs/xilinx_zynqmp.h:#define GICC_BASE 0xF9020000 ./arch/arm/include/asm/arch-tegra210/tegra.h:#define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */ ./arch/arm/include/asm/arch-fsl-layerscape/config.h:#define GICC_BASE 0x01402000 ./arch/arm/include/asm/arch-fsl-layerscape/config.h:#define GICC_BASE_64K 0x01420000 ./arch/arm/include/asm/arch-fsl-layerscape/config.h:#define GICC_BASE 0x01402000 ./arch/arm/include/asm/arch-fsl-layerscape/config.h:#define GICC_BASE 0x01420000 ./arch/arm/include/asm/arch-tegra186/tegra.h:#define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */ ./arch/arm/lib/gic_64.S: ldr x1, =GICC_BASE /* GICC_CTLR */ ./arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h:#define GICC_BASE (0x0a20c000) ./arch/arm/mach-socfpga/include/mach/base_addr_s10.h:#define GICC_BASE 0xfffc2000 ./arch/arm/cpu/armv7/sunxi/psci.c:#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15) ./arch/arm/cpu/armv7/sunxi/psci.c: reg = readl(GICC_BASE + GICC_IAR); ./arch/arm/cpu/armv7/sunxi/psci.c: writel(reg, GICC_BASE + GICC_EOIR); ./arch/arm/cpu/armv7/sunxi/psci.c: writel(0xff, GICC_BASE + GICC_PMR); ./arch/arm/cpu/armv7/sunxi/psci.c: setbits_le32(GICC_BASE + GICC_CTLR, BIT(3)); ./arch/arm/cpu/armv8/start.S: ldr x1, =GICC_BASE ./arch/arm/cpu/armv8/start.S: ldr x0, =GICC_BASE ./arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S: ldr x1, =GICC_BASE ./arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S: ldr x1, =GICC_BASE_64K ./arch/arm/cpu/armv8/fsl-layerscape/fdt.c: reg[2] = cpu_to_fdt64(GICC_BASE_64K); ./arch/arm/cpu/armv8/fsl-layerscape/fdt.c: reg[2] = cpu_to_fdt64(GICC_BASE); ./arch/arm/cpu/armv8/start.S.orig: ldr x1, =GICC_BASE ./arch/arm/cpu/armv8/start.S.orig: ldr x0, =GICC_BASE ./arch/arm/mach-rmobile/lowlevel_init_gen3.S: ldr x1, =GICC_BASE ./arch/arm/mach-rmobile/lowlevel_init_gen3.S: ldr x0, =GICC_BASE
On Jan 22, 2020, at 1:24 PM, Daniel Schwierzeck <daniel.schwierzeck@gmail.commailto:daniel.schwierzeck@gmail.com> wrote:
Am 21.01.20 um 11:19 schrieb Alex Nemirovsky: Add basic Presidio G3 engineering board support
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.commailto:alex.nemirovsky@cortina-access.com> ---
Changes in v2: None
arch/arm/Kconfig | 5 ++ arch/arm/dts/Makefile | 2 + arch/arm/dts/ca-presidio-engboard.dts | 69 +++++++++++++++ board/cortina/common/armv8/ca7774_regs.h | 18 ++++ board/cortina/presidio-asic/Kconfig | 20 +++++ board/cortina/presidio-asic/MAINTAINERS | 6 ++ board/cortina/presidio-asic/Makefile | 8 ++ board/cortina/presidio-asic/presidio.c | 126 +++++++++++++++++++++++++++ configs/cortina_presidio-asic-base_defconfig | 45 ++++++++++ include/configs/presidio_asic.h | 123 ++++++++++++++++++++++++++ 10 files changed, 422 insertions(+) create mode 100644 arch/arm/dts/ca-presidio-engboard.dts create mode 100644 board/cortina/common/armv8/ca7774_regs.h create mode 100644 board/cortina/presidio-asic/Kconfig create mode 100644 board/cortina/presidio-asic/MAINTAINERS create mode 100644 board/cortina/presidio-asic/Makefile create mode 100644 board/cortina/presidio-asic/presidio.c create mode 100644 configs/cortina_presidio-asic-base_defconfig create mode 100644 include/configs/presidio_asic.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 36c9c2f..6d95cde 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1638,6 +1638,10 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie.
+config TARGET_PRESIDIO_ASIC + bool "Support Cortina Presidio ASIC Platform" + select ARM64 + endchoice
config ARCH_SUPPORT_TFABOOT @@ -1782,6 +1786,7 @@ source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" +source "board/cortina/presidio-asic/Kconfig" source "board/broadcom/bcm23550_w1d/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcm963158/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0127a91..81db1e6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -849,6 +849,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
+dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb + targets += $(dtb-y)
# Add any required device tree compiler flags here diff --git a/arch/arm/dts/ca-presidio-engboard.dts b/arch/arm/dts/ca-presidio-engboard.dts new file mode 100644 index 0000000..ef371b0 --- /dev/null +++ b/arch/arm/dts/ca-presidio-engboard.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Cortina Access Inc. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + + mmc0: mmc@f4400000 { + compatible = "snps,dw-cortina"; + reg = <0x0 0xf4400000 0x1000>; + bus-width = <4>; + io_ds = <0x77>; + fifo-mode; + sd_dll_ctrl = <0xf43200e8>; + io_drv_ctrl = <0xf432004c>; + }; + + gpio0: gpio-controller@0xf4329280 { + compatible = "cortina,ca-gpio"; + reg = <0x0 0xf4329280 0x24>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + gpio1: gpio-controller@0xf43292a4 { + compatible = "cortina,ca-gpio"; + reg = <0x0 0xf43292a4 0x24>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + watchdog: watchdog@0xf432901c { + compatible = "cortina,ca-wdt"; + reg = <0x0 0xf432901c 0x34>, + <0x0 0xf4320020 0x04>; + status = "okay"; + }; + + uart0: serial@0xf4329148 { + u-boot,dm-pre-reloc; + compatible = "cortina,ca-uart"; + reg = <0x0 0xf4329148 0x30>; + status = "okay"; + }; + + i2c: i2c@f4329120 { + compatible = "cortina,ca-i2c"; + reg = <0x0 0xf4329120 0x28>; + clock-frequency = <400000>; + }; + + sflash: sflash-controller@f4324000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "cortina,ca-sflash"; + reg = <0x0 0xf4324000 0x50>; + reg-names = "sflash-regs"; + flash@0 { + compatible = "jedec,spi-nor"; + spi-rx-bus-width = <1>; + spi-max-frequency = <108000000>; + };
closing bracket is incorrectly indented
+ }; +}; diff --git a/board/cortina/common/armv8/ca7774_regs.h b/board/cortina/common/armv8/ca7774_regs.h new file mode 100644 index 0000000..d997155 --- /dev/null +++ b/board/cortina/common/armv8/ca7774_regs.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015-2020, Cortina-Access Incorporation. + */ + +#ifndef _CA7774_H_ +#define _CA7774_H_ + +#define CA_PERIPH_BASE 0xE0000000UL +#define CA_PERIPH_SIZE 0x20000000UL +#define CA_GLOBAL_BASE 0xf4320000 +#define CA_GLOBAL_JTAG_ID 0xf4320000 +#define CA_GLOBAL_BLOCK_RESET 0xf4320004 +#define CA_GLOBAL_BLOCK_RESET_RESET_DMA BIT(16) +#define CA_DMA_SEC_SSP_BAUDRATE_CTRL 0xf7001b94 +#define CA_DMA_SEC_SSP_ID 0xf7001b80 + +#endif /* _CA7774_H_ */ diff --git a/board/cortina/presidio-asic/Kconfig b/board/cortina/presidio-asic/Kconfig new file mode 100644 index 0000000..8b3f3fd --- /dev/null +++ b/board/cortina/presidio-asic/Kconfig @@ -0,0 +1,20 @@ +if TARGET_PRESIDIO_ASIC +config BIT64 + bool + default y + +config CA77XX + bool + default y + +config SYS_BOARD + default "presidio-asic" + +config SYS_VENDOR + default "cortina" + +config SYS_CONFIG_NAME + default "presidio_asic" + +source "board/cortina/common/Kconfig" +endif diff --git a/board/cortina/presidio-asic/MAINTAINERS b/board/cortina/presidio-asic/MAINTAINERS new file mode 100644 index 0000000..9db17bd --- /dev/null +++ b/board/cortina/presidio-asic/MAINTAINERS @@ -0,0 +1,6 @@ +Cortina Presidio ASIC G3 Engineering BOARD +M: Alex Nemirovsky <alex.nemirovsky@cortina-access.commailto:alex.nemirovsky@cortina-access.com> +S: Supported +F: board/cortina/presidio-asic/ +F: include/configs/presidio_asic.h +F: configs/cortina_presidio-asic*defconfig diff --git a/board/cortina/presidio-asic/Makefile b/board/cortina/presidio-asic/Makefile new file mode 100644 index 0000000..33f8e7c --- /dev/null +++ b/board/cortina/presidio-asic/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2020 Cortina-Access.Inc. +# +# + +obj-y := presidio.o +obj-y += ../common/armv8/lowlevel_init.o diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c new file mode 100644 index 0000000..1bebe28 --- /dev/null +++ b/board/cortina/presidio-asic/presidio.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 - Cortina Access Inc. + * + */ +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <asm/io.h> +#include <linux/compiler.h> +#include <configs/presidio_asic.h> +#include <linux/psci.h> +#include <asm/psci.h> +#include <cpu_func.h> +#include <asm/armv8/mmu.h> +#include "../common/armv8/ca7774_regs.h" + +DECLARE_GLOBAL_DATA_PTR; + +int print_cpuinfo(void) +{ + printf("CPU: Cortina Presidio G3\n"); + return 0; +} + +static struct mm_region presidio_mem_map[] = { + { + .virt = DDR_BASE, + .phys = DDR_BASE, + .size = PHYS_SDRAM_1_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, + { + .virt = CA_PERIPH_BASE, + .phys = CA_PERIPH_BASE, + .size = CA_PERIPH_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = presidio_mem_map; + +static noinline int invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1, + u64 arg2) +{ + asm volatile("mov x0, %0\n" + "mov x1, %1\n" + "mov x2, %2\n" + "mov x3, %3\n" + "smc #0\n" + : "+r" (function_id) + : "r" (arg0), "r" (arg1), "r" (arg2) + ); + + return function_id; +} + +int board_early_init_r(void) +{ + dcache_disable(); + return 0; +} + +int board_init(void) +{ + unsigned int reg_data, jtag_id; + + /* Enable timer */ + writel(1, CONFIG_SYS_TIMER_BASE); + + /* Enable snoop in CCI400 slave port#4 */ + writel(3, 0xF5595000); + + jtag_id = readl(CA_GLOBAL_JTAG_ID); + + /* If this is HGU variant then do not use + * the Saturn daughter card ref. clk + */ + if (jtag_id == 0x1010D8F3) { + reg_data = readl(0xF3100064); + /* change multifunc. REF CLK pin to + * a simple GPIO pin + */ + reg_data |= (1 << 1); + writel(reg_data, 0xf3100064); + } + + return 0; +} + +int dram_init(void) +{ + unsigned int ddr_size; + + ddr_size = readl(0x111100c); + gd->ram_size = ddr_size * 0x100000; + return 0; +} + +void reset_cpu(ulong addr) +{ + invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0); +} + +#ifdef CONFIG_LAST_STAGE_INIT +int last_stage_init(void) +{ + u32 val; + + val = readl(CA_GLOBAL_BLOCK_RESET); + val &= ~CA_GLOBAL_BLOCK_RESET_RESET_DMA; + writel(val, CA_GLOBAL_BLOCK_RESET); + + /* reduce output pclk ~3.7Hz to save power consumption */ + writel(0x000000FF, CA_DMA_SEC_SSP_BAUDRATE_CTRL); + + return 0; +} +#endif diff --git a/configs/cortina_presidio-asic-base_defconfig b/configs/cortina_presidio-asic-base_defconfig new file mode 100644 index 0000000..45b911c --- /dev/null +++ b/configs/cortina_presidio-asic-base_defconfig @@ -0,0 +1,45 @@ +# Cortina-Access Ltd. Presidio ASIC Board
the defconfig file must not created manually, try this:
make savedefconfig cp defconfig configs/cortina_presidio-asic-base_defconfig
+CONFIG_CORTINA_PLATFORM=y +CONFIG_ARM=y +CONFIG_SYS_ARCH_TIMER=n +CONFIG_TARGET_PRESIDIO_ASIC=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_TEXT_BASE=0x04000000 +CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="G3#" +CONFIG_NR_DRAM_BANKS=1 +CONFIG_CONS_INDEX=0 +CONFIG_IDENT_STRING="Presidio-SoC" +CONFIG_BOOTP_VCI_STRING="U-boot.armv8.presidio" +CONFIG_OF_LIBFDT=y + +CONFIG_MENU=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SMC=y + +CONFIG_DM=y +CONFIG_CORTINA_UART=y +CONFIG_REQUIRE_SERIAL_CONSOLE=y +CONFIG_DM_SERIAL=y + +CONFIG_DM_GPIO=y +CONFIG_CORTINA_GPIO=y + +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 +CONFIG_WDT=y +CONFIG_WDT_CORTINA=y +CONFIG_CMD_WDT=y + +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard" + +CONFIG_MMC=n +CONFIG_NET=n +CONFIG_NETDEVICES=n diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h new file mode 100644 index 0000000..d4f7888 --- /dev/null +++ b/include/configs/presidio_asic.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Cortina Access Inc. + * + * Configuration for Cortina-Access Presidio board. + */ + +#ifndef __PRESIDIO_ASIC_H +#define __PRESIDIO_ASIC_H + +#define CONFIG_BIT64 1 + +//#include <generated/autoconf.h>
remove dead code
+ +#define CA_REG_READ(addr) readl((u64)addr) +#define CA_REG_WRITE(value, addr) writel(value, (u64)addr)
don't use custom I/O accessors
+ +#define CONFIG_CA77XX 1
new config options should be added in Kconfig
+ +#define CONFIG_REMAKE_ELF + +#define CONFIG_GICV2 + +#define CONFIG_SUPPORT_RAW_INITRD +#define CONFIG_ARMV8_MULTIENTRY + +/* SMP jump address in DRAM */ +#define CPU_RELEASE_ADDR 0x0740fff8 + +#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 +#define CONFIG_SYS_BOOTM_LEN 0x00c00000 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 +#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY +#define CONFIG_SYS_TIMER_COUNTER 0xf4321008 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xf7011000 +#define GICC_BASE 0xf7012000
don't put register addresses in the config file. Those should come from device-tree anyway. The config file should only set the legacy config options which aren't yet migrated to Kconfig. If you need that in low-level code or so, put the defines there or create a small header file
+ +#define CONFIG_SYS_MEMTEST_SCRATCH 0x00100000 +#define CONFIG_SYS_MEMTEST_START 0x05000000 +#define CONFIG_SYS_MEMTEST_END 0x0D000000 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) + +#define CONFIG_SYS_TIMER_BASE 0xf4321000 + +/* Use external clock source */ +#define PRESIDIO_APB_CLK 125000000 +#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK + +/* Cortina Serial Configuration */ +#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) +#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_SERIAL0 PER_UART0_CFG +#define CONFIG_SYS_SERIAL1 PER_UART1_CFG + +/* BLOCK Reset Definitions */ +#define RESET_OTPROM BIT(29) +#define RESET_SD BIT(28) +#define RESET_EAXI BIT(27) +#define RESET_FBM BIT(26) +#define RESET_LDMA BIT(25) +#define RESET_RCRYPTO BIT(24) +#define RESET_SADB BIT(22) +#define RESET_RCPU1 BIT(21) +#define RESET_RCPU0 BIT(20) +#define RESET_PE1 BIT(19) +#define RESET_PE0 BIT(18) +#define RESET_RTC BIT(17) +#define RESET_DMA BIT(16) +#define RESET_PER BIT(15) +#define RESET_FLASH BIT(14) +#define RESET_GIC400 BIT(10) +#define RESET_SATA BIT(9) +#define RESET_PCIE2 BIT(8) +#define RESET_PCIE1 BIT(7) +#define RESET_PCIE0 BIT(6) +#define RESET_TQM BIT(5) +#define RESET_SDRAM BIT(4) +#define RESET_L3FE BIT(3) +#define RESET_L2TM BIT(2) +#define RESET_L2FE BIT(1) +#define RESET_NI BIT(0) + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* Miscellaneous configurable options */ +#define DDR_BASE 0x00000000 +#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000) +#define CONFIG_LAST_STAGE_INIT + +/* Physical Memory Map */ + +/* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 DDR_BASE +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Initial environment variables */ + +#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" +#define CONFIG_BOOTARGS "earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0" + +/* Monitor Command Prompt */ + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* max command args */ +#define CONFIG_SYS_MAXARGS 64 + +#endif /* __PRESIDIO_ASIC_H */
-- - Daniel
Hi Daniel,
We have a question about one of your feedback points.
On Jan 22, 2020, at 1:24 PM, Daniel Schwierzeck daniel.schwierzeck@gmail.com wrote:
the defconfig file must not created manually, try this:
make savedefconfig cp defconfig configs/cortina_presidio-asic-base_defconfig
We can appreciate that *defconfig should be complete. However we also have a desire to easy maintenance of multiple board *defconfig files variants which differ in key CA features differences. As presidio is a development board, its important to be able to support and easily maintain different but common configuration variants for our customers.
It seems that buildman takes in our partial board varient *defconfig files and autogenerates more complete defconfig called u-boot.cfg at build time. This also, in our opinion, helps to keep our defconfig files from becoming stale with newer revisions of the core u-boot code base.
If this is not acceptable, do you have any recommendation on how we easy our maintenance of multiple board defconfig variants using an alternate approach?
-BR AN
On Tue, Jan 21, 2020 at 10:19:01AM +0000, Alex Nemirovsky wrote:
Cortina Access management has decided that we want to add formal upstream support of u-boot going forward for our line of SoCs and evaluation boards.
[snip]
MAINTAINERS | 18 +++ arch/arm/Kconfig | 5 + arch/arm/dts/Makefile | 2 + arch/arm/dts/ca-presidio-engboard.dts | 69 +++++++++++ arch/arm/include/asm/gpio.h | 2 +- board/cortina/common/Kconfig | 5 + board/cortina/common/armv8/ca7774_regs.h | 18 +++ board/cortina/common/armv8/lowlevel_init.S | 87 ++++++++++++++ board/cortina/presidio-asic/Kconfig | 20 ++++ board/cortina/presidio-asic/MAINTAINERS | 6 + board/cortina/presidio-asic/Makefile | 8 ++ board/cortina/presidio-asic/presidio.c | 126 ++++++++++++++++++++
I should have spotted this sooner, sorry. Why are you doing board/cortina/common/armv8/ rather than arch/arm/mach-xxx/ (and related include directory) as is the norm?
We have many common features across ISAs and common ARM, MIPS, other ISA modification across SoCs. Looking at how this was addressed by other silicon vendors who support multiple ISAs, lead to this path. i.e. TI, freescale, and others.
./board/BuR/common ./board/xilinx/common ./board/atmel/common ./board/ti/common ./board/seco/common ./board/gdsys/common ./board/avionic-design/common ./board/LaCie/common ./board/cortina/common ./board/xes/common ./board/varisys/common ./board/engicam/common ./board/siemens/common ./board/mscc/common ./board/toradex/common ./board/compulab/common ./board/alliedtelesis/common ./board/freescale/common ./board/keymile/common ./board/samsung/common ./board/google/common ./board/ge/common
On Jan 24, 2020, at 7:13 AM, Tom Rini <trini@konsulko.commailto:trini@konsulko.com> wrote:
On Tue, Jan 21, 2020 at 10:19:01AM +0000, Alex Nemirovsky wrote:
Cortina Access management has decided that we want to add formal upstream support of u-boot going forward for our line of SoCs and evaluation boards. [snip] MAINTAINERS | 18 +++ arch/arm/Kconfig | 5 + arch/arm/dts/Makefile | 2 + arch/arm/dts/ca-presidio-engboard.dts | 69 +++++++++++ arch/arm/include/asm/gpio.h | 2 +- board/cortina/common/Kconfig | 5 + board/cortina/common/armv8/ca7774_regs.h | 18 +++ board/cortina/common/armv8/lowlevel_init.S | 87 ++++++++++++++ board/cortina/presidio-asic/Kconfig | 20 ++++ board/cortina/presidio-asic/MAINTAINERS | 6 + board/cortina/presidio-asic/Makefile | 8 ++ board/cortina/presidio-asic/presidio.c | 126 ++++++++++++++++++++
I should have spotted this sooner, sorry. Why are you doing board/cortina/common/armv8/ rather than arch/arm/mach-xxx/ (and related include directory) as is the norm?
-- Tom
On Fri, Jan 24, 2020 at 05:22:50PM +0000, Alex Nemirovsky wrote:
We have many common features across ISAs and common ARM, MIPS, other ISA modification across SoCs. Looking at how this was addressed by other silicon vendors who support multiple ISAs, lead to this path. i.e. TI, freescale, and others.
./board/BuR/common ./board/xilinx/common ./board/atmel/common ./board/ti/common ./board/seco/common ./board/gdsys/common ./board/avionic-design/common ./board/LaCie/common ./board/cortina/common ./board/xes/common ./board/varisys/common ./board/engicam/common ./board/siemens/common ./board/mscc/common ./board/toradex/common ./board/compulab/common ./board/alliedtelesis/common ./board/freescale/common ./board/keymile/common ./board/samsung/common ./board/google/common ./board/ge/common
Yes. And in I believe all of the above cases there is also a relevant arch/*/mach-* directory. This can be a hard distinction to make sometimes, especially at first, but board/VENDOR/common is for the parts that are common but outside of a specific SoC. What you're putting in there that is common between your MIPS and ARM platforms for example. To use board/ti/common as an example there are platforms under arch/arm/mach-omap2/{am33xx,omap5} and arch/arm/mach-k3/ that all share that code.
To use one of your examples, lowlevel_init.S is something that is for the SoC and would be shared by some other vendor that uses your platform, right? It's leveraging features of the SoC itself rather than the PCB design of the board.
Does that help? Thanks!
Looking inside grep -h CA board/cortina/common/armv8/lowlevel_init.S #if defined(CONFIG_SOC_CA7774) #if defined(CONFIG_SOC_CA8277B)
as we understand it, the alternative would lead to maintaining duplicate but slightly different code for each ARM based SoC in arch/arm/mach-ca7774 arch/arm/mach-ca8277B arch/arm/mach-ca7742 arch/arm/mach-ca8279 arch/arm/mach-caXnnn
correct? or should we simply create a arch/arm/mach-caxxxx, arch/mips/mach-caxxxx, arch/xtensa/mach-axxxx, arch/riscv/mach-caxxxx, etc to maintain similar changes to each arch related custom code which varies slightly for each SoC variation within each architecture? What’s best to avoid maintaining duplicate code across SoC variations within the same ISA family?
On Jan 24, 2020, at 9:37 AM, Tom Rini <trini@konsulko.commailto:trini@konsulko.com> wrote:
On Fri, Jan 24, 2020 at 05:22:50PM +0000, Alex Nemirovsky wrote:
We have many common features across ISAs and common ARM, MIPS, other ISA modification across SoCs. Looking at how this was addressed by other silicon vendors who support multiple ISAs, lead to this path. i.e. TI, freescale, and others.
./board/BuR/common ./board/xilinx/common ./board/atmel/common ./board/ti/common ./board/seco/common ./board/gdsys/common ./board/avionic-design/common ./board/LaCie/common ./board/cortina/common ./board/xes/common ./board/varisys/common ./board/engicam/common ./board/siemens/common ./board/mscc/common ./board/toradex/common ./board/compulab/common ./board/alliedtelesis/common ./board/freescale/common ./board/keymile/common ./board/samsung/common ./board/google/common ./board/ge/common
Yes. And in I believe all of the above cases there is also a relevant arch/*/mach-* directory. This can be a hard distinction to make sometimes, especially at first, but board/VENDOR/common is for the parts that are common but outside of a specific SoC. What you're putting in there that is common between your MIPS and ARM platforms for example. To use board/ti/common as an example there are platforms under arch/arm/mach-omap2/{am33xx,omap5} and arch/arm/mach-k3/ that all share that code.
To use one of your examples, lowlevel_init.S is something that is for the SoC and would be shared by some other vendor that uses your platform, right? It's leveraging features of the SoC itself rather than the PCB design of the board.
Does that help? Thanks!
-- Tom
On Fri, Jan 24, 2020 at 05:55:29PM +0000, Alex Nemirovsky wrote:
Looking inside grep -h CA board/cortina/common/armv8/lowlevel_init.S #if defined(CONFIG_SOC_CA7774) #if defined(CONFIG_SOC_CA8277B)
as we understand it, the alternative would lead to maintaining duplicate but slightly different code for each ARM based SoC in arch/arm/mach-ca7774 arch/arm/mach-ca8277B arch/arm/mach-ca7742 arch/arm/mach-ca8279 arch/arm/mach-caXnnn
correct? or should we simply create a arch/arm/mach-caxxxx, arch/mips/mach-caxxxx, arch/xtensa/mach-axxxx, arch/riscv/mach-caxxxx, etc to maintain similar changes to each arch related custom code which varies slightly for each SoC variation within each architecture? What’s best to avoid maintaining duplicate code across SoC variations within the same ISA family?
I would hope we can get by with arch/arm/mach-caxxxx or so and board/cortina/common/. How are you handling common code in the linux kernel?
Sounds good Tom. We will send the next series with the ARMv8 low_level.S moved to arch/mach-caxxxx/ Thanks for you guidance. Did you see anything else in 2nd series that needs modified before we send series 3 or can we assume those are fine to avoid sending another series after this issues is fixed in series 3?
On Jan 24, 2020, at 10:30 AM, Tom Rini trini@konsulko.com wrote:
On Fri, Jan 24, 2020 at 05:55:29PM +0000, Alex Nemirovsky wrote:
Looking inside grep -h CA board/cortina/common/armv8/lowlevel_init.S #if defined(CONFIG_SOC_CA7774) #if defined(CONFIG_SOC_CA8277B)
as we understand it, the alternative would lead to maintaining duplicate but slightly different code for each ARM based SoC in arch/arm/mach-ca7774 arch/arm/mach-ca8277B arch/arm/mach-ca7742 arch/arm/mach-ca8279 arch/arm/mach-caXnnn
correct? or should we simply create a arch/arm/mach-caxxxx, arch/mips/mach-caxxxx, arch/xtensa/mach-axxxx, arch/riscv/mach-caxxxx, etc to maintain similar changes to each arch related custom code which varies slightly for each SoC variation within each architecture? What’s best to avoid maintaining duplicate code across SoC variations within the same ISA family?
I would hope we can get by with arch/arm/mach-caxxxx or so and board/cortina/common/. How are you handling common code in the linux kernel?
-- Tom
On Fri, Jan 24, 2020 at 06:34:40PM +0000, Alex Nemirovsky wrote:
Sounds good Tom. We will send the next series with the ARMv8 low_level.S moved to arch/mach-caxxxx/ Thanks for you guidance. Did you see anything else in 2nd series that needs modified before we send series 3 or can we assume those are fine to avoid sending another series after this issues is fixed in series 3?
That was all I noticed, thanks again.
On Jan 24, 2020, at 10:30 AM, Tom Rini trini@konsulko.com wrote:
On Fri, Jan 24, 2020 at 05:55:29PM +0000, Alex Nemirovsky wrote:
Looking inside grep -h CA board/cortina/common/armv8/lowlevel_init.S #if defined(CONFIG_SOC_CA7774) #if defined(CONFIG_SOC_CA8277B)
as we understand it, the alternative would lead to maintaining duplicate but slightly different code for each ARM based SoC in arch/arm/mach-ca7774 arch/arm/mach-ca8277B arch/arm/mach-ca7742 arch/arm/mach-ca8279 arch/arm/mach-caXnnn
correct? or should we simply create a arch/arm/mach-caxxxx, arch/mips/mach-caxxxx, arch/xtensa/mach-axxxx, arch/riscv/mach-caxxxx, etc to maintain similar changes to each arch related custom code which varies slightly for each SoC variation within each architecture? What’s best to avoid maintaining duplicate code across SoC variations within the same ISA family?
I would hope we can get by with arch/arm/mach-caxxxx or so and board/cortina/common/. How are you handling common code in the linux kernel?
-- Tom
one last thing, since we are moving SoC code out of the board tree. would you prefer each SoC specific header directly in top level include directory or within nclude/cortina subdirectory? i.e. include/ca7774.h vs include/cortina/ca7774.h?
On Jan 24, 2020, at 10:42 AM, Tom Rini trini@konsulko.com wrote:
On Fri, Jan 24, 2020 at 06:34:40PM +0000, Alex Nemirovsky wrote:
Sounds good Tom. We will send the next series with the ARMv8 low_level.S moved to arch/mach-caxxxx/ Thanks for you guidance. Did you see anything else in 2nd series that needs modified before we send series 3 or can we assume those are fine to avoid sending another series after this issues is fixed in series 3?
That was all I noticed, thanks again.
On Jan 24, 2020, at 10:30 AM, Tom Rini trini@konsulko.com wrote:
On Fri, Jan 24, 2020 at 05:55:29PM +0000, Alex Nemirovsky wrote:
Looking inside grep -h CA board/cortina/common/armv8/lowlevel_init.S #if defined(CONFIG_SOC_CA7774) #if defined(CONFIG_SOC_CA8277B)
as we understand it, the alternative would lead to maintaining duplicate but slightly different code for each ARM based SoC in arch/arm/mach-ca7774 arch/arm/mach-ca8277B arch/arm/mach-ca7742 arch/arm/mach-ca8279 arch/arm/mach-caXnnn
correct? or should we simply create a arch/arm/mach-caxxxx, arch/mips/mach-caxxxx, arch/xtensa/mach-axxxx, arch/riscv/mach-caxxxx, etc to maintain similar changes to each arch related custom code which varies slightly for each SoC variation within each architecture? What’s best to avoid maintaining duplicate code across SoC variations within the same ISA family?
I would hope we can get by with arch/arm/mach-caxxxx or so and board/cortina/common/. How are you handling common code in the linux kernel?
-- Tom
-- Tom
On Fri, Jan 24, 2020 at 06:58:13PM +0000, Alex Nemirovsky wrote:
one last thing, since we are moving SoC code out of the board tree. would you prefer each SoC specific header directly in top level include directory or within nclude/cortina subdirectory? i.e. include/ca7774.h vs include/cortina/ca7774.h?
Inside of arch/arm/include/asm/mach-caxxxx/ you can split things how you think makes the most sense. There's many other examples to look at here.
On Jan 24, 2020, at 10:42 AM, Tom Rini trini@konsulko.com wrote:
On Fri, Jan 24, 2020 at 06:34:40PM +0000, Alex Nemirovsky wrote:
Sounds good Tom. We will send the next series with the ARMv8 low_level.S moved to arch/mach-caxxxx/ Thanks for you guidance. Did you see anything else in 2nd series that needs modified before we send series 3 or can we assume those are fine to avoid sending another series after this issues is fixed in series 3?
That was all I noticed, thanks again.
On Jan 24, 2020, at 10:30 AM, Tom Rini trini@konsulko.com wrote:
On Fri, Jan 24, 2020 at 05:55:29PM +0000, Alex Nemirovsky wrote:
Looking inside grep -h CA board/cortina/common/armv8/lowlevel_init.S #if defined(CONFIG_SOC_CA7774) #if defined(CONFIG_SOC_CA8277B)
as we understand it, the alternative would lead to maintaining duplicate but slightly different code for each ARM based SoC in arch/arm/mach-ca7774 arch/arm/mach-ca8277B arch/arm/mach-ca7742 arch/arm/mach-ca8279 arch/arm/mach-caXnnn
correct? or should we simply create a arch/arm/mach-caxxxx, arch/mips/mach-caxxxx, arch/xtensa/mach-axxxx, arch/riscv/mach-caxxxx, etc to maintain similar changes to each arch related custom code which varies slightly for each SoC variation within each architecture? What’s best to avoid maintaining duplicate code across SoC variations within the same ISA family?
I would hope we can get by with arch/arm/mach-caxxxx or so and board/cortina/common/. How are you handling common code in the linux kernel?
-- Tom
-- Tom
participants (3)
-
Alex Nemirovsky -
Daniel Schwierzeck -
Tom Rini