This patch adds support for the s3c2440 cpu to the nand driver. It does this by replacing the existing driver with that from linux 2.6.31.5, modified to make it work in the u-boot mtd nand architecture. Note that the linux s3c2410 nand driver supports s3c2410 and s3c2440, though I haven't been able to test this on an s3c2410 board, only an s3c2440 board.

Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no new warnings or errors were found.

Signed-off-by: Kevin Morfitt kevin.morfitt@fearnside-systems.co.uk drivers/mtd/nand/s3c2410_nand.c | 134 +++++++++++++++++++++------------------ 1 files changed, 73 insertions(+), 61 deletions(-)

diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index 87d0bf6..b8ea581 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -2,6 +2,10 @@ * (C) Copyright 2006 OpenMoko, Inc. * Author: Harald Welte laforge@openmoko.org * + * Modified to add S3C2440 support by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, kevin.morfitt@fearnside-systems.co.uk + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -21,48 +25,53 @@ #include <common.h>

#include <nand.h> +#include <linux/mtd/nand_ecc.h> #include <s3c24x0_cpu.h> #include <asm/io.h>

-#define S3C2410_NFCONF_EN (1<<15) -#define S3C2410_NFCONF_512BYTE (1<<14) -#define S3C2410_NFCONF_4STEP (1<<13) -#define S3C2410_NFCONF_INITECC (1<<12) -#define S3C2410_NFCONF_nFCE (1<<11) -#define S3C2410_NFCONF_TACLS(x) ((x)<<8) -#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) -#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) +#if defined(CONFIG_S3C2410_NAND_HWECC) && defined(CONFIG_SYS_NAND_LARGEPAGE) +/* new oob placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob = { + .eccbytes = 3, + .eccpos = {0, 1, 2}, + .oobfree = { {8, 8} } +}; +#endif

-#define S3C2410_ADDR_NALE 4 -#define S3C2410_ADDR_NCLE 8 +static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) +{ + struct s3c2410_nand *nand = s3c2410_get_base_nand(); + unsigned long reg = readl(&nand->S3C24X0_NAND_CTRL_REG); + + if (chip == -1) { + debugX(1, "Negating nFCE\n"); + reg |= S3C24X0_NAND_nFCE_BIT; + } else { + debugX(1, "Asserting nFCE\n"); + reg &= ~S3C24X0_NAND_nFCE_BIT; + } + writel(reg, &nand->S3C24X0_NAND_CTRL_REG); +}

static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *chip = mtd->priv; struct s3c2410_nand *nand = s3c2410_get_base_nand();

debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);

- if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong)nand; - - if (!(ctrl & NAND_CLE)) - IO_ADDR_W |= S3C2410_ADDR_NCLE; - if (!(ctrl & NAND_ALE)) - IO_ADDR_W |= S3C2410_ADDR_NALE; - - chip->IO_ADDR_W = (void *)IO_ADDR_W; + if (cmd == NAND_CMD_NONE) + return;

- if (ctrl & NAND_NCE) - writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE, - &nand->NFCONF); - else - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE, - &nand->NFCONF); + if (ctrl & NAND_CLE) { + debugX(1, "NFCMD = 0x%08X\n", cmd); + writel(cmd, &nand->NFCMD); }

- if (cmd != NAND_CMD_NONE) - writeb(cmd, chip->IO_ADDR_W); + if (ctrl & NAND_ALE) { + debugX(1, "NFADDR = 0x%08X\n", cmd); + writel(cmd, &nand->NFADDR); + } }

static int s3c2410_dev_ready(struct mtd_info *mtd) @@ -76,39 +85,32 @@ static int s3c2410_dev_ready(struct mtd_info *mtd) void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); + unsigned long reg = readl(&nand->S3C24X0_NAND_CTRL_REG); + debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF); + reg |= S3C24X0_NAND_INITECC_BIT; + writel(reg, &nand->S3C24X0_NAND_CTRL_REG); }

static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { - ecc_code[0] = NFECC0; - ecc_code[1] = NFECC1; - ecc_code[2] = NFECC2; + struct s3c2410_nand *nand = s3c2410_get_base_nand(); + unsigned long ecc = readl(&nand->S3C24X0_NAND_ECC_REG); + + ecc_code[0] = ecc; + ecc_code[1] = ecc >> 8; + ecc_code[2] = ecc >> 16; debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", - mtd , ecc_code[0], ecc_code[1], ecc_code[2]); + mtd, ecc_code[0], ecc_code[1], ecc_code[2]);

return 0; } - -static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *calc_ecc) -{ - if (read_ecc[0] == calc_ecc[0] && - read_ecc[1] == calc_ecc[1] && - read_ecc[2] == calc_ecc[2]) - return 0; - - printf("s3c2410_nand_correct_data: not implemented\n"); - return -1; -} #endif

int board_nand_init(struct nand_chip *nand) { - u_int32_t cfg; - u_int8_t tacls, twrph0, twrph1; + unsigned long reg; struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); struct s3c2410_nand *nand_reg = s3c2410_get_base_nand();

@@ -117,15 +119,12 @@ int board_nand_init(struct nand_chip *nand) writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);

/* initialize hardware */ - twrph0 = 3; - twrph1 = 0; - tacls = 0; - - cfg = S3C2410_NFCONF_EN; - cfg |= S3C2410_NFCONF_TACLS(tacls - 1); - cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); - cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); - writel(cfg, &nand_reg->NFCONF); + reg = S3C24X0_NAND_TACLS_BITS(CONFIG_SYS_NAND_TACLS); + reg |= S3C24X0_NAND_TWRPH0_BITS(CONFIG_SYS_NAND_TWRPH0); + reg |= S3C24X0_NAND_TWRPH1_BITS(CONFIG_SYS_NAND_TWRPH1); + writel(reg, &nand_reg->S3C24X0_NAND_TIMING_REG); + reg = S3C24X0_NAND_EN_BIT | S3C24X0_NAND_nFCE_BIT; + writel(reg, &nand_reg->S3C24X0_NAND_CTRL_REG);

/* initialize nand_chip data structure */ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; @@ -133,16 +132,29 @@ int board_nand_init(struct nand_chip *nand) /* read_buf and write_buf are default */ /* read_byte and write_byte are default */

+ nand->select_chip = s3c2410_nand_select_chip; + nand->chip_delay = 50; + /* hwcontrol always must be implemented */ nand->cmd_ctrl = s3c2410_hwcontrol; - nand->dev_ready = s3c2410_dev_ready;

#ifdef CONFIG_S3C2410_NAND_HWECC - nand->ecc.hwctl = s3c2410_nand_enable_hwecc; - nand->ecc.calculate = s3c2410_nand_calculate_ecc; - nand->ecc.correct = s3c2410_nand_correct_data; - nand->ecc.mode = NAND_ECC_HW3_512; + nand->ecc.correct = nand_correct_data; + nand->ecc.hwctl = s3c2410_nand_enable_hwecc; + nand->ecc.calculate = s3c2410_nand_calculate_ecc; + nand->ecc.mode = NAND_ECC_HW; + /* change the behaviour depending on whether we are using + * the large or small page nand device */ +#ifdef CONFIG_SYS_NAND_LARGEPAGE + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.layout = &nand_hw_eccoob; +#else + nand->ecc.size = 256; + nand->ecc.bytes = 3; +#endif + debugX(2, "ecc: size: %d bytes: %d\n", nand->ecc.size, nand->ecc.bytes); #else nand->ecc.mode = NAND_ECC_SOFT; #endif