[PATCH 1/7] pci: pcie_dw_rockchip: Add rk3588 compatible
From: Jon Lin jon.lin@rock-chips.com
Add compatible for RK3588 SoC.
Signed-off-by: Jon Lin jon.lin@rock-chips.com --- drivers/pci/pcie_dw_rockchip.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 6155710a9f5f..ff121046604a 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -468,6 +468,7 @@ static const struct dm_pci_ops rockchip_pcie_ops = {
static const struct udevice_id rockchip_pcie_ids[] = { { .compatible = "rockchip,rk3568-pcie" }, + { .compatible = "rockchip,rk3588-pcie" }, { } };
From: Jon Lin jon.lin@rock-chips.com
Add support for max_link_speed specified in the PCI DT binding.
Signed-off-by: Jon Lin jon.lin@rock-chips.com [eugen.hristev@collabora.com: port to latest API, set default correctly, align to 80 chars] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- drivers/pci/pcie_dw_rockchip.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index ff121046604a..6a2a5e15646e 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -42,6 +42,7 @@ struct rk_pcie { struct clk_bulk clks; struct reset_ctl_bulk rsts; struct gpio_desc rst_gpio; + u32 gen; };
/* Parameters for the waiting for iATU enabled routine */ @@ -331,7 +332,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) rk_pcie_writel_apb(priv, 0x0, 0xf00040); pcie_dw_setup_host(&priv->dw);
- ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3); + ret = rk_pcie_link_up(priv, priv->gen); if (ret < 0) goto err_link_up;
@@ -351,6 +352,7 @@ err_exit_phy: static int rockchip_pcie_parse_dt(struct udevice *dev) { struct rk_pcie *priv = dev_get_priv(dev); + u32 max_link_speed; int ret;
priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0); @@ -397,6 +399,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) goto rockchip_pcie_parse_dt_err_phy_get_by_index; }
+ ret = ofnode_read_u32(dev_ofnode(dev), "max-link-speed", + &max_link_speed); + if (ret < 0 || max_link_speed > 4) + priv->gen = LINK_SPEED_GEN_3; + else + priv->gen = max_link_speed; + return 0;
rockchip_pcie_parse_dt_err_phy_get_by_index:
Hi Eugen,
On 2023-04-17 11:19, Eugen Hristev wrote:
From: Jon Lin jon.lin@rock-chips.com
Add support for max_link_speed specified in the PCI DT binding.
Signed-off-by: Jon Lin jon.lin@rock-chips.com [eugen.hristev@collabora.com: port to latest API, set default correctly, align to 80 chars] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
drivers/pci/pcie_dw_rockchip.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index ff121046604a..6a2a5e15646e 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -42,6 +42,7 @@ struct rk_pcie { struct clk_bulk clks; struct reset_ctl_bulk rsts; struct gpio_desc rst_gpio;
- u32 gen;
};
/* Parameters for the waiting for iATU enabled routine */ @@ -331,7 +332,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) rk_pcie_writel_apb(priv, 0x0, 0xf00040); pcie_dw_setup_host(&priv->dw);
- ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3);
- ret = rk_pcie_link_up(priv, priv->gen); if (ret < 0) goto err_link_up;
@@ -351,6 +352,7 @@ err_exit_phy: static int rockchip_pcie_parse_dt(struct udevice *dev) { struct rk_pcie *priv = dev_get_priv(dev);
u32 max_link_speed; int ret;
priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
@@ -397,6 +399,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) goto rockchip_pcie_parse_dt_err_phy_get_by_index; }
- ret = ofnode_read_u32(dev_ofnode(dev), "max-link-speed",
&max_link_speed);
I would recommend to use the related dev_read function here, possible something like this:
priv->gen = dev_read_u32_default(dev, "max-link-speed", LINK_SPEED_GEN_3);
Regards, Jonas
- if (ret < 0 || max_link_speed > 4)
priv->gen = LINK_SPEED_GEN_3;- else
priv->gen = max_link_speed;- return 0;
rockchip_pcie_parse_dt_err_phy_get_by_index:
Some variants of the PHY have more than just one reset. To cover all cases, request the rests in bulk rather than just the reset at index 0.
Co-developed-by: Ren Jianing jianing.ren@rock-chips.com Signed-off-by: Ren Jianing jianing.ren@rock-chips.com Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 78da5fe79700..b673a8da9f8e 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -76,7 +76,7 @@ struct rockchip_combphy_priv { struct regmap *pipe_grf; struct regmap *phy_grf; struct phy *phy; - struct reset_ctl phy_rst; + struct reset_ctl_bulk phy_rsts; struct clk ref_clk; const struct rockchip_combphy_cfg *cfg; }; @@ -189,7 +189,7 @@ static int rockchip_combphy_init(struct phy *phy) if (ret) goto err_clk;
- reset_deassert(&priv->phy_rst); + reset_deassert_bulk(&priv->phy_rsts);
return 0;
@@ -204,7 +204,7 @@ static int rockchip_combphy_exit(struct phy *phy) struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
clk_disable(&priv->ref_clk); - reset_assert(&priv->phy_rst); + reset_assert_bulk(&priv->phy_rsts);
return 0; } @@ -255,7 +255,7 @@ static int rockchip_combphy_parse_dt(struct udevice *dev, return PTR_ERR(&priv->ref_clk); }
- ret = reset_get_by_index(dev, 0, &priv->phy_rst); + ret = reset_get_bulk(dev, &priv->phy_rsts); if (ret) { dev_err(dev, "no phy reset control specified\n"); return ret;
On 2023/4/17 17:19, Eugen Hristev wrote:
Some variants of the PHY have more than just one reset. To cover all cases, request the rests in bulk rather than just the reset at index 0.
Co-developed-by: Ren Jianing jianing.ren@rock-chips.com Signed-off-by: Ren Jianing jianing.ren@rock-chips.com Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 78da5fe79700..b673a8da9f8e 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -76,7 +76,7 @@ struct rockchip_combphy_priv { struct regmap *pipe_grf; struct regmap *phy_grf; struct phy *phy;
- struct reset_ctl phy_rst;
- struct reset_ctl_bulk phy_rsts; struct clk ref_clk; const struct rockchip_combphy_cfg *cfg; };
@@ -189,7 +189,7 @@ static int rockchip_combphy_init(struct phy *phy) if (ret) goto err_clk;
- reset_deassert(&priv->phy_rst);
reset_deassert_bulk(&priv->phy_rsts);
return 0;
@@ -204,7 +204,7 @@ static int rockchip_combphy_exit(struct phy *phy) struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
clk_disable(&priv->ref_clk);
- reset_assert(&priv->phy_rst);
reset_assert_bulk(&priv->phy_rsts);
return 0; }
@@ -255,7 +255,7 @@ static int rockchip_combphy_parse_dt(struct udevice *dev, return PTR_ERR(&priv->ref_clk); }
- ret = reset_get_by_index(dev, 0, &priv->phy_rst);
- ret = reset_get_bulk(dev, &priv->phy_rsts); if (ret) { dev_err(dev, "no phy reset control specified\n"); return ret;
From: Jon Lin jon.lin@rock-chips.com
Add support for rk3588 phy variant. The PHY clock is fixed at 100MHz.
Signed-off-by: Jon Lin jon.lin@rock-chips.com [kever.yang@rock-chips.com: update pcie pll parameters] Co-developed-by: Kever Yang kever.yang@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com [eugen.hristev@collabora.com: squashed, tidy up] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- .../rockchip/phy-rockchip-naneng-combphy.c | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index b673a8da9f8e..d5408ccac976 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -58,6 +58,7 @@ struct rockchip_combphy_grfcfg { struct combphy_reg con2_for_sata; struct combphy_reg con3_for_sata; struct combphy_reg pipe_con0_for_sata; + struct combphy_reg pipe_con1_for_sata; struct combphy_reg pipe_sgmii_mac_sel; struct combphy_reg pipe_xpcs_phy_ready; struct combphy_reg u3otg0_port_en; @@ -423,11 +424,105 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { .combphy_cfg = rk3568_combphy_cfg, };
+static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + case PHY_TYPE_SATA: + param_write(priv->phy_grf, &cfg->con0_for_sata, true); + param_write(priv->phy_grf, &cfg->con1_for_sata, true); + param_write(priv->phy_grf, &cfg->con2_for_sata, true); + param_write(priv->phy_grf, &cfg->con3_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); + break; + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + /* 100MHz refclock signal is good */ + clk_set_rate(&priv->ref_clk, 100000000); + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~GENMASK(4, 2); + val |= 0x4 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ + val = 0x4c; + writel(val, priv->mmio + (0x1b << 2)); + + /* Set up su_trim: T3 */ + val = 0xb0; + writel(val, priv->mmio + (0xa << 2)); + val = 0x47; + writel(val, priv->mmio + (0xb << 2)); + val = 0x57; + writel(val, priv->mmio + (0xd << 2)); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, + /* pipe-grf */ + .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, + .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, +}; + +static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { + .grfcfg = &rk3588_combphy_grfcfgs, + .combphy_cfg = rk3588_combphy_cfg, +}; + static const struct udevice_id rockchip_combphy_ids[] = { { .compatible = "rockchip,rk3568-naneng-combphy", .data = (ulong)&rk3568_combphy_cfgs }, + { + .compatible = "rockchip,rk3588-naneng-combphy", + .data = (ulong)&rk3588_combphy_cfgs + }, { } };
On 2023/4/17 17:19, Eugen Hristev wrote:
From: Jon Lin jon.lin@rock-chips.com
Add support for rk3588 phy variant. The PHY clock is fixed at 100MHz.
Signed-off-by: Jon Lin jon.lin@rock-chips.com [kever.yang@rock-chips.com: update pcie pll parameters] Co-developed-by: Kever Yang kever.yang@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com [eugen.hristev@collabora.com: squashed, tidy up] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
.../rockchip/phy-rockchip-naneng-combphy.c | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index b673a8da9f8e..d5408ccac976 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -58,6 +58,7 @@ struct rockchip_combphy_grfcfg { struct combphy_reg con2_for_sata; struct combphy_reg con3_for_sata; struct combphy_reg pipe_con0_for_sata;
- struct combphy_reg pipe_con1_for_sata; struct combphy_reg pipe_sgmii_mac_sel; struct combphy_reg pipe_xpcs_phy_ready; struct combphy_reg u3otg0_port_en;
@@ -423,11 +424,105 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { .combphy_cfg = rk3568_combphy_cfg, };
+static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) +{
- const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
- u32 val;
- switch (priv->mode) {
- case PHY_TYPE_PCIE:
param_write(priv->phy_grf, &cfg->con0_for_pcie, true);param_write(priv->phy_grf, &cfg->con1_for_pcie, true);param_write(priv->phy_grf, &cfg->con2_for_pcie, true);param_write(priv->phy_grf, &cfg->con3_for_pcie, true);break;- case PHY_TYPE_USB3:
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);param_write(priv->phy_grf, &cfg->usb_mode_set, true);break;- case PHY_TYPE_SATA:
param_write(priv->phy_grf, &cfg->con0_for_sata, true);param_write(priv->phy_grf, &cfg->con1_for_sata, true);param_write(priv->phy_grf, &cfg->con2_for_sata, true);param_write(priv->phy_grf, &cfg->con3_for_sata, true);param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);break;- case PHY_TYPE_SGMII:
- case PHY_TYPE_QSGMII:
- default:
dev_err(priv->dev, "incompatible PHY type\n");return -EINVAL;- }
- /* 100MHz refclock signal is good */
- clk_set_rate(&priv->ref_clk, 100000000);
- param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
- if (priv->mode == PHY_TYPE_PCIE) {
/* PLL KVCO tuning fine */val = readl(priv->mmio + (0x20 << 2));val &= ~GENMASK(4, 2);val |= 0x4 << 2;writel(val, priv->mmio + (0x20 << 2));/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */val = 0x4c;writel(val, priv->mmio + (0x1b << 2));/* Set up su_trim: T3 */val = 0xb0;writel(val, priv->mmio + (0xa << 2));val = 0x47;writel(val, priv->mmio + (0xb << 2));val = 0x57;writel(val, priv->mmio + (0xd << 2));- }
- return 0;
+}
+static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
- /* pipe-phy-grf */
- .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
- .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
- .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
- .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
- .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
- .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
- .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
- .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
- .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
- .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
- .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
- .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
- .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
- .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
- .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
- .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
- .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
- .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
- .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
- .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
- /* pipe-grf */
- .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
- .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
+};
+static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
- .grfcfg = &rk3588_combphy_grfcfgs,
- .combphy_cfg = rk3588_combphy_cfg,
+};
- static const struct udevice_id rockchip_combphy_ids[] = { { .compatible = "rockchip,rk3568-naneng-combphy", .data = (ulong)&rk3568_combphy_cfgs },
- {
.compatible = "rockchip,rk3588-naneng-combphy",.data = (ulong)&rk3588_combphy_cfgs- }, { } };
From: Joseph Chen chenjh@rock-chips.com
Add the node for pciE 2x1l 2 device together with the corresponding combphy.
Signed-off-by: Joseph Chen chenjh@rock-chips.com [eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor adaptations] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- arch/arm/dts/rk3588s-u-boot.dtsi | 73 ++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index f23112bf7ab6..17348c8f9789 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -4,6 +4,7 @@ */
#include "rockchip-u-boot.dtsi" +#include <dt-bindings/phy/phy.h>
/ { dmc { @@ -58,6 +59,11 @@ reg = <0x0 0xfd58a000 0x0 0x2000>; };
+ pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; @@ -104,6 +110,58 @@ }; };
+ pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + num-ib-windows = <8>; + num-ob-windows = <8>; + max-link-speed = <2>; + msi-map = <0x4000 &gic 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PHP>; + ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 + 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 + 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000 + 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x400000>, + <0x0 0xfe190000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE4_POWER_UP>; + reset-names = "pipe"; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + sfc: spi@fe2b0000 { compatible = "rockchip,sfc"; reg = <0x0 0xfe2b0000 0x0 0x4000>; @@ -128,6 +186,21 @@ reg = <0x07 0x10>; }; }; + + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>; + clock-names = "refclk", "apbclk"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; };
&xin24m {
Hi Eugen,
On 2023-04-17 11:19, Eugen Hristev wrote:
From: Joseph Chen chenjh@rock-chips.com
Add the node for pciE 2x1l 2 device together with the corresponding combphy.
Signed-off-by: Joseph Chen chenjh@rock-chips.com [eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor adaptations] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
arch/arm/dts/rk3588s-u-boot.dtsi | 73 ++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index f23112bf7ab6..17348c8f9789 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -4,6 +4,7 @@ */
#include "rockchip-u-boot.dtsi" +#include <dt-bindings/phy/phy.h>
/ { dmc { @@ -58,6 +59,11 @@ reg = <0x0 0xfd58a000 0x0 0x2000>; };
- pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,pipe-phy-grf", "syscon";reg = <0x0 0xfd5bc000 0x0 0x100>;- };
- usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
@@ -104,6 +110,58 @@ }; };
- pcie2x1l2: pcie@fe190000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";#address-cells = <3>;#size-cells = <2>;bus-range = <0x40 0x4f>;clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,<&cru CLK_PCIE_AUX4>;clock-names = "aclk_mst", "aclk_slv","aclk_dbi", "pclk", "aux";device_type = "pci";interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;interrupt-names = "sys", "pmc", "msg", "legacy", "err";#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 7>;interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,<0 0 0 2 &pcie2x1l2_intc 1>,<0 0 0 3 &pcie2x1l2_intc 2>,<0 0 0 4 &pcie2x1l2_intc 3>;linux,pci-domain = <4>;num-ib-windows = <8>;num-ob-windows = <8>;max-link-speed = <2>;msi-map = <0x4000 &gic 0x4000 0x1000>;num-lanes = <1>;phys = <&combphy0_ps PHY_TYPE_PCIE>;phy-names = "pcie-phy";power-domains = <&power RK3588_PD_PHP>;ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x1000000x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x1000000x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe000000xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;reg = <0xa 0x41000000 0x0 0x400000>,<0x0 0xfe190000 0x0 0x10000>;reg-names = "pcie-dbi", "pcie-apb";
These reg-names are not fully compatible with the mainline linux binding for the rk3568 variant, see [1]. Please use the reg-names as defined in the mainline binding: dbi and apb.
In a pending patch to fix pcie/nvme on rk3568 I am planing to change to get reg addr by name instead of index, as part of the fix to use correct cfg_base.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Doc...
Regards, Jonas
resets = <&cru SRST_PCIE4_POWER_UP>;reset-names = "pipe";status = "disabled";pcie2x1l2_intc: legacy-interrupt-controller {interrupt-controller;#address-cells = <0>;#interrupt-cells = <1>;interrupt-parent = <&gic>;interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;};- };
- sfc: spi@fe2b0000 { compatible = "rockchip,sfc"; reg = <0x0 0xfe2b0000 0x0 0x4000>;
@@ -128,6 +186,21 @@ reg = <0x07 0x10>; }; };
- combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee00000 0x0 0x100>;#phy-cells = <1>;clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>;clock-names = "refclk", "apbclk";assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;assigned-clock-rates = <100000000>;resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;reset-names = "combphy-apb", "combphy";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy0_grf>;status = "disabled";- };
};
&xin24m {
On 2023-04-18 22:54, Jonas Karlman wrote:
Hi Eugen,
On 2023-04-17 11:19, Eugen Hristev wrote:
From: Joseph Chen chenjh@rock-chips.com
Add the node for pciE 2x1l 2 device together with the corresponding combphy.
Signed-off-by: Joseph Chen chenjh@rock-chips.com [eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor adaptations] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
arch/arm/dts/rk3588s-u-boot.dtsi | 73 ++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index f23112bf7ab6..17348c8f9789 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -4,6 +4,7 @@ */
#include "rockchip-u-boot.dtsi" +#include <dt-bindings/phy/phy.h>
/ { dmc { @@ -58,6 +59,11 @@ reg = <0x0 0xfd58a000 0x0 0x2000>; };
- pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,pipe-phy-grf", "syscon";reg = <0x0 0xfd5bc000 0x0 0x100>;- };
- usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
@@ -104,6 +110,58 @@ }; };
- pcie2x1l2: pcie@fe190000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";#address-cells = <3>;#size-cells = <2>;bus-range = <0x40 0x4f>;clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,<&cru CLK_PCIE_AUX4>;clock-names = "aclk_mst", "aclk_slv","aclk_dbi", "pclk", "aux";device_type = "pci";interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;interrupt-names = "sys", "pmc", "msg", "legacy", "err";#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 7>;interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,<0 0 0 2 &pcie2x1l2_intc 1>,<0 0 0 3 &pcie2x1l2_intc 2>,<0 0 0 4 &pcie2x1l2_intc 3>;linux,pci-domain = <4>;num-ib-windows = <8>;num-ob-windows = <8>;max-link-speed = <2>;msi-map = <0x4000 &gic 0x4000 0x1000>;num-lanes = <1>;phys = <&combphy0_ps PHY_TYPE_PCIE>;phy-names = "pcie-phy";power-domains = <&power RK3588_PD_PHP>;ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x1000000x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x1000000x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe000000xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;reg = <0xa 0x41000000 0x0 0x400000>,<0x0 0xfe190000 0x0 0x10000>;reg-names = "pcie-dbi", "pcie-apb";These reg-names are not fully compatible with the mainline linux binding for the rk3568 variant, see [1]. Please use the reg-names as defined in the mainline binding: dbi and apb.
In a pending patch to fix pcie/nvme on rk3568 I am planing to change to get reg addr by name instead of index, as part of the fix to use correct cfg_base.
I tested this series together with work-in-progress patches for rk3568, see [1], still an issue with BARs from the RC claiming the entire memory region to work around on rk3568.
Made small fixups for this series to base the device tree node on mainline node at [3]. I also made a small adjustment to the ranges so that the memory region falls within a 32-bit address space. Please feel free to squash the fixups if you agree with them :-)
On my ROCK 5 Model B:
=> pci enum PCI Autoconfig: Bus Memory region: [40000000-7fffffff], Physical Memory [a00000000-a3fffffff] PCI Autoconfig: Bus I/O region: [f4100000-f41fffff], Physical Memory [f4100000-f41fffff] PCI Autoconfig: ROM, size=0x10000, address=0x40000000 bus_lower=0x40010000 PCI Autoconfig: BAR 0, I/O, size=0x100, address=0xf4100000 bus_lower=0xf4100100 PCI Autoconfig: BAR 1, Mem64, size=0x10000, address=0x40100000 bus_lower=0x40110000 PCI Autoconfig: BAR 2, Mem64, size=0x4000, address=0x40110000 bus_lower=0x40114000
=> pci BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1d87 0x3588 Bridge device 0x04 01.00.00 0x10ec 0x8125 Network controller 0x00
[2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-pcie-v1 [3] https://patchwork.kernel.org/project/linux-rockchip/patch/20230310080518.780...
Regards, Jonas
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Doc...
Regards, Jonas
resets = <&cru SRST_PCIE4_POWER_UP>;reset-names = "pipe";status = "disabled";pcie2x1l2_intc: legacy-interrupt-controller {interrupt-controller;#address-cells = <0>;#interrupt-cells = <1>;interrupt-parent = <&gic>;interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;};- };
- sfc: spi@fe2b0000 { compatible = "rockchip,sfc"; reg = <0x0 0xfe2b0000 0x0 0x4000>;
@@ -128,6 +186,21 @@ reg = <0x07 0x10>; }; };
- combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee00000 0x0 0x100>;#phy-cells = <1>;clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>;clock-names = "refclk", "apbclk";assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;assigned-clock-rates = <100000000>;resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;reset-names = "combphy-apb", "combphy";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy0_grf>;status = "disabled";- };
};
&xin24m {
On 2023/4/17 17:19, Eugen Hristev wrote:
From: Joseph Chen chenjh@rock-chips.com
Add the node for pciE 2x1l 2 device together with the corresponding combphy.
Signed-off-by: Joseph Chen chenjh@rock-chips.com [eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor adaptations] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
arch/arm/dts/rk3588s-u-boot.dtsi | 73 ++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index f23112bf7ab6..17348c8f9789 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -4,6 +4,7 @@ */
#include "rockchip-u-boot.dtsi" +#include <dt-bindings/phy/phy.h>
/ { dmc { @@ -58,6 +59,11 @@ reg = <0x0 0xfd58a000 0x0 0x2000>; };
- pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,pipe-phy-grf", "syscon";reg = <0x0 0xfd5bc000 0x0 0x100>;- };
- usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
@@ -104,6 +110,58 @@ }; };
- pcie2x1l2: pcie@fe190000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
The mainline kernel should have this node, we should sync with kernel?
Thanks,
- Kever
#address-cells = <3>;#size-cells = <2>;bus-range = <0x40 0x4f>;clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,<&cru CLK_PCIE_AUX4>;clock-names = "aclk_mst", "aclk_slv","aclk_dbi", "pclk", "aux";device_type = "pci";interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;interrupt-names = "sys", "pmc", "msg", "legacy", "err";#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 7>;interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,<0 0 0 2 &pcie2x1l2_intc 1>,<0 0 0 3 &pcie2x1l2_intc 2>,<0 0 0 4 &pcie2x1l2_intc 3>;linux,pci-domain = <4>;num-ib-windows = <8>;num-ob-windows = <8>;max-link-speed = <2>;msi-map = <0x4000 &gic 0x4000 0x1000>;num-lanes = <1>;phys = <&combphy0_ps PHY_TYPE_PCIE>;phy-names = "pcie-phy";power-domains = <&power RK3588_PD_PHP>;ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x1000000x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x1000000x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe000000xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;reg = <0xa 0x41000000 0x0 0x400000>,<0x0 0xfe190000 0x0 0x10000>;reg-names = "pcie-dbi", "pcie-apb";resets = <&cru SRST_PCIE4_POWER_UP>;reset-names = "pipe";status = "disabled";pcie2x1l2_intc: legacy-interrupt-controller {interrupt-controller;#address-cells = <0>;#interrupt-cells = <1>;interrupt-parent = <&gic>;interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;};- };
- sfc: spi@fe2b0000 { compatible = "rockchip,sfc"; reg = <0x0 0xfe2b0000 0x0 0x4000>;
@@ -128,6 +186,21 @@ reg = <0x07 0x10>; }; };
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee00000 0x0 0x100>;#phy-cells = <1>;clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>;clock-names = "refclk", "apbclk";assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;assigned-clock-rates = <100000000>;resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;reset-names = "combphy-apb", "combphy";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy0_grf>;status = "disabled";}; };
&xin24m {
From: Christopher Obbard chris.obbard@collabora.com
Enable the pciE 2x1l 2 device and associated combphy. On this bus, the Rock5B has an Ethernet transceiver connected.
Signed-off-by: Christopher Obbard chris.obbard@collabora.com [eugen.hristev@collabora.com: minor tweaks] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 8a5b0ce42034..8293738407c4 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -31,10 +31,21 @@ }; };
+&combphy0_ps { + status = "okay"; +}; + &fspim2_pins { bootph-all; };
+&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + &sdmmc { bus-width = <4>; bootph-all; @@ -45,6 +56,12 @@ &pinctrl { bootph-all;
+ pcie { + pcie_reset_h: pcie-reset-h { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
Add drivers for pciE , phy, and command.
Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- configs/rock5b-rk3588_defconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 8c097ab3a109..a14fcd2ee924 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -47,6 +47,7 @@ CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -71,7 +72,10 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_SPL_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y @@ -81,7 +85,6 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y -# CONFIG_BINMAN_FDT is not set CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y @@ -95,4 +98,5 @@ CONFIG_USB_ETHER_LAN78XX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +# CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y
Hi Eugen,
On 2023/4/17 17:19, Eugen Hristev wrote:
Add drivers for pciE , phy, and command.
Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
configs/rock5b-rk3588_defconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 8c097ab3a109..a14fcd2ee924 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -47,6 +47,7 @@ CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -71,7 +72,10 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
Does this board have pcie2 interface and need to enable in U-Boot?
CONFIG_SPL_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y @@ -81,7 +85,6 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y -# CONFIG_BINMAN_FDT is not set CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y @@ -95,4 +98,5 @@ CONFIG_USB_ETHER_LAN78XX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +# CONFIG_BINMAN_FDT is not set
This should have been removed after [1]
Thanks,
- Kever
[1]https://patchwork.ozlabs.org/project/uboot/patch/20230417190708.1982556-2-jo...
CONFIG_ERRNO_STR=y
On 2023/4/17 17:19, Eugen Hristev wrote:
From: Jon Lin jon.lin@rock-chips.com
Add compatible for RK3588 SoC.
Signed-off-by: Jon Lin jon.lin@rock-chips.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
drivers/pci/pcie_dw_rockchip.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 6155710a9f5f..ff121046604a 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -468,6 +468,7 @@ static const struct dm_pci_ops rockchip_pcie_ops = {
static const struct udevice_id rockchip_pcie_ids[] = { { .compatible = "rockchip,rk3568-pcie" },
- { .compatible = "rockchip,rk3588-pcie" }, { } };
participants (3)
-
Eugen Hristev -
Jonas Karlman -
Kever Yang