Re: [U-Boot] [PATCH 1/2] common: make bouncebuf work for non-DMA transfers

Simon Goldschmidt wrote:
Marek Vasut wrote:
So what alignment problems do you observe ? If you copy using the CPU only, why do you need the bounce buffer at all ? I don't quite get it.
Sorry for not explaining it good enough: I don't observe any alignment problems. mach-socfpga can do unaligned accesses as well. This driver does CPU based copy, but since it transfers words, not bytes, I guess on other platforms, the CPU might fail when trying to read a word from an unaligned pointer.
Vignesh added this about a year ago and from that commit message, it seems like he was observing alignment errors on his TI platform. Also, those commits have a reviewed-by tag from you and Jagan.
For me, reverting these patches would be OK as well, but I guess Vinesh's TI platform kind of needs them?
So to clarify it again, the cadence_spi driver has to transfer 32-bit words to/from the hardware and the driver uses 'readsl' and 'writesl' to do this. Now if the source/destination buffer is not aligned, this results in an error on platforms that do not support unaligned access.
We have three options here: a) fix all call stacks calling dm_spi_ops->xfer to use aligned buffers (which could be hard when looking at 'sf read') b) fix the driver by doing malloc + memcpy or loading byte by byte from ram c) add framework functions doing malloc + memcpy (which is nearly the same as bouncebuf)
This 32-bit spi transfer mode does not seem to be used too often, all other drivers I looked at are transferring byte by byte and thus can not be used as an example.
Additionally, the TI platform Vignesh used obviously does not support unaligned access (which is why he added using bouncebuf here although no dma is used) while mach-socfpga supports unaligned accesses by default.
So given my explanation above, what's the preferred way to fix this?
I thought a framework solution would be better, which is why I modified bouncebuf to work with this, but as cadence_qspi is the only driver using bouncebuf in this fashion for now, I'm open for suggestions.
I need this driver fixed, so whatever way will be accepted is fine by me, I guess. Just let me know.
Simon

Hi Simon,
On Thursday 16 November 2017 03:39 PM, Goldschmidt Simon wrote: [...]
This 32-bit spi transfer mode does not seem to be used too often, all other drivers I looked at are transferring byte by byte and thus can not be used as an example.
Additionally, the TI platform Vignesh used obviously does not support unaligned access (which is why he added using bouncebuf here although no dma is used) while mach-socfpga supports unaligned accesses by default.
Its not actually unaligned access, cadence QSPI IP on TI platforms do not support non-byte accesses except for the last word. As per the TRM: "The external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer"
So given my explanation above, what's the preferred way to fix this?
Sorry, I overlooked the fact that bounce_buffer_stop() is calling invalidate_dcache_range(). Somehow, this did not show problems on my platform although its a writeback cache.
I would suggest to revert commit b63b46313 ("spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"). I have seen that non 32 bit accesses cause problems only while writing to flash but not during read operations although the TRM states that both reads and writes are affected. But, since reverting b63b46313 as such does not break TI platforms, I would prefer sending a revert. Meanwhile, I will work on a better patch later.
I thought a framework solution would be better, which is why I modified bouncebuf to work with this, but as cadence_qspi is the only driver using bouncebuf in this fashion for now, I'm open for suggestions.
Lets not touch bouncebuf for now.
I need this driver fixed, so whatever way will be accepted is fine by me, I guess. Just let me know.
Sorry for the trouble. I am okay with reverting the patch affecting read path.
participants (2)
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Goldschmidt Simon
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Vignesh R