[U-Boot-Users] PATCH: IBM440Ref Platform (Ocotea) interrupt
PATCH:
This patch brings the ocotea port up to date with the recent patch for 440GX native interrupt mode.
CHANGELOG * Travis Sawyer 11Mar2004 Fix ocotea board early init interrupt setup.
Patch is attached.
Travis
Greetings u-boot'ers:
Is anyone working on Gigabit Ethernet PHY support for u-boot?
Wanted to ask before I reinvent the wheel...
thanx
travis
In message 1079020123.17587.135.camel@pavement.sandburst.com you wrote:
Is anyone working on Gigabit Ethernet PHY support for u-boot?
What _exactly_ are you looking for?
Wanted to ask before I reinvent the wheel...
Then just use the existing Intel e1000 driver.
Best regards,
Wolfgang Denk
On Thu, 2004-03-11 at 11:02, Wolfgang Denk wrote:
In message 1079020123.17587.135.camel@pavement.sandburst.com you wrote:
Is anyone working on Gigabit Ethernet PHY support for u-boot?
What _exactly_ are you looking for?
The IBM 440GX supports GbE on the 2nd and 3rd ports, if a gigabit capable phy is in place that is.
The current miiphy_utils (specifically miiphy_speed and miiphy_duplex) read the phy autonegiotation link partner ability register (reg 0x05) to determine current link speed and duplex.
Register 5 is a standard IEEE802.3 register. However, in order to get 'true' status (10/100/1000), extended registers are needed.
In the case of the ocotea board, IBM placed a LXT9762 (6 port phy) for emac 0 and 1 (as they only support 10/100), and two (2) cicada CIS8201 phys for emac 2 and 3 (supports 10/100/1000).
The problem I see is that the extended register set may not be the same across the phy part spectrum. So, one would need to check the OUI and then go to the appropriate register for that part. Which, IMHO, would add quite a bit of code.
Perhaps for my application I should force 1000 Gbps off in the autonegotiation register...
-travis
Travis:
The Marvell 88E1111 PHYs work at 100M without changing the miiphy_speed function. Of course the extended registers are different and a wack of register 0x14 is needed for the correct RGMII settings for the 440GX. I used the mii command for the wack and have not changed u-boot. I did not persue 1000M because my TFTP server runs at 100M.
The Marvell PHYs must have the correct hard reset waveform to function correctly. You may want to check the hardware reset waveform for the CIS8201 PHY and then check the IEEE register status for proper indications.
Carl
--- Travis Sawyer tsawyer+u-boot@sandburst.com wrote:
On Thu, 2004-03-11 at 11:02, Wolfgang Denk wrote:
In message
1079020123.17587.135.camel@pavement.sandburst.com you wrote:
Is anyone working on Gigabit Ethernet PHY
support for u-boot?
What _exactly_ are you looking for?
The IBM 440GX supports GbE on the 2nd and 3rd ports, if a gigabit capable phy is in place that is.
The current miiphy_utils (specifically miiphy_speed and miiphy_duplex) read the phy autonegiotation link partner ability register (reg 0x05) to determine current link speed and duplex.
Register 5 is a standard IEEE802.3 register. However, in order to get 'true' status (10/100/1000), extended registers are needed.
In the case of the ocotea board, IBM placed a LXT9762 (6 port phy) for emac 0 and 1 (as they only support 10/100), and two (2) cicada CIS8201 phys for emac 2 and 3 (supports 10/100/1000).
The problem I see is that the extended register set may not be the same across the phy part spectrum. So, one would need to check the OUI and then go to the appropriate register for that part. Which, IMHO, would add quite a bit of code.
Perhaps for my application I should force 1000 Gbps off in the autonegotiation register...
-travis
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Please, please, PLEASE someone tell me there's at least an 'unofficial' standard for this.. like a GMII standard or something similar (802.3ab??)? I'm familiar with the Marvell and Cicada code.. and having to write specific code for each phy, whose documentation may or may not be publically available is.. well, scary...
Phy register 0x0A looks promising.. does anyone know of a gigabit phy that doesn't support that register for 1000bT mode? specifically bits 10/11. (see a Cicada datasheet here: http://www.cicada-semi.com/products/lan/CIS8201/CIS8201_Data_Sheet_Rev_1_2_2...) I don't know about marvell (no docs).
Seems like we should be able to use those bits like the bits in register 0x5 for 10/100 modes... and my gut tells me that register is in a spec somwhere..
john.c
On Thu, 11 Mar 2004, Travis Sawyer wrote:
On Thu, 2004-03-11 at 11:02, Wolfgang Denk wrote:
In message 1079020123.17587.135.camel@pavement.sandburst.com you wrote:
Is anyone working on Gigabit Ethernet PHY support for u-boot?
What _exactly_ are you looking for?
The IBM 440GX supports GbE on the 2nd and 3rd ports, if a gigabit capable phy is in place that is.
The current miiphy_utils (specifically miiphy_speed and miiphy_duplex) read the phy autonegiotation link partner ability register (reg 0x05) to determine current link speed and duplex.
Register 5 is a standard IEEE802.3 register. However, in order to get 'true' status (10/100/1000), extended registers are needed.
In the case of the ocotea board, IBM placed a LXT9762 (6 port phy) for emac 0 and 1 (as they only support 10/100), and two (2) cicada CIS8201 phys for emac 2 and 3 (supports 10/100/1000).
The problem I see is that the extended register set may not be the same across the phy part spectrum. So, one would need to check the OUI and then go to the appropriate register for that part. Which, IMHO, would add quite a bit of code.
Perhaps for my application I should force 1000 Gbps off in the autonegotiation register...
-travis
This SF.Net email is sponsored by: IBM Linux Tutorials Free Linux tutorial presented by Daniel Robbins, President and CEO of GenToo technologies. Learn everything from fundamentals to system administration.http://ads.osdn.com/?ad_id=1470&alloc_id=3638&op=click _______________________________________________ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
John et al:
See inline below... On Thu, 2004-03-11 at 23:59, John Clemens wrote:
and having to write specific code for each phy, whose documentation may or may not be publically available is.. well, scary...
I concur full heartedly!!!
Phy register 0x0A looks promising.. does anyone know of a gigabit phy that doesn't support that register for 1000bT mode? specifically bits 10/11. (see a Cicada datasheet here: http://www.cicada-semi.com/products/lan/CIS8201/CIS8201_Data_Sheet_Rev_1_2_2...) I don't know about marvell (no docs).
The cicada spec says: (paraphrasing here): Shaded registers (0x00 - 0x0f) indicate standard MII registers. All unshaded registers are optional registers, per the IEEE 802.3 standard.
Seems like we should be able to use those bits like the bits in register 0x5 for 10/100 modes... and my gut tells me that register is in a spec somwhere..
The LXT9262/9782 spec says: Base registers (0 through 8) are in accordance with... Additional rgisters (16 through 22) are defined in accordance with IEEE 802.3 specification for adding _*unique chip functions*_
Specifically, registers 9 and 10 (1000Base-T/100Base-T2 Control and status) are not implemented.
The lxt spec does not indicate what reads to these registers would result in, but for giggles I tried it out.
Using my ocotea board (4 ethernet ports, 0 & 1 are 10/100 and 2 & 3 are 10/100/1000). Phy for port 0 is at address 0x01, and phy for port 2 is at 0x10. Since the board has 4 phy chips, the mii info is a bit cluttered. (Note the lxt is a 6 port phy)
Please note, I currently don't have any hacks in for GbE support so mii info incorrectly states that phy 0x10 is at 100Mb/s.
=> mii info PHY 0x00: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x01: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 100baseT, FDX PHY 0x02: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 10baseT, HDX PHY 0x03: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 10baseT, HDX PHY 0x04: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 10baseT, HDX PHY 0x05: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 10baseT, HDX PHY 0x06: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 10baseT, HDX PHY 0x10: OUI = 0x03F1, Model = 0x01, Rev = 0x03, 100baseT, FDX PHY 0x18: OUI = 0x03F1, Model = 0x01, Rev = 0x03, 10baseT, HDX => mii read 1 0 3100 => mii read 1 1 7829 => mii read 1 9 FFFF => mii read 1 a FFFF => mii read 10 0 1140 => mii read 10 1 796D => mii read 10 9 0300 => mii read 10 a 7C00 =>
So, the LXT reports FFFF for the unimplented registers, the cicada properly reports Link partner capable of 1000FDX & 1000HDX in register 0xA
So, if the IEEE802.3 spec. say unimplemented registers return F's we're in business. Anyone have the spec handy???
Is anyone working on Gigabit Ethernet PHY support for u-boot?
-travis
Take a look at the DB64360 source tree in u-boot. That's the one I use as model for our 64360 based board, it (the GigE port) comes up in 1000bt full duplex without a problem...
--- Travis Sawyer tsawyer+u-boot@sandburst.com wrote:
John et al:
See inline below... On Thu, 2004-03-11 at 23:59, John Clemens wrote:
and having to write specific code for each phy, whose documentation may or may not be
publically
available is.. well, scary...
I concur full heartedly!!!
Phy register 0x0A looks promising.. does anyone know of a
gigabit phy that
doesn't support that register for 1000bT mode? specifically
bits 10/11.
(see a Cicada datasheet here:
http://www.cicada-semi.com/products/lan/CIS8201/CIS8201_Data_Sheet_Rev_1_2_2...)
I don't know about marvell (no docs).
The cicada spec says: (paraphrasing here): Shaded registers (0x00 - 0x0f) indicate standard MII registers. All unshaded registers are optional registers, per the IEEE 802.3 standard.
Seems like we should be able to use those bits like the bits
in register
0x5 for 10/100 modes... and my gut tells me that register is
in a spec
somwhere..
The LXT9262/9782 spec says: Base registers (0 through 8) are in accordance with... Additional rgisters (16 through 22) are defined in accordance with IEEE 802.3 specification for adding _*unique chip functions*_
Specifically, registers 9 and 10 (1000Base-T/100Base-T2 Control and status) are not implemented.
The lxt spec does not indicate what reads to these registers would result in, but for giggles I tried it out.
Using my ocotea board (4 ethernet ports, 0 & 1 are 10/100 and 2 & 3 are 10/100/1000). Phy for port 0 is at address 0x01, and phy for port 2 is at 0x10. Since the board has 4 phy chips, the mii info is a bit cluttered. (Note the lxt is a 6 port phy)
Please note, I currently don't have any hacks in for GbE support so mii info incorrectly states that phy 0x10 is at 100Mb/s.
=> mii info PHY 0x00: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX PHY 0x01: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 100baseT, FDX PHY 0x02: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 10baseT, HDX PHY 0x03: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 10baseT, HDX PHY 0x04: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 10baseT, HDX PHY 0x05: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 10baseT, HDX PHY 0x06: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 10baseT, HDX PHY 0x10: OUI = 0x03F1, Model = 0x01, Rev = 0x03, 100baseT, FDX PHY 0x18: OUI = 0x03F1, Model = 0x01, Rev = 0x03, 10baseT, HDX => mii read 1 0 3100 => mii read 1 1 7829 => mii read 1 9 FFFF => mii read 1 a FFFF => mii read 10 0 1140 => mii read 10 1 796D => mii read 10 9 0300 => mii read 10 a 7C00 =>
So, the LXT reports FFFF for the unimplented registers, the cicada properly reports Link partner capable of 1000FDX & 1000HDX in register 0xA
So, if the IEEE802.3 spec. say unimplemented registers return F's we're in business. Anyone have the spec handy???
Is anyone working on Gigabit Ethernet PHY support for
u-boot?
-travis
This SF.Net email is sponsored by: IBM Linux Tutorials Free Linux tutorial presented by Daniel Robbins, President and CEO of GenToo technologies. Learn everything from fundamentals to system
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Hmm... well, i happen to know of another gigabit phy that i dare not speak it's name, that happens to implement registers 0x9 and 0xA the same way as the cicada phy does... so that's two for and one against :) hardly a large enough sample size.... It's highly annoyint the LXT ones don't. :(
looking at tigon3.h, it looks like the BCM54xx series at least supports register 0x9... since 0x9 and 0xa seem to be tightly coupled, i can only guess that it also supports register 0xa.
Can someone with a bcm54xx verify?
The tsec.h file in cpu/mpc85xx/ which contains the Marvell 88E1011 support also indicates that is supports register 0x9, so using the same (quite possibly flawed) logic as above the marvell one may support the 0x9 and 0xa pair as well.
I'm just trying to figure out if the LXT is an exception, not the norm...
john.c
On Fri, 12 Mar 2004, Travis Sawyer wrote:
Phy register 0x0A looks promising.. does anyone know of a gigabit phy that doesn't support that register for 1000bT mode? specifically bits 10/11. (see a Cicada datasheet here: http://www.cicada-semi.com/products/lan/CIS8201/CIS8201_Data_Sheet_Rev_1_2_2...) I don't know about marvell (no docs).
The cicada spec says: (paraphrasing here): Shaded registers (0x00 - 0x0f) indicate standard MII registers. All unshaded registers are optional registers, per the IEEE 802.3 standard.
Seems like we should be able to use those bits like the bits in register 0x5 for 10/100 modes... and my gut tells me that register is in a spec somwhere..
The LXT9262/9782 spec says: Base registers (0 through 8) are in accordance with... Additional rgisters (16 through 22) are defined in accordance with IEEE 802.3 specification for adding _*unique chip functions*_
Specifically, registers 9 and 10 (1000Base-T/100Base-T2 Control and status) are not implemented.
John:
On Fri, 2004-03-12 at 13:27, John Clemens wrote:
Hmm... well, i happen to know of another gigabit phy that i dare not speak it's name, that happens to implement registers 0x9 and 0xA the same way as the cicada phy does... so that's two for and one against :) hardly a large enough sample size.... It's highly annoyint the LXT ones don't. :(
The LXT phy I mentioned early is 10/100, so not having a 1000B-T config/status pair would make sense...
looking at tigon3.h, it looks like the BCM54xx series at least supports register 0x9... since 0x9 and 0xa seem to be tightly coupled, i can only guess that it also supports register 0xa.
Can someone with a bcm54xx verify?
Verified ;) (that is they have 1000B-T config/status regs)
I'm just trying to figure out if the LXT is an exception, not the norm...
An exception only that it is a 10/100 only (the LXT9762 is the part in question) (see above)
travis
On Fri, 12 Mar 2004, Travis Sawyer wrote:
The LXT phy I mentioned early is 10/100, so not having a 1000B-T config/status pair would make sense...
Ahh... missed that minor but important fact :) very cool.. thanks agian.
john.c
Travis Sawyer wrote:
Is anyone working on Gigabit Ethernet PHY support for u-boot?
It works on the Morotola 85xx with the Marvell M88E1011, both copper and fiber. There are some questionable "workarounds" for reset problems, with the magic bits differenent depending upon who you talk to or documentation you read.
-- Dan
In message 1079019436.17587.132.camel@pavement.sandburst.com you wrote:
- Travis Sawyer 11Mar2004
Fix ocotea board early init interrupt setup.
Thanks, added.
Best regards,
Wolfgang Denk
participants (6)
-
Carl Riechers -
Dan Malek -
Frank -
John Clemens -
Travis Sawyer -
Wolfgang Denk