in the cpu/mips/start.S if the cache is on, where need to add the cache flush code? only flush dcache? or both dcacahe and icache?

i add cache flush after the copy loop, i wonder whether i need to add cache flush after the GOT table relocate and bss clean

as follow is the relocate_code in cpu/mips/start.S, i add cache flush one place,is that right?

best regards zhuzhenhua

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ relocate_code: move sp, a0 /* Set new stack pointer */

li t0, CFG_MONITOR_BASE la t3, in_ram lw t2, -12(t3) /* t2 <-- uboot_end_data */ move t1, a2

/* * Fix GOT pointer: * * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address */ move t6, gp sub gp, CFG_MONITOR_BASE add gp, a2 /* gp now adjusted */ sub t6, gp, t6 /* t6 <-- relocation offset */

/* * t0 = source address * t1 = target address * t2 = source end address */ /* On the purple board we copy the code earlier in a special way * in order to solve flash problems */ #ifndef CONFIG_PURPLE 1: lw t3, 0(t0) sw t3, 0(t1) addu t0, 4 ble t0, t2, 1b addu t1, 4 /* delay slot */ #endif

/* If caches were enabled, we would have to flush them here. */

/*~~~~~~~~~~~~~~~~ as follow is my cache flush code */

#ifdef CONFIG_MYBOARD li t1, (16*1024) #cache total size li t2, 16 #cache line size li t3, 0x80000000 addu t4, t1, t3

cacheloop1: cache 0, 0(t3) /* Index_Invalidate_I */ cache 1, 0(t3) /* Index_Writeback_Inv_D */ addu t3, t2 bne t3, t4, cacheloop1 nop #endif

/* Jump to where we've relocated ourselves. */ addi t0, a2, in_ram - _start j t0 nop

.word uboot_end_data .word uboot_end .word num_got_entries

in_ram: /* Now we want to update GOT. */ lw t3, -4(t0) /* t3 <-- num_got_entries */ addi t4, gp, 8 /* Skipping first two entries. */ li t2, 2 1: lw t1, 0(t4) beqz t1, 2f add t1, t6 sw t1, 0(t4) 2: addi t2, 1 blt t2, t3, 1b addi t4, 4 /* delay slot */

/* Clear BSS. */

lw t1, -12(t0) /* t1 <-- uboot_end_data */ lw t2, -8(t0) /* t2 <-- uboot_end */ add t1, t6 /* adjust pointers */ add t2, t6

sub t1, 4 1: addi t1, 4 bltl t1, t2, 1b sw zero, 0(t1) /* delay slot */ #if 0 nop sync nop #endif move a0, a1 la t9, board_init_r j t9 move a1, a2 /* delay slot */

.end relocate_code

/* Exception handlers. */ romReserved: b romReserved romExcHandle: b romExcHandle