[PATCH 1/6] sh: Remove MigoR board
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/sh/Kconfig | 5 - board/renesas/MigoR/Kconfig | 12 -- board/renesas/MigoR/MAINTAINERS | 6 - board/renesas/MigoR/Makefile | 13 -- board/renesas/MigoR/lowlevel_init.S | 193 ---------------------------- board/renesas/MigoR/migo_r.c | 43 ------- configs/MigoR_defconfig | 34 ----- include/configs/MigoR.h | 82 ------------ 8 files changed, 388 deletions(-) delete mode 100644 board/renesas/MigoR/Kconfig delete mode 100644 board/renesas/MigoR/MAINTAINERS delete mode 100644 board/renesas/MigoR/Makefile delete mode 100644 board/renesas/MigoR/lowlevel_init.S delete mode 100644 board/renesas/MigoR/migo_r.c delete mode 100644 configs/MigoR_defconfig delete mode 100644 include/configs/MigoR.h
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 91002a9be08f..2cd153fbac0d 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -21,10 +21,6 @@ choice prompt "Target select" optional
-config TARGET_MIGOR - bool "Migo-R" - select CPU_SH4 - config TARGET_R2DPLUS bool "Renesas R2D-PLUS" select CPU_SH4 @@ -59,7 +55,6 @@ config SYS_CPU
source "arch/sh/lib/Kconfig"
-source "board/renesas/MigoR/Kconfig" source "board/renesas/r2dplus/Kconfig" source "board/renesas/r7780mp/Kconfig" source "board/renesas/sh7752evb/Kconfig" diff --git a/board/renesas/MigoR/Kconfig b/board/renesas/MigoR/Kconfig deleted file mode 100644 index 25b170ac0712..000000000000 --- a/board/renesas/MigoR/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MIGOR - -config SYS_BOARD - default "MigoR" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "MigoR" - -endif diff --git a/board/renesas/MigoR/MAINTAINERS b/board/renesas/MigoR/MAINTAINERS deleted file mode 100644 index 21ee5e275483..000000000000 --- a/board/renesas/MigoR/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MIGOR BOARD -#M: - -S: Maintained -F: board/renesas/MigoR/ -F: include/configs/MigoR.h -F: configs/MigoR_defconfig diff --git a/board/renesas/MigoR/Makefile b/board/renesas/MigoR/Makefile deleted file mode 100644 index 944a3bfe2cf6..000000000000 --- a/board/renesas/MigoR/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu iwamatsu@nigauri.org -# -# Copyright (C) 2007 -# Kenati Technologies, Inc. -# -# board/MigoR/Makefile -# - -obj-y := migo_r.o -extra-y += lowlevel_init.o diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S deleted file mode 100644 index 1b494faeb0e2..000000000000 --- a/board/renesas/MigoR/lowlevel_init.S +++ /dev/null @@ -1,193 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007-2008 - * Nobuhiro Iwamatsu iwamatsu@nigauri.org - * - * Copyright (C) 2007 - * Kenati Technologies, Inc. - * - * board/MigoR/lowlevel_init.S - */ - -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - write32 CCR_A, CCR_D ! Address of Cache Control Register - ! Instruction Cache Invalidate - - write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register - ! TI == TLB Invalidate bit - - write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0 - - write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2 - - write16 PFC_PULCR_A, PFC_PULCR_D - - write16 PFC_DRVCR_A, PFC_DRVCR_D - - write16 SBSCR_A, SBSCR_D - - write16 PSCR_A, PSCR_D - - write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register) - ! 0xA507 -> timer_STOP / WDT_CLK = max - - write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register) - ! 0x5A00 -> Clear - - write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register) - ! 0xA504 -> timer_STOP / CLK = 500ms - - write32 DLLFRQ_A, DLLFRQ_D ! 20080115 - ! 20080115 - - write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register - ! 20080115 - - write32 CCR_A, CCR_D_2 ! Address of Cache Control Register - ! ?? - -bsc_init: - write32 CMNCR_A, CMNCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5ABCR_A, CS5ABCR_D - - write32 CS5BBCR_A, CS5BBCR_D - - write32 CS6ABCR_A, CS6ABCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5AWCR_A, CS5AWCR_D - - write32 CS5BWCR_A, CS5BWCR_D - - write32 CS6AWCR_A, CS6AWCR_D - - ! SDRAM initialization - write32 SDCR_A, SDCR_D - - write32 SDWCR_A, SDWCR_D - - write32 SDPCR_A, SDPCR_D - - write32 RTCOR_A, RTCOR_D - - write32 RTCNT_A, RTCNT_D - - write32 RTCSR_A, RTCSR_D - - write32 RFCR_A, RFCR_D - - write8 SDMR3_A, SDMR3_D - - ! BL bit off (init = ON) (?!?) - - stc sr, r0 ! BL bit off(init=ON) - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - mov #0, r0 - - .align 4 - -CCR_A: .long CCR -MMUCR_A: .long MMUCR -MSTPCR0_A: .long MSTPCR0 -MSTPCR2_A: .long MSTPCR2 -PFC_PULCR_A: .long PULCR -PFC_DRVCR_A: .long DRVCR -SBSCR_A: .long SBSCR -PSCR_A: .long PSCR -RWTCSR_A: .long RWTCSR -RWTCNT_A: .long RWTCNT -FRQCR_A: .long FRQCR -PLLCR_A: .long PLLCR -DLLFRQ_A: .long DLLFRQ - -CCR_D: .long 0x00000800 -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff -PFC_PULCR_D: .long 0x6000 -PFC_DRVCR_D: .long 0x0464 -FRQCR_D: .long 0x07033639 -PLLCR_D: .long 0x00005000 -DLLFRQ_D: .long 0x000004F6 - -CMNCR_A: .long CMNCR -CMNCR_D: .long 0x0000001B -CS0BCR_A: .long CS0BCR -CS0BCR_D: .long 0x24920400 -CS4BCR_A: .long CS4BCR -CS4BCR_D: .long 0x00003400 -CS5ABCR_A: .long CS5ABCR -CS5ABCR_D: .long 0x24920400 -CS5BBCR_A: .long CS5BBCR -CS5BBCR_D: .long 0x24920400 -CS6ABCR_A: .long CS6ABCR -CS6ABCR_D: .long 0x24920400 - -CS0WCR_A: .long CS0WCR -CS0WCR_D: .long 0x00000380 -CS4WCR_A: .long CS4WCR -CS4WCR_D: .long 0x00110080 -CS5AWCR_A: .long CS5AWCR -CS5AWCR_D: .long 0x00000300 -CS5BWCR_A: .long CS5BWCR -CS5BWCR_D: .long 0x00000300 -CS6AWCR_A: .long CS6AWCR -CS6AWCR_D: .long 0x00000300 - -SDCR_A: .long SBSC_SDCR -SDCR_D: .long 0x80160809 -SDWCR_A: .long SBSC_SDWCR -SDWCR_D: .long 0x0014450C -SDPCR_A: .long SBSC_SDPCR -SDPCR_D: .long 0x00000087 -RTCOR_A: .long SBSC_RTCOR -RTCNT_A: .long SBSC_RTCNT -RTCNT_D: .long 0xA55A0012 -RTCOR_D: .long 0xA55A001C -RTCSR_A: .long SBSC_RTCSR -RFCR_A: .long SBSC_RFCR -RFCR_D: .long 0xA55A0221 -RTCSR_D: .long 0xA55A009a -SDMR3_A: .long 0xFE581180 -SDMR3_D: .long 0x0 - -SR_MASK_D: .long 0xEFFFFF0F - - .align 2 - -SBSCR_D: .word 0x0044 -PSCR_D: .word 0x0000 -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA504 -RWTCNT_D: .word 0x5A00 diff --git a/board/renesas/MigoR/migo_r.c b/board/renesas/MigoR/migo_r.c deleted file mode 100644 index f2f4c657534f..000000000000 --- a/board/renesas/MigoR/migo_r.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu iwamatsu@nigauri.org - * - * Copyright (C) 2007 - * Kenati Technologies, Inc. - * - * board/MigoR/migo_r.c - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -int checkboard(void) -{ - puts("BOARD: Renesas MigoR\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -void led_set_state (unsigned short value) -{ -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/configs/MigoR_defconfig b/configs/MigoR_defconfig deleted file mode 100644 index f29f1ec1f332..000000000000 --- a/configs/MigoR_defconfig +++ /dev/null @@ -1,34 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x8FFC0000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_TARGET_MIGOR=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC0,115200 root=1f01" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_RUN is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -# CONFIG_CMD_SLEEP is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xA0020000 -CONFIG_VERSION_VARIABLE=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SCIF_CONSOLE=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h deleted file mode 100644 index 026ffbeb6c7b..000000000000 --- a/include/configs/MigoR.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Renesas Solutions Migo-R board - * - * Copyright (C) 2007 Nobuhiro Iwamatsu iwamatsu@nigauri.org - */ - -#ifndef __MIGO_R_H -#define __MIGO_R_H - -#define CONFIG_CPU_SH7722 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* SMC9111 */ -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE (0xB0000000) - -/* MEMORY */ -#define MIGO_R_SDRAM_BASE (0x8C000000) -#define MIGO_R_FLASH_BASE_1 (0xA0000000) -#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ - -/* SCIF */ -#define CONFIG_CONS_SCIF0 1 - -/* Enable alternate, more extensive, memory test */ -/* Scratch address used by the alternate memory test */ - -/* Enable temporary baudrate change while serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE) -/* maybe more, but if so u-boot doesn't know about it... */ -#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) -/* default load address for scripts ?!? */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) - -/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ -#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1) -/* Monitor size */ -#define CONFIG_SYS_MONITOR_LEN (128 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* FLASH */ -#undef CONFIG_SYS_FLASH_QUIET_TEST -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -/* Physical start address of Flash memory */ -#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1) -/* Max number of sectors on each Flash chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } - -/* Timeout for Flash erase operations (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) -/* Timeout for Flash write operations (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) -/* Timeout for Flash set sector lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) -/* Timeout for Flash clear lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) - -/* Use hardware flash sectors protection instead of U-Boot software protection */ -#undef CONFIG_SYS_DIRECT_FLASH_TFTP - -/* ENV setting */ -/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 33333333 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -#endif /* __MIGO_R_H */
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
Patch-cc: Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com Patch-cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Signed-off-by: Tom Rini trini@konsulko.com --- arch/sh/Kconfig | 5 - board/renesas/r7780mp/Kconfig | 12 - board/renesas/r7780mp/MAINTAINERS | 7 - board/renesas/r7780mp/Makefile | 9 - board/renesas/r7780mp/lowlevel_init.S | 356 -------------------------- board/renesas/r7780mp/r7780mp.c | 64 ----- board/renesas/r7780mp/r7780mp.h | 40 --- configs/r7780mp_defconfig | 40 --- doc/arch/sh.rst | 18 -- drivers/net/Makefile | 1 - drivers/net/ax88796.c | 144 ----------- drivers/net/ax88796.h | 66 ----- include/configs/r7780mp.h | 108 -------- 13 files changed, 870 deletions(-) delete mode 100644 board/renesas/r7780mp/Kconfig delete mode 100644 board/renesas/r7780mp/MAINTAINERS delete mode 100644 board/renesas/r7780mp/Makefile delete mode 100644 board/renesas/r7780mp/lowlevel_init.S delete mode 100644 board/renesas/r7780mp/r7780mp.c delete mode 100644 board/renesas/r7780mp/r7780mp.h delete mode 100644 configs/r7780mp_defconfig delete mode 100644 drivers/net/ax88796.c delete mode 100644 drivers/net/ax88796.h delete mode 100644 include/configs/r7780mp.h
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 2cd153fbac0d..2d7525e61db4 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -25,10 +25,6 @@ config TARGET_R2DPLUS bool "Renesas R2D-PLUS" select CPU_SH4
-config TARGET_R7780MP - bool "R7780MP board" - select CPU_SH4A - config TARGET_SH7752EVB bool "SH7752EVB" select CPU_SH4A @@ -56,7 +52,6 @@ config SYS_CPU source "arch/sh/lib/Kconfig"
source "board/renesas/r2dplus/Kconfig" -source "board/renesas/r7780mp/Kconfig" source "board/renesas/sh7752evb/Kconfig" source "board/renesas/sh7753evb/Kconfig" source "board/renesas/sh7757lcr/Kconfig" diff --git a/board/renesas/r7780mp/Kconfig b/board/renesas/r7780mp/Kconfig deleted file mode 100644 index 050cc4cc0f6d..000000000000 --- a/board/renesas/r7780mp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_R7780MP - -config SYS_BOARD - default "r7780mp" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "r7780mp" - -endif diff --git a/board/renesas/r7780mp/MAINTAINERS b/board/renesas/r7780mp/MAINTAINERS deleted file mode 100644 index 56ec21fd32f8..000000000000 --- a/board/renesas/r7780mp/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -R7780MP BOARD -M: Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com -M: Nobuhiro Iwamatsu iwamatsu@nigauri.org -S: Maintained -F: board/renesas/r7780mp/ -F: include/configs/r7780mp.h -F: configs/r7780mp_defconfig diff --git a/board/renesas/r7780mp/Makefile b/board/renesas/r7780mp/Makefile deleted file mode 100644 index 0a387db35d29..000000000000 --- a/board/renesas/r7780mp/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007,2008 Nobuhiro Iwamatsu -# -# board/r7780mp/Makefile -# - -obj-y := r7780mp.o -extra-y += lowlevel_init.o diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S deleted file mode 100644 index 7be1a1bf0703..000000000000 --- a/board/renesas/r7780mp/lowlevel_init.S +++ /dev/null @@ -1,356 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu - * - * u-boot/board/r7780mp/lowlevel_init.S - */ - -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - write32 CCR_A, CCR_D /* Address of Cache Control Register */ - /* Instruction Cache Invalidate */ - - write32 FRQCR_A, FRQCR_D /* Frequency control register */ - - /* pin_multi_setting */ - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1 - - write32 BBG_PMSR1_A, BBG_PMSR1_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2 - - write32 BBG_PMSR2_A, BBG_PMSR2_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3 - - write32 BBG_PMSR3_A, BBG_PMSR3_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4 - - write32 BBG_PMSR4_A, BBG_PMSR4_D - - write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG - - write32 BBG_PMSRG_A, BBG_PMSRG_D - - /* cpg_setting */ - write32 FRQCR_A, FRQCR_D - - write32 DLLCSR_A, DLLCSR_D - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* wait 200us */ - mov.l REPEAT0_R3, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - /* bsc_setting */ - write32 MMSELR_A, MMSELR_D - - write32 BCR_A, BCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS1BCR_A, CS1BCR_D - - write32 CS2BCR_A, CS2BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5BCR_A, CS5BCR_D - - write32 CS6BCR_A, CS6BCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS1WCR_A, CS1WCR_D - - write32 CS2WCR_A, CS2WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5WCR_A, CS5WCR_D - - write32 CS6WCR_A, CS6WCR_D - - write32 CS5PCR_A, CS5PCR_D - - write32 CS6PCR_A, CS6PCR_D - - /* ddr_setting */ - /* wait 200us */ - mov.l REPEAT0_R3, r3 - mov #0, r2 -repeat1: - add #1, r2 - cmp/hs r3, r2 - bf repeat1 - nop - - mov.l MIM_U_A, r0 - mov.l MIM_U_D, r1 - synco - mov.l r1, @r0 - synco - - mov.l MIM_L_A, r0 - mov.l MIM_L_D0, r1 - synco - mov.l r1, @r0 - synco - - mov.l STR_L_A, r0 - mov.l STR_L_D, r1 - synco - mov.l r1, @r0 - synco - - mov.l SDR_L_A, r0 - mov.l SDR_L_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D0, r1 - synco - mov.l r1, @r0 - synco - - mov.l SCR_L_A, r0 - mov.l SCR_L_D1, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l EMRS_A, r0 - mov.l EMRS_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l MRS1_A, r0 - mov.l MRS1_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D2, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D3, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D4, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l MRS2_A, r0 - mov.l MRS2_D, r1 - synco - mov.l r1, @r0 - synco - - nop - nop - nop - - mov.l SCR_L_A, r0 - mov.l SCR_L_D5, r1 - synco - mov.l r1, @r0 - synco - - /* wait 200us */ - mov.l REPEAT0_R1, r3 - mov #0, r2 -repeat2: - add #1, r2 - cmp/hs r3, r2 - bf repeat2 - - synco - - mov.l MIM_L_A, r0 - mov.l MIM_L_D1, r1 - synco - mov.l r1, @r0 - synco - - rts - nop - .align 4 - -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA507 -RWTCNT_D: .word 0x5A00 - .align 2 - -BBG_PMMR_A: .long 0xFF800010 -BBG_PMSR1_A: .long 0xFF800014 -BBG_PMSR2_A: .long 0xFF800018 -BBG_PMSR3_A: .long 0xFF80001C -BBG_PMSR4_A: .long 0xFF800020 -BBG_PMSRG_A: .long 0xFF800024 - -BBG_PMMR_D_PMSR1: .long 0xffffbffd -BBG_PMSR1_D: .long 0x00004002 -BBG_PMMR_D_PMSR2: .long 0xfc21a7ff -BBG_PMSR2_D: .long 0x03de5800 -BBG_PMMR_D_PMSR3: .long 0xfffffff8 -BBG_PMSR3_D: .long 0x00000007 -BBG_PMMR_D_PMSR4: .long 0xdffdfff9 -BBG_PMSR4_D: .long 0x20020006 -BBG_PMMR_D_PMSRG: .long 0xffffffff -BBG_PMSRG_D: .long 0x00000000 - -FRQCR_A: .long FRQCR -DLLCSR_A: .long 0xffc40010 -FRQCR_D: .long 0x40233035 -DLLCSR_D: .long 0x00000000 - -/* for DDR-SDRAM */ -MIM_U_A: .long MIM_1 -MIM_L_A: .long MIM_2 -SCR_U_A: .long SCR_1 -SCR_L_A: .long SCR_2 -STR_U_A: .long STR_1 -STR_L_A: .long STR_2 -SDR_U_A: .long SDR_1 -SDR_L_A: .long SDR_2 - -EMRS_A: .long 0xFEC02000 -MRS1_A: .long 0xFEC00B08 -MRS2_A: .long 0xFEC00308 - -MIM_U_D: .long 0x00004000 -MIM_L_D0: .long 0x03e80009 -MIM_L_D1: .long 0x03e80209 -SCR_L_D0: .long 0x3 -SCR_L_D1: .long 0x2 -SCR_L_D2: .long 0x2 -SCR_L_D3: .long 0x4 -SCR_L_D4: .long 0x4 -SCR_L_D5: .long 0x0 -STR_L_D: .long 0x000f0000 -SDR_L_D: .long 0x00000400 -EMRS_D: .long 0x0 -MRS1_D: .long 0x0 -MRS2_D: .long 0x0 - -/* Cache Controller */ -CCR_A: .long CCR -MMUCR_A: .long MMUCR -RWTCNT_A: .long WTCNT - -CCR_D: .long 0x0000090b -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff - -/* local Bus State Controller */ -MMSELR_A: .long MMSELR -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS1BCR_A: .long CS1BCR -CS2BCR_A: .long CS2BCR -CS4BCR_A: .long CS4BCR -CS5BCR_A: .long CS5BCR -CS6BCR_A: .long CS6BCR -CS0WCR_A: .long CS0WCR -CS1WCR_A: .long CS1WCR -CS2WCR_A: .long CS2WCR -CS4WCR_A: .long CS4WCR -CS5WCR_A: .long CS5WCR -CS6WCR_A: .long CS6WCR -CS5PCR_A: .long CS5PCR -CS6PCR_A: .long CS6PCR - -MMSELR_D: .long 0xA5A50003 -BCR_D: .long 0x00000000 -CS0BCR_D: .long 0x77777770 -CS1BCR_D: .long 0x77777670 -CS2BCR_D: .long 0x77777770 -CS4BCR_D: .long 0x77777770 -CS5BCR_D: .long 0x77777670 -CS6BCR_D: .long 0x77777770 -CS0WCR_D: .long 0x00020006 -CS1WCR_D: .long 0x00232304 -CS2WCR_D: .long 0x7777770F -CS4WCR_D: .long 0x7777770F -CS5WCR_D: .long 0x00101006 -CS6WCR_D: .long 0x77777703 -CS5PCR_D: .long 0x77000000 -CS6PCR_D: .long 0x77000000 - -REPEAT0_R3: .long 0x00002000 -REPEAT0_R1: .long 0x0000200 diff --git a/board/renesas/r7780mp/r7780mp.c b/board/renesas/r7780mp/r7780mp.c deleted file mode 100644 index 422381ca780b..000000000000 --- a/board/renesas/r7780mp/r7780mp.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu iwamatsu@nigauri.org - * Copyright (C) 2008 Yusuke Goda goda.yusuke@renesas.com - */ - -#include <common.h> -#include <ide.h> -#include <init.h> -#include <net.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <netdev.h> -#include "r7780mp.h" - -int checkboard(void) -{ -#if defined(CONFIG_R7780MP) - puts("BOARD: Renesas Solutions R7780MP\n"); -#else - puts("BOARD: Renesas Solutions R7780RP\n"); -#endif - return 0; -} - -int board_init(void) -{ - /* SCIF Enable */ - writew(0x0, PHCR); - - return 0; -} - -void led_set_state(unsigned short value) -{ - -} - -void ide_set_reset(int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - if (idereset) { - writew(0x432, FPGA_CFCTL); -#if defined(CONFIG_R7780MP) - writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); -#else - writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); -#endif - writew(0x01, FPGA_CFCDINTCLR); - } -} - -static struct pci_controller hose; -void pci_init_board(void) -{ - pci_sh7780_init(&hose); -} - -int board_eth_init(struct bd_info *bis) -{ - /* return >= 0 if a chip is found, the board's AX88796L is n2k-based */ - return ne2k_register() + pci_eth_init(bis); -} diff --git a/board/renesas/r7780mp/r7780mp.h b/board/renesas/r7780mp/r7780mp.h deleted file mode 100644 index cce66bc4d2a9..000000000000 --- a/board/renesas/r7780mp/r7780mp.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007 Nobuhiro Iwamatsu - * Copyright (C) 2008 Yusuke Goda goda.yusuke@renesas.com - * - * u-boot/board/r7780mp/r7780mp.h - */ - -#ifndef _BOARD_R7780MP_R7780MP_H_ -#define _BOARD_R7780MP_R7780MP_H_ - -/* R7780MP's FPGA register map */ -#define FPGA_BASE 0xa4000000 -#define FPGA_IRLMSK (FPGA_BASE + 0x00) -#define FPGA_IRLMON (FPGA_BASE + 0x02) -#define FPGA_IRLPRI1 (FPGA_BASE + 0x04) -#define FPGA_IRLPRI2 (FPGA_BASE + 0x06) -#define FPGA_IRLPRI3 (FPGA_BASE + 0x08) -#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) -#define FPGA_RSTCTL (FPGA_BASE + 0x0C) -#define FPGA_PCIBD (FPGA_BASE + 0x0E) -#define FPGA_PCICD (FPGA_BASE + 0x10) -#define FPGA_EXTGIO (FPGA_BASE + 0x16) -#define FPGA_IVDRMON (FPGA_BASE + 0x18) -#define FPGA_IVDRCR (FPGA_BASE + 0x1A) -#define FPGA_OBLED (FPGA_BASE + 0x1C) -#define FPGA_OBSW (FPGA_BASE + 0x1E) -#define FPGA_TPCTL (FPGA_BASE + 0x100) -#define FPGA_TPDCKCTL (FPGA_BASE + 0x102) -#define FPGA_TPCLR (FPGA_BASE + 0x104) -#define FPGA_TPXPOS (FPGA_BASE + 0x106) -#define FPGA_TPYPOS (FPGA_BASE + 0x108) -#define FPGA_DBSW (FPGA_BASE + 0x200) -#define FPGA_VERSION (FPGA_BASE + 0x700) -#define FPGA_CFCTL (FPGA_BASE + 0x300) -#define FPGA_CFPOW (FPGA_BASE + 0x302) -#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) -#define FPGA_PMR (FPGA_BASE + 0x900) - -#endif /* _BOARD_R7780RP_R7780RP_H_ */ diff --git a/configs/r7780mp_defconfig b/configs/r7780mp_defconfig deleted file mode 100644 index ed89aa9dcd63..000000000000 --- a/configs/r7780mp_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x0FFC0000 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_TARGET_R7780MP=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC0,115200" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_RUN is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_IDE=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_PCI=y -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_EXT2=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xA0040000 -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PCI=y -CONFIG_SCIF_CONSOLE=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/doc/arch/sh.rst b/doc/arch/sh.rst index 3a3f92dd3e20..3e3759d68b20 100644 --- a/doc/arch/sh.rst +++ b/doc/arch/sh.rst @@ -26,10 +26,6 @@ Renesas SH7722 ^^^^^^^^^^^^^^ This CPU has the SH4AL-DSP core.
-Renesas SH7780 -^^^^^^^^^^^^^^ -This CPU has the SH4A core. - Supported Boards ----------------
@@ -67,20 +63,6 @@ Support devices are: - NOR Flash - Marubun PCMCIA
-Renesas R7780MP -^^^^^^^^^^^^^^^ -Board specific code is in board/r7780mp -To use this board, type "make r7780mp_config". -Support devices are: - - - SCIF - - DDR-SDRAM - - NOR Flash - - Compact Flash - - ASIX ethernet - - SH7780 PCI bridge - - RTL8110 ethernet - In SuperH, S-record and binary of made u-boot work on the memory. When u-boot is written in the flash, it is necessary to change the address by using 'objcopy':: diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 6712b74a897b..a19511aaa7ba 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -53,7 +53,6 @@ obj-$(CONFIG_MVNETA) += mvneta.o obj-$(CONFIG_MVPP2) += mvpp2.o obj-$(CONFIG_NATSEMI) += natsemi.o obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o -obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o obj-$(CONFIG_NETCONSOLE) += netconsole.o obj-$(CONFIG_NS8382X) += ns8382x.o obj-$(CONFIG_PCH_GBE) += pch_gbe.o diff --git a/drivers/net/ax88796.c b/drivers/net/ax88796.c deleted file mode 100644 index d161f0e09c36..000000000000 --- a/drivers/net/ax88796.c +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (c) 2007 Nobuhiro Iwamatsu iwamatsu@nigauri.org - */ -#include <common.h> -#include <linux/delay.h> -#include "ax88796.h" - -/* - * Set 1 bit data - */ -static void ax88796_bitset(u32 bit) -{ - /* DATA1 */ - if( bit ) - EEDI_HIGH; - else - EEDI_LOW; - - EECLK_LOW; - udelay(1000); - EECLK_HIGH; - udelay(1000); - EEDI_LOW; -} - -/* - * Get 1 bit data - */ -static u8 ax88796_bitget(void) -{ - u8 bit; - - EECLK_LOW; - udelay(1000); - /* DATA */ - bit = EEDO; - EECLK_HIGH; - udelay(1000); - - return bit; -} - -/* - * Send COMMAND to EEPROM - */ -static void ax88796_eep_cmd(u8 cmd) -{ - ax88796_bitset(BIT_DUMMY); - switch(cmd){ - case MAC_EEP_READ: - ax88796_bitset(1); - ax88796_bitset(1); - ax88796_bitset(0); - break; - - case MAC_EEP_WRITE: - ax88796_bitset(1); - ax88796_bitset(0); - ax88796_bitset(1); - break; - - case MAC_EEP_ERACE: - ax88796_bitset(1); - ax88796_bitset(1); - ax88796_bitset(1); - break; - - case MAC_EEP_EWEN: - ax88796_bitset(1); - ax88796_bitset(0); - ax88796_bitset(0); - break; - - case MAC_EEP_EWDS: - ax88796_bitset(1); - ax88796_bitset(0); - ax88796_bitset(0); - break; - default: - break; - } -} - -static void ax88796_eep_setaddr(u16 addr) -{ - int i ; - - for( i = 7 ; i >= 0 ; i-- ) - ax88796_bitset(addr & (1 << i)); -} - -/* - * Get data from EEPROM - */ -static u16 ax88796_eep_getdata(void) -{ - ushort data = 0; - int i; - - ax88796_bitget(); /* DUMMY */ - for( i = 0 ; i < 16 ; i++ ){ - data <<= 1; - data |= ax88796_bitget(); - } - return data; -} - -static void ax88796_mac_read(u8 *buff) -{ - int i ; - u16 data; - u16 addr = 0; - - for( i = 0 ; i < 3; i++ ) - { - EECS_HIGH; - EEDI_LOW; - udelay(1000); - /* READ COMMAND */ - ax88796_eep_cmd(MAC_EEP_READ); - /* ADDRESS */ - ax88796_eep_setaddr(addr++); - /* GET DATA */ - data = ax88796_eep_getdata(); - *buff++ = (uchar)(data & 0xff); - *buff++ = (uchar)((data >> 8) & 0xff); - EECLK_LOW; - EEDI_LOW; - EECS_LOW; - } -} - -int get_prom(u8* mac_addr, u8* base_addr) -{ - u8 prom[32]; - int i; - - ax88796_mac_read(prom); - for (i = 0; i < 6; i++){ - mac_addr[i] = prom[i]; - } - return 1; -} diff --git a/drivers/net/ax88796.h b/drivers/net/ax88796.h deleted file mode 100644 index 510606610662..000000000000 --- a/drivers/net/ax88796.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * AX88796L(NE2000) support - * - * (c) 2007 Nobuhiro Iwamatsu iwamatsu@nigauri.org - */ - -#ifndef __DRIVERS_AX88796L_H__ -#define __DRIVERS_AX88796L_H__ - -#define DP_DATA (0x10 << 1) -#define START_PG 0x40 /* First page of TX buffer */ -#define START_PG2 0x48 -#define STOP_PG 0x80 /* Last page +1 of RX ring */ -#define TX_PAGES 12 -#define RX_START (START_PG+TX_PAGES) -#define RX_END STOP_PG - -#define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE -#define AX88796L_BYTE_ACCESS 0x00001000 -#define AX88796L_OFFSET 0x00000400 -#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ - AX88796L_BYTE_ACCESS + AX88796L_OFFSET -#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) -#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) - -#define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR)) -#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) - -#define EECS_HIGH (AX88796L_MEMR |= 0x10) -#define EECS_LOW (AX88796L_MEMR &= 0xef) -#define EECLK_HIGH (AX88796L_MEMR |= 0x80) -#define EECLK_LOW (AX88796L_MEMR &= 0x7f) -#define EEDI_HIGH (AX88796L_MEMR |= 0x20) -#define EEDI_LOW (AX88796L_MEMR &= 0xdf) -#define EEDO ((AX88796L_MEMR & 0x40)>>6) - -#define PAGE0_SET (AX88796L_CR &= 0x3f) -#define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40) - -#define BIT_DUMMY 0 -#define MAC_EEP_READ 1 -#define MAC_EEP_WRITE 2 -#define MAC_EEP_ERACE 3 -#define MAC_EEP_EWEN 4 -#define MAC_EEP_EWDS 5 - -/* R7780MP Specific code */ -#if defined(CONFIG_R7780MP) -#define ISA_OFFSET 0x1400 -#define DP_IN(_b_, _o_, _d_) (_d_) = \ - *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET)) -#define DP_OUT(_b_, _o_, _d_) \ - *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_) -#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) -#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) -#else -/* Please change for your target boards */ -#define ISA_OFFSET 0x0000 -#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) -#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) -#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) -#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) -#endif - -#endif /* __DRIVERS_AX88796L_H__ */ diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h deleted file mode 100644 index 0455b1c2eca6..000000000000 --- a/include/configs/r7780mp.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Renesas R7780MP board - * - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu iwamatsu@nigauri.org - * Copyright (C) 2008 Yusuke Goda goda.yusuke@renesas.com - */ - -#ifndef __R7780RP_H -#define __R7780RP_H - -#define CONFIG_CPU_SH7780 1 -#define CONFIG_R7780MP 1 -#define CONFIG_SYS_R7780MP_OLD_FLASH 1 -#define __LITTLE_ENDIAN__ 1 - -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_CONS_SCIF0 1 - -#define CONFIG_SYS_SDRAM_BASE (0x08000000) -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 - -/* Flash board support */ -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#ifdef CONFIG_SYS_R7780MP_OLD_FLASH -/* NOR Flash (S29PL127J60TFI130) */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT -# define CONFIG_SYS_MAX_FLASH_BANKS (2) -# define CONFIG_SYS_MAX_FLASH_SECT 270 -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x100000,\ - CONFIG_SYS_FLASH_BASE + 0x400000,\ - CONFIG_SYS_FLASH_BASE + 0x700000, } -#else /* CONFIG_SYS_R7780MP_OLD_FLASH */ -/* NOR Flash (Spantion S29GL256P) */ -# define CONFIG_SYS_MAX_FLASH_BANKS (1) -# define CONFIG_SYS_MAX_FLASH_SECT 256 -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) -/* Address of u-boot image in Flash */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (1204 * 1024) - -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) -#define CONFIG_SYS_RX_ETH_BUFFER (8) - -#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE -#undef CONFIG_SYS_FLASH_QUIET_TEST -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 33333333 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -/* PCI Controller */ -#if defined(CONFIG_CMD_PCI) -#define CONFIG_SH4_PCI -#define CONFIG_SH7780_PCI -#define CONFIG_SH7780_PCI_LSR 0x07f00001 -#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE -#define CONFIG_PCI_SCAN_SHOW 1 -#define __mem_pci - -#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ - -#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ -#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE -#endif /* CONFIG_CMD_PCI */ - -#if defined(CONFIG_CMD_NET) -/* AX88796L Support(NE2000 base chip) */ -#define CONFIG_DRIVER_AX88796L -#define CONFIG_DRIVER_NE2000_BASE 0xA4100000 -#endif - -/* Compact flash Support */ -#if defined(CONFIG_IDE) -#define CONFIG_IDE_RESET 1 -#define CONFIG_SYS_PIO_MODE 1 -#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 -#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ -#define CONFIG_IDE_SWAP_IO -#endif /* CONFIG_IDE */ - -#endif /* __R7780RP_H */
On Wed, Feb 10, 2021 at 12:51:22PM -0500, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
Patch-cc: Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com Patch-cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/sh/Kconfig | 5 - board/renesas/sh7752evb/Kconfig | 12 - board/renesas/sh7752evb/MAINTAINERS | 6 - board/renesas/sh7752evb/Makefile | 7 - board/renesas/sh7752evb/lowlevel_init.S | 445 ------------------------ board/renesas/sh7752evb/sh7752evb.c | 313 ----------------- board/renesas/sh7752evb/spi-boot.c | 116 ------ configs/sh7752evb_defconfig | 39 --- doc/board/renesas/index.rst | 1 - doc/board/renesas/sh7752evb.rst | 79 ----- include/configs/sh7752evb.h | 65 ---- 11 files changed, 1088 deletions(-) delete mode 100644 board/renesas/sh7752evb/Kconfig delete mode 100644 board/renesas/sh7752evb/MAINTAINERS delete mode 100644 board/renesas/sh7752evb/Makefile delete mode 100644 board/renesas/sh7752evb/lowlevel_init.S delete mode 100644 board/renesas/sh7752evb/sh7752evb.c delete mode 100644 board/renesas/sh7752evb/spi-boot.c delete mode 100644 configs/sh7752evb_defconfig delete mode 100644 doc/board/renesas/sh7752evb.rst delete mode 100644 include/configs/sh7752evb.h
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 2d7525e61db4..8446d9587ed5 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -25,10 +25,6 @@ config TARGET_R2DPLUS bool "Renesas R2D-PLUS" select CPU_SH4
-config TARGET_SH7752EVB - bool "SH7752EVB" - select CPU_SH4A - config TARGET_SH7753EVB bool "SH7753EVB" select CPU_SH4 @@ -52,7 +48,6 @@ config SYS_CPU source "arch/sh/lib/Kconfig"
source "board/renesas/r2dplus/Kconfig" -source "board/renesas/sh7752evb/Kconfig" source "board/renesas/sh7753evb/Kconfig" source "board/renesas/sh7757lcr/Kconfig" source "board/renesas/sh7763rdp/Kconfig" diff --git a/board/renesas/sh7752evb/Kconfig b/board/renesas/sh7752evb/Kconfig deleted file mode 100644 index 7f40888336eb..000000000000 --- a/board/renesas/sh7752evb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SH7752EVB - -config SYS_BOARD - default "sh7752evb" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "sh7752evb" - -endif diff --git a/board/renesas/sh7752evb/MAINTAINERS b/board/renesas/sh7752evb/MAINTAINERS deleted file mode 100644 index 9840477d7dd2..000000000000 --- a/board/renesas/sh7752evb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SH7752EVB BOARD -#M: - -S: Maintained -F: board/renesas/sh7752evb/ -F: include/configs/sh7752evb.h -F: configs/sh7752evb_defconfig diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile deleted file mode 100644 index 658dc3bc6ded..000000000000 --- a/board/renesas/sh7752evb/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com -# - -obj-y := sh7752evb.o spi-boot.o -extra-y += lowlevel_init.o diff --git a/board/renesas/sh7752evb/lowlevel_init.S b/board/renesas/sh7752evb/lowlevel_init.S deleted file mode 100644 index 0f7b643ad8fe..000000000000 --- a/board/renesas/sh7752evb/lowlevel_init.S +++ /dev/null @@ -1,445 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -.macro or32, addr, data - mov.l \addr, r1 - mov.l \data, r0 - mov.l @r1, r2 - or r2, r0 - mov.l r0, @r1 -.endm - -.macro wait_DBCMD - mov.l DBWAIT_A, r0 - mov.l @r0, r1 -.endm - - .global lowlevel_init - .section .spiboot1.text - .align 2 - -lowlevel_init: - /*------- GPIO -------*/ - write16 PDCR_A, PDCR_D ! SPI0 - write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1) - write16 PJCR_A, PJCR_D ! SCIF4 - write16 PTCR_A, PTCR_D ! STATUS - write16 PSEL1_A, PSEL1_D ! SPI0 - write16 PSEL2_A, PSEL2_D ! SPI0 - write16 PSEL5_A, PSEL5_D ! STATUS - - bra exit_gpio - nop - - .align 2 - -/*------- GPIO -------*/ -PDCR_A: .long 0xffec0006 -PGCR_A: .long 0xffec000c -PJCR_A: .long 0xffec0012 -PTCR_A: .long 0xffec0026 -PSEL1_A: .long 0xffec0072 -PSEL2_A: .long 0xffec0074 -PSEL5_A: .long 0xffec007a - -PDCR_D: .long 0x0000 -PGCR_D: .long 0x0004 -PJCR_D: .long 0x0000 -PTCR_D: .long 0x0000 -PSEL1_D: .long 0x0000 -PSEL2_D: .long 0x3000 -PSEL5_D: .long 0x0ffc - - .align 2 - -exit_gpio: - mov #0, r14 - mova 2f, r0 - mov.l PC_MASK, r1 - tst r0, r1 - bf 2f - - bra exit_pmb - nop - - .align 2 - -/* If CPU runs on SDRAM (PC=0x5???????) or not. */ -PC_MASK: .long 0x20000000 - -2: - mov #1, r14 - - mov.l EXPEVT_A, r0 - mov.l @r0, r0 - mov.l EXPEVT_POWER_ON_RESET, r1 - cmp/eq r0, r1 - bt 1f - - /* - * If EXPEVT value is manual reset or tlb multipul-hit, - * initialization of DDR3IF is not necessary. - */ - bra exit_ddr - nop - -1: - /*------- Reset -------*/ - write32 MRSTCR0_A, MRSTCR0_D - write32 MRSTCR1_A, MRSTCR1_D - - /* For Core Reset */ - mov.l DBACEN_A, r0 - mov.l @r0, r0 - cmp/eq #0, r0 - bt 3f - - /* - * If DBACEN == 1(DBSC was already enabled), we have to avoid the - * initialization of DDR3-SDRAM. - */ - bra exit_ddr - nop - -3: - /*------- DDR3IF -------*/ - /* oscillation stabilization time */ - wait_timer WAIT_OSC_TIME - - /* step 3 */ - write32 DBCMD_A, DBCMD_RSTL_VAL - wait_timer WAIT_30US - - /* step 4 */ - write32 DBCMD_A, DBCMD_PDEN_VAL - - /* step 5 */ - write32 DBKIND_A, DBKIND_D - - /* step 6 */ - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBTR4_A, DBTR4_D - write32 DBTR5_A, DBTR5_D - write32 DBTR6_A, DBTR6_D - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D - write32 DBTR13_A, DBTR13_D - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D - write32 DBTR17_A, DBTR17_D - write32 DBTR18_A, DBTR18_D - write32 DBTR19_A, DBTR19_D - write32 DBRNK0_A, DBRNK0_D - - /* step 7 */ - write32 DBPDCNT3_A, DBPDCNT3_D - - /* step 8 */ - write32 DBPDCNT1_A, DBPDCNT1_D - write32 DBPDCNT2_A, DBPDCNT2_D - write32 DBPDLCK_A, DBPDLCK_D - write32 DBPDRGA_A, DBPDRGA_D - write32 DBPDRGD_A, DBPDRGD_D - - /* step 9 */ - wait_timer WAIT_30US - - /* step 10 */ - write32 DBPDCNT0_A, DBPDCNT0_D - - /* step 11 */ - wait_timer WAIT_30US - wait_timer WAIT_30US - - /* step 12 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - wait_DBCMD - - /* step 13 */ - write32 DBCMD_A, DBCMD_RSTH_VAL - wait_DBCMD - - /* step 14 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - - /* step 15 */ - write32 DBCMD_A, DBCMD_PDXT_VAL - - /* step 16 */ - write32 DBCMD_A, DBCMD_MRS2_VAL - - /* step 17 */ - write32 DBCMD_A, DBCMD_MRS3_VAL - - /* step 18 */ - write32 DBCMD_A, DBCMD_MRS1_VAL - - /* step 19 */ - write32 DBCMD_A, DBCMD_MRS0_VAL - - /* step 20 */ - write32 DBCMD_A, DBCMD_ZQCL_VAL - - write32 DBCMD_A, DBCMD_REF_VAL - write32 DBCMD_A, DBCMD_REF_VAL - wait_DBCMD - - /* step 21 */ - write32 DBADJ0_A, DBADJ0_D - write32 DBADJ1_A, DBADJ1_D - write32 DBADJ2_A, DBADJ2_D - - /* step 22 */ - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D - write32 DBRFCNF2_A, DBRFCNF2_D - - /* step 23 */ - write32 DBCALCNF_A, DBCALCNF_D - - /* step 24 */ - write32 DBRFEN_A, DBRFEN_D - write32 DBCMD_A, DBCMD_SRXT_VAL - - /* step 25 */ - write32 DBACEN_A, DBACEN_D - - /* step 26 */ - wait_DBCMD - - bra exit_ddr - nop - - .align 2 - -EXPEVT_A: .long 0xff000024 -EXPEVT_POWER_ON_RESET: .long 0x00000000 - -/*------- Reset -------*/ -MRSTCR0_A: .long 0xffd50030 -MRSTCR0_D: .long 0xfe1ffe7f -MRSTCR1_A: .long 0xffd50034 -MRSTCR1_D: .long 0xfff3ffff - -/*------- DDR3IF -------*/ -DBCMD_A: .long 0xfe800018 -DBKIND_A: .long 0xfe800020 -DBCONF_A: .long 0xfe800024 -DBTR0_A: .long 0xfe800040 -DBTR1_A: .long 0xfe800044 -DBTR2_A: .long 0xfe800048 -DBTR3_A: .long 0xfe800050 -DBTR4_A: .long 0xfe800054 -DBTR5_A: .long 0xfe800058 -DBTR6_A: .long 0xfe80005c -DBTR7_A: .long 0xfe800060 -DBTR8_A: .long 0xfe800064 -DBTR9_A: .long 0xfe800068 -DBTR10_A: .long 0xfe80006c -DBTR11_A: .long 0xfe800070 -DBTR12_A: .long 0xfe800074 -DBTR13_A: .long 0xfe800078 -DBTR14_A: .long 0xfe80007c -DBTR15_A: .long 0xfe800080 -DBTR16_A: .long 0xfe800084 -DBTR17_A: .long 0xfe800088 -DBTR18_A: .long 0xfe80008c -DBTR19_A: .long 0xfe800090 -DBRNK0_A: .long 0xfe800100 -DBPDCNT0_A: .long 0xfe800200 -DBPDCNT1_A: .long 0xfe800204 -DBPDCNT2_A: .long 0xfe800208 -DBPDCNT3_A: .long 0xfe80020c -DBPDLCK_A: .long 0xfe800280 -DBPDRGA_A: .long 0xfe800290 -DBPDRGD_A: .long 0xfe8002a0 -DBADJ0_A: .long 0xfe8000c0 -DBADJ1_A: .long 0xfe8000c4 -DBADJ2_A: .long 0xfe8000c8 -DBRFCNF0_A: .long 0xfe8000e0 -DBRFCNF1_A: .long 0xfe8000e4 -DBRFCNF2_A: .long 0xfe8000e8 -DBCALCNF_A: .long 0xfe8000f4 -DBRFEN_A: .long 0xfe800014 -DBACEN_A: .long 0xfe800010 -DBWAIT_A: .long 0xfe80001c - -WAIT_OSC_TIME: .long 6000 -WAIT_30US: .long 13333 - -DBCMD_RSTL_VAL: .long 0x20000000 -DBCMD_PDEN_VAL: .long 0x1000d73c -DBCMD_WAIT_VAL: .long 0x0000d73c -DBCMD_RSTH_VAL: .long 0x2100d73c -DBCMD_PDXT_VAL: .long 0x110000c8 -DBCMD_MRS0_VAL: .long 0x28000930 -DBCMD_MRS1_VAL: .long 0x29000004 -DBCMD_MRS2_VAL: .long 0x2a000008 -DBCMD_MRS3_VAL: .long 0x2b000000 -DBCMD_ZQCL_VAL: .long 0x03000200 -DBCMD_REF_VAL: .long 0x0c000000 -DBCMD_SRXT_VAL: .long 0x19000000 -DBKIND_D: .long 0x00000007 -DBCONF_D: .long 0x0f030a01 -DBTR0_D: .long 0x00000007 -DBTR1_D: .long 0x00000006 -DBTR2_D: .long 0x00000000 -DBTR3_D: .long 0x00000007 -DBTR4_D: .long 0x00070007 -DBTR5_D: .long 0x0000001b -DBTR6_D: .long 0x00000014 -DBTR7_D: .long 0x00000005 -DBTR8_D: .long 0x00000015 -DBTR9_D: .long 0x00000006 -DBTR10_D: .long 0x00000008 -DBTR11_D: .long 0x00000007 -DBTR12_D: .long 0x0000000e -DBTR13_D: .long 0x00000056 -DBTR14_D: .long 0x00000006 -DBTR15_D: .long 0x00000004 -DBTR16_D: .long 0x00150002 -DBTR17_D: .long 0x000c0017 -DBTR18_D: .long 0x00000200 -DBTR19_D: .long 0x00000040 -DBRNK0_D: .long 0x00000001 -DBPDCNT0_D: .long 0x00000001 -DBPDCNT1_D: .long 0x00000001 -DBPDCNT2_D: .long 0x00000000 -DBPDCNT3_D: .long 0x00004010 -DBPDLCK_D: .long 0x0000a55a -DBPDRGA_D: .long 0x00000028 -DBPDRGD_D: .long 0x00017100 - -DBADJ0_D: .long 0x00000000 -DBADJ1_D: .long 0x00000000 -DBADJ2_D: .long 0x18061806 -DBRFCNF0_D: .long 0x000001ff -DBRFCNF1_D: .long 0x08001000 -DBRFCNF2_D: .long 0x00000000 -DBCALCNF_D: .long 0x0000ffff -DBRFEN_D: .long 0x00000001 -DBACEN_D: .long 0x00000001 - - .align 2 -exit_ddr: -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - */ - write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D - write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - - write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif /* if defined(CONFIG_SH_32BIT) */ - -exit_pmb: - /* CPU is running on ILRAM? */ - mov r14, r0 - tst #1, r0 - bt 1f - - mov.l _stack_ilram, r15 - mov.l _spiboot_main, r0 -100: bsrf r0 - nop - - .align 2 -_spiboot_main: .long (spiboot_main - (100b + 4)) -_stack_ilram: .long 0xe5204000 - -1: - write32 CCR_A, CCR_D - - rts - nop - - .align 2 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) -PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) -PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) -PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) -PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) -PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) -PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) -PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) -PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) -PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) -PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) -PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) -PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) -PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) - -PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_NOT_USE_D: .long 0x00000000 - -PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) - -PASCR_A: .long 0xff000070 -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long CCR -CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c deleted file mode 100644 index 522b4bd610dc..000000000000 --- a/board/renesas/sh7752evb/sh7752evb.c +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <flash.h> -#include <init.h> -#include <malloc.h> -#include <net.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmc.h> -#include <spi.h> -#include <spi_flash.h> -#include <linux/delay.h> - -int checkboard(void) -{ - puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n"); - - return 0; -} - -static void init_gpio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - struct sermux_regs *sermux = SERMUX_BASE; - - /* GPIO */ - writew(0x0000, &gpio->pacr); /* GETHER */ - writew(0x0001, &gpio->pbcr); /* INTC */ - writew(0x0000, &gpio->pccr); /* PWMU, INTC */ - writew(0xeaff, &gpio->pecr); /* GPIO */ - writew(0x0000, &gpio->pfcr); /* WDT */ - writew(0x0000, &gpio->phcr); /* SPI1 */ - writew(0x0000, &gpio->picr); /* SDHI */ - writew(0x0003, &gpio->pkcr); /* SerMux */ - writew(0x0000, &gpio->plcr); /* SerMux */ - writew(0x0000, &gpio->pmcr); /* RIIC */ - writew(0x0000, &gpio->pncr); /* USB, SGPIO */ - writew(0x0000, &gpio->pocr); /* SGPIO */ - writew(0xd555, &gpio->pqcr); /* GPIO */ - writew(0x0000, &gpio->prcr); /* RIIC */ - writew(0x0000, &gpio->pscr); /* RIIC */ - writeb(0x00, &gpio->pudr); - writew(0x5555, &gpio->pucr); /* Debug LED */ - writew(0x0000, &gpio->pvcr); /* RSPI */ - writew(0x0000, &gpio->pwcr); /* EVC */ - writew(0x0000, &gpio->pxcr); /* LBSC */ - writew(0x0000, &gpio->pycr); /* LBSC */ - writew(0x0000, &gpio->pzcr); /* eMMC */ - writew(0xfe00, &gpio->psel0); - writew(0xff00, &gpio->psel3); - writew(0x771f, &gpio->psel4); - writew(0x00ff, &gpio->psel6); - writew(0xfc00, &gpio->psel7); - - writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ -} - -static void init_usb_phy(void) -{ - struct usb_common_regs *common0 = USB0_COMMON_BASE; - struct usb_common_regs *common1 = USB1_COMMON_BASE; - struct usb0_phy_regs *phy = USB0_PHY_BASE; - struct usb1_port_regs *port = USB1_PORT_BASE; - struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; - - writew(0x0100, &phy->reset); /* set reset */ - /* port0 = USB0, port1 = USB1 */ - writew(0x0002, &phy->portsel); - writel(0x0001, &port->port1sel); /* port1 = Host */ - writew(0x0111, &phy->reset); /* clear reset */ - - writew(0x4000, &common0->suspmode); - writew(0x4000, &common1->suspmode); - -#if defined(__LITTLE_ENDIAN) - writel(0x00000000, &align->ehcidatac); - writel(0x00000000, &align->ohcidatac); -#endif -} - -static void init_gether_mdio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); - writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ -} - -static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - string_to_enetaddr(mac_string, mac); - - if (!channel) - ether = GETHER0_MAC_BASE; - else - ether = GETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -/***************************************************************** - * This PMB must be set on this timing. The lowlevel_init is run on - * Area 0(phys 0x00000000), so we have to map it. - * - * The new PMB table is following: - * ent virt phys v sz c wt - * 0 0xa0000000 0x40000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 2 0xb0000000 0x50000000 1 128M 0 1 - * 3 0xb8000000 0x58000000 1 128M 0 1 - * 4 0x80000000 0x40000000 1 128M 1 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - * 6 0x90000000 0x50000000 1 128M 1 1 - * 7 0x98000000 0x58000000 1 128M 1 1 - */ -static void set_pmb_on_board_init(void) -{ - struct mmu_regs *mmu = MMU_BASE; - - /* clear ITLB */ - writel(0x00000004, &mmu->mmucr); - - /* delete PMB for SPIBOOT */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - /* ppn ub v s1 s0 c wt */ - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); - writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); - writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); - writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); - writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); - writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); - writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); - writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); - writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); -} - -int board_init(void) -{ - init_gpio(); - set_pmb_on_board_init(); - - init_usb_phy(); - init_gether_mdio(); - - return 0; -} - -int board_mmc_init(struct bd_info *bis) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); - writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ - udelay(1); - writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ - udelay(200); - - return mmcif_mmc_init(); -} - -static int get_sh_eth_mac_raw(unsigned char *buf, int size) -{ -#ifdef CONFIG_DEPRECATED - struct spi_flash *spi; - int ret; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (spi == NULL) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf); - if (ret) { - printf("%s: spi_flash read failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); -#endif - - return 0; -} - -static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) -{ - memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)], - SH7752EVB_ETHERNET_MAC_SIZE); - mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ - - return 0; -} - -static void init_ethernet_mac(void) -{ - char mac_string[64]; - char env_string[64]; - int i; - unsigned char *buf; - - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return; - } - get_sh_eth_mac_raw(buf, 256); - - /* Gigabit Ethernet */ - for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i == 0) - env_set("ethaddr", mac_string); - else { - sprintf(env_string, "eth%daddr", i); - env_set(env_string, mac_string); - } - set_mac_to_sh_giga_eth_register(i, mac_string); - } - - free(buf); -} - -int board_late_init(void) -{ - init_ethernet_mac(); - - return 0; -} - -#ifdef CONFIG_DEPRECATED -int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int i, ret; - char mac_string[256]; - struct spi_flash *spi; - unsigned char *buf; - - if (argc != 3) { - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return 1; - } - - get_sh_eth_mac_raw(buf, 256); - - /* print current MAC address */ - for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - printf("GETHERC ch%d = %s\n", i, mac_string); - } - free(buf); - return 0; - } - - /* new setting */ - memset(mac_string, 0xff, sizeof(mac_string)); - sprintf(mac_string, "%s\t%s", - argv[1], argv[2]); - - /* write MAC data to SPI rom */ - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, - SH7752EVB_SPI_SECTOR_SIZE); - if (ret) { - printf("%s: spi_flash erase failed.\n", __func__); - return 1; - } - - ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, - sizeof(mac_string), mac_string); - if (ret) { - printf("%s: spi_flash write failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - puts("The writing of the MAC address to SPI ROM was completed.\n"); - - return 0; -} - -U_BOOT_CMD( - write_mac, 3, 1, do_write_mac, - "write MAC address for GETHERC", - "[GETHERC ch0] [GETHERC ch1]\n" -); -#endif diff --git a/board/renesas/sh7752evb/spi-boot.c b/board/renesas/sh7752evb/spi-boot.c deleted file mode 100644 index 91565d44d7f8..000000000000 --- a/board/renesas/sh7752evb/spi-boot.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License. See the file "COPYING.LIB" in the main - * directory of this archive for more details. - */ - -#include <common.h> - -#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE -#define CONFIG_SPI_ADDR 0x00000000 -#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN -#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE - -#define SPIWDMADR 0xFE001018 -#define SPIWDMCNTR 0xFE001020 -#define SPIDMCOR 0xFE001028 -#define SPIDMINTSR 0xFE001188 -#define SPIDMINTMR 0xFE001190 - -#define SPIDMINTSR_DMEND 0x00000004 - -#define TBR 0xFE002000 -#define RBR 0xFE002000 - -#define CR1 0xFE002008 -#define CR2 0xFE002010 -#define CR3 0xFE002018 -#define CR4 0xFE002020 - -/* CR1 */ -#define SPI_TBE 0x80 -#define SPI_TBF 0x40 -#define SPI_RBE 0x20 -#define SPI_RBF 0x10 -#define SPI_PFONRD 0x08 -#define SPI_SSDB 0x04 -#define SPI_SSD 0x02 -#define SPI_SSA 0x01 - -/* CR2 */ -#define SPI_RSTF 0x80 -#define SPI_LOOPBK 0x40 -#define SPI_CPOL 0x20 -#define SPI_CPHA 0x10 -#define SPI_L1M0 0x08 - -/* CR4 */ -#define SPI_TBEI 0x80 -#define SPI_TBFI 0x40 -#define SPI_RBEI 0x20 -#define SPI_RBFI 0x10 -#define SPI_SpiS0 0x02 -#define SPI_SSS 0x01 - -#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val -#define spi_read(addr) (*(volatile unsigned long *)(addr)) - -/* M25P80 */ -#define M25_READ 0x03 - -#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) -static void __uses_spiboot2 spi_reset(void) -{ - int timeout = 0x00100000; - - /* Make sure the last transaction is finalized */ - spi_write(0x00, CR3); - spi_write(0x02, CR1); - while (!(spi_read(CR4) & SPI_SpiS0)) { - if (timeout-- < 0) - break; - } - spi_write(0x00, CR1); - - spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ - spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); - - spi_write(0, SPIDMCOR); -} - -static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, - unsigned long len) -{ - spi_write(M25_READ, TBR); - spi_write((addr >> 16) & 0xFF, TBR); - spi_write((addr >> 8) & 0xFF, TBR); - spi_write(addr & 0xFF, TBR); - - spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); - spi_write((unsigned long)buf, SPIWDMADR); - spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); - spi_write(1, SPIDMCOR); - - spi_write(0xff, CR3); - spi_write(spi_read(CR1) | SPI_SSDB, CR1); - spi_write(spi_read(CR1) | SPI_SSA, CR1); - - while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) - ; - - /* Nagate SP0-SS0 */ - spi_write(0, CR1); -} - -void __uses_spiboot2 spiboot_main(void) -{ - void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; - - spi_reset(); - spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, - CONFIG_SPI_LENGTH); - - _start(); -} diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig deleted file mode 100644 index bc174f466134..000000000000 --- a/configs/sh7752evb_defconfig +++ /dev/null @@ -1,39 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x5ff80000 -CONFIG_ENV_SIZE=0x10000 -CONFIG_SH_32BIT=y -CONFIG_TARGET_SH7752EVB=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC2,115200 root=/dev/nfs ip=dhcp" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_MD5SUM=y -# CONFIG_CMD_LOADB is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_EXT2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MMC=y -CONFIG_SH_MMCIF=y -CONFIG_BITBANGMII=y -CONFIG_PHY_VITESSE=y -CONFIG_SH_ETHER=y -CONFIG_SCIF_CONSOLE=y -CONFIG_SPI=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/doc/board/renesas/index.rst b/doc/board/renesas/index.rst index 34e62baff620..401ffcf61b25 100644 --- a/doc/board/renesas/index.rst +++ b/doc/board/renesas/index.rst @@ -6,5 +6,4 @@ Renesas .. toctree:: :maxdepth: 2
- sh7752evb sh7753evb diff --git a/doc/board/renesas/sh7752evb.rst b/doc/board/renesas/sh7752evb.rst deleted file mode 100644 index 272d6dde053e..000000000000 --- a/doc/board/renesas/sh7752evb.rst +++ /dev/null @@ -1,79 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ - -R0P7752C00000RZ board -===================== - -This board specification ------------------------- - -The R0P7752C00000RZ(board config name:sh7752evb) has the following device: - - - SH7752 (SH-4A) - - DDR3-SDRAM 512MB - - SPI ROM 8MB - - Gigabit Ethernet controllers - - eMMC 4GB - - -Configuration for This board ----------------------------- - -You can select the configuration as follows: - - - make sh7752evb_config - - -This board specific command ---------------------------- - -This board has the following its specific command: - -write_mac: - You can write MAC address to SPI ROM. - -Usage 1: Write MAC address - -.. code-block:: none - - write_mac [GETHERC ch0] [GETHERC ch1] - - For example: - => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f - -* We have to input the command as a single line (without carriage return) -* We have to reset after input the command. - -Usage 2: Show current data - -.. code-block:: none - - write_mac - - For example: - => write_mac - GETHERC ch0 = 74:90:50:00:33:9e - GETHERC ch1 = 74:90:50:00:33:9f - - -Update SPI ROM --------------- - -1. Copy u-boot image to RAM area. -2. Probe SPI device. - -.. code-block:: none - - => sf probe 0 - SF: Detected MX25L6405D with page size 64KiB, total 8 MiB - -3. Erase SPI ROM. - -.. code-block:: none - - => sf erase 0 80000 - -4. Write u-boot image to SPI ROM. - -.. code-block:: none - - => sf write 0x48000000 0 80000 diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h deleted file mode 100644 index aeb54032d198..000000000000 --- a/include/configs/sh7752evb.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the sh7752evb board - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __SH7752EVB_H -#define __SH7752EVB_H - -#define CONFIG_CPU_SH7752 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* MEMORY */ -#define SH7752EVB_SDRAM_BASE (0x40000000) -#define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_CONS_SCIF2 1 - -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ - 128 * 1024 * 1024) - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 18 -#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 -#define CONFIG_SH_ETHER_USE_GETHER 1 -#define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII - -#define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000 -#define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024) -#define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI -#define SH7752EVB_ETHERNET_MAC_SIZE 17 -#define SH7752EVB_ETHERNET_NUM_CH 2 - -/* SPI */ -#define CONFIG_SH_SPI_BASE 0xfe002000 - -/* MMCIF */ -#define CONFIG_SH_MMCIF_ADDR 0xffcb0000 -#define CONFIG_SH_MMCIF_CLK 48000000 - -/* ENV setting */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netboot=bootp; bootm\0" - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 48000000 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ -#endif /* __SH7752EVB_H */
On Wed, Feb 10, 2021 at 12:51:23PM -0500, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/sh/Kconfig | 5 - board/renesas/sh7753evb/Kconfig | 12 - board/renesas/sh7753evb/MAINTAINERS | 6 - board/renesas/sh7753evb/Makefile | 7 - board/renesas/sh7753evb/lowlevel_init.S | 414 ------------------------ board/renesas/sh7753evb/sh7753evb.c | 329 ------------------- board/renesas/sh7753evb/spi-boot.c | 133 -------- configs/sh7753evb_defconfig | 38 --- doc/board/index.rst | 1 - doc/board/renesas/index.rst | 9 - doc/board/renesas/sh7753evb.rst | 79 ----- include/configs/sh7753evb.h | 65 ---- 12 files changed, 1098 deletions(-) delete mode 100644 board/renesas/sh7753evb/Kconfig delete mode 100644 board/renesas/sh7753evb/MAINTAINERS delete mode 100644 board/renesas/sh7753evb/Makefile delete mode 100644 board/renesas/sh7753evb/lowlevel_init.S delete mode 100644 board/renesas/sh7753evb/sh7753evb.c delete mode 100644 board/renesas/sh7753evb/spi-boot.c delete mode 100644 configs/sh7753evb_defconfig delete mode 100644 doc/board/renesas/index.rst delete mode 100644 doc/board/renesas/sh7753evb.rst delete mode 100644 include/configs/sh7753evb.h
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 8446d9587ed5..d8d2a7ffe9d0 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -25,10 +25,6 @@ config TARGET_R2DPLUS bool "Renesas R2D-PLUS" select CPU_SH4
-config TARGET_SH7753EVB - bool "SH7753EVB" - select CPU_SH4 - config TARGET_SH7757LCR bool "SH7757LCR" select CPU_SH4A @@ -48,7 +44,6 @@ config SYS_CPU source "arch/sh/lib/Kconfig"
source "board/renesas/r2dplus/Kconfig" -source "board/renesas/sh7753evb/Kconfig" source "board/renesas/sh7757lcr/Kconfig" source "board/renesas/sh7763rdp/Kconfig"
diff --git a/board/renesas/sh7753evb/Kconfig b/board/renesas/sh7753evb/Kconfig deleted file mode 100644 index be889248a8e7..000000000000 --- a/board/renesas/sh7753evb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SH7753EVB - -config SYS_BOARD - default "sh7753evb" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "sh7753evb" - -endif diff --git a/board/renesas/sh7753evb/MAINTAINERS b/board/renesas/sh7753evb/MAINTAINERS deleted file mode 100644 index b6c85eedab75..000000000000 --- a/board/renesas/sh7753evb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SH7753EVB BOARD -#M: - -S: Maintained -F: board/renesas/sh7753evb/ -F: include/configs/sh7753evb.h -F: configs/sh7753evb_defconfig diff --git a/board/renesas/sh7753evb/Makefile b/board/renesas/sh7753evb/Makefile deleted file mode 100644 index e1e099777c71..000000000000 --- a/board/renesas/sh7753evb/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com -# - -obj-y := sh7753evb.o spi-boot.o -extra-y += lowlevel_init.o diff --git a/board/renesas/sh7753evb/lowlevel_init.S b/board/renesas/sh7753evb/lowlevel_init.S deleted file mode 100644 index 901e9eb64887..000000000000 --- a/board/renesas/sh7753evb/lowlevel_init.S +++ /dev/null @@ -1,414 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Renesas Solutions Corp. - */ - -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -.macro or32, addr, data - mov.l \addr, r1 - mov.l \data, r0 - mov.l @r1, r2 - or r2, r0 - mov.l r0, @r1 -.endm - -.macro wait_DBCMD - mov.l DBWAIT_A, r0 - mov.l @r0, r1 -.endm - - .global lowlevel_init - .section .spiboot1.text - .align 2 - -lowlevel_init: - mov #0, r14 - mova 2f, r0 - mov.l PC_MASK, r1 - tst r0, r1 - bf 2f - - bra exit_pmb - nop - - .align 2 - -/* If CPU runs on SDRAM (PC=0x5???????) or not. */ -PC_MASK: .long 0x20000000 - -2: - mov #1, r14 - - mov.l EXPEVT_A, r0 - mov.l @r0, r0 - mov.l EXPEVT_POWER_ON_RESET, r1 - cmp/eq r0, r1 - bt 1f - - /* - * If EXPEVT value is manual reset or tlb multipul-hit, - * initialization of DBSC3 is not necessary. - */ - bra exit_ddr - nop - -1: - /*------- Reset -------*/ - write32 MRSTCR0_A, MRSTCR0_D - write32 MRSTCR1_A, MRSTCR1_D - - /* For Core Reset */ - mov.l DBACEN_A, r0 - mov.l @r0, r0 - cmp/eq #0, r0 - bt 3f - - /* - * If DBACEN == 1(DBSC was already enabled), we have to avoid the - * initialization of DDR3-SDRAM. - */ - bra exit_ddr - nop - -3: - /*------- DBSC3 -------*/ - /* oscillation stabilization time */ - wait_timer WAIT_OSC_TIME - - /* step 3 */ - write32 DBKIND_A, DBKIND_D - - /* step 4 */ - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBTR4_A, DBTR4_D - write32 DBTR5_A, DBTR5_D - write32 DBTR6_A, DBTR6_D - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D - write32 DBTR13_A, DBTR13_D - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D - write32 DBTR17_A, DBTR17_D - write32 DBTR18_A, DBTR18_D - write32 DBTR19_A, DBTR19_D - write32 DBRNK0_A, DBRNK0_D - write32 DBADJ0_A, DBADJ0_D - write32 DBADJ2_A, DBADJ2_D - - /* step 5 */ - write32 DBCMD_A, DBCMD_RSTL_VAL - wait_timer WAIT_30US - - /* step 6 */ - write32 DBCMD_A, DBCMD_PDEN_VAL - - /* step 7 */ - write32 DBPDCNT3_A, DBPDCNT3_D - - /* step 8 */ - write32 DBPDCNT1_A, DBPDCNT1_D - write32 DBPDCNT2_A, DBPDCNT2_D - write32 DBPDLCK_A, DBPDLCK_D - write32 DBPDRGA_A, DBPDRGA_D - write32 DBPDRGD_A, DBPDRGD_D - - /* step 9 */ - wait_timer WAIT_30US - - /* step 10 */ - write32 DBPDCNT0_A, DBPDCNT0_D - - /* step 11 */ - wait_timer WAIT_30US - wait_timer WAIT_30US - - /* step 12 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - wait_DBCMD - - /* step 13 */ - write32 DBCMD_A, DBCMD_RSTH_VAL - wait_DBCMD - - /* step 14 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - - /* step 15 */ - write32 DBCMD_A, DBCMD_PDXT_VAL - - /* step 16 */ - write32 DBCMD_A, DBCMD_MRS2_VAL - - /* step 17 */ - write32 DBCMD_A, DBCMD_MRS3_VAL - - /* step 18 */ - write32 DBCMD_A, DBCMD_MRS1_VAL - - /* step 19 */ - write32 DBCMD_A, DBCMD_MRS0_VAL - write32 DBPDNCNF_A, DBPDNCNF_D - - /* step 20 */ - write32 DBCMD_A, DBCMD_ZQCL_VAL - - write32 DBCMD_A, DBCMD_REF_VAL - write32 DBCMD_A, DBCMD_REF_VAL - wait_DBCMD - - /* step 21 */ - write32 DBCALTR_A, DBCALTR_D - - /* step 22 */ - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D - write32 DBRFCNF2_A, DBRFCNF2_D - - /* step 23 */ - write32 DBCALCNF_A, DBCALCNF_D - - /* step 24 */ - write32 DBRFEN_A, DBRFEN_D - write32 DBCMD_A, DBCMD_SRXT_VAL - - /* step 25 */ - write32 DBACEN_A, DBACEN_D - - /* step 26 */ - wait_DBCMD - - bra exit_ddr - nop - - .align 2 - -EXPEVT_A: .long 0xff000024 -EXPEVT_POWER_ON_RESET: .long 0x00000000 - -/*------- Reset -------*/ -MRSTCR0_A: .long 0xffd50030 -MRSTCR0_D: .long 0xfe1ffe7f -MRSTCR1_A: .long 0xffd50034 -MRSTCR1_D: .long 0xfff3ffff - -/*------- DBSC3 -------*/ -DBCMD_A: .long 0xfe800018 -DBKIND_A: .long 0xfe800020 -DBCONF_A: .long 0xfe800024 -DBTR0_A: .long 0xfe800040 -DBTR1_A: .long 0xfe800044 -DBTR2_A: .long 0xfe800048 -DBTR3_A: .long 0xfe800050 -DBTR4_A: .long 0xfe800054 -DBTR5_A: .long 0xfe800058 -DBTR6_A: .long 0xfe80005c -DBTR7_A: .long 0xfe800060 -DBTR8_A: .long 0xfe800064 -DBTR9_A: .long 0xfe800068 -DBTR10_A: .long 0xfe80006c -DBTR11_A: .long 0xfe800070 -DBTR12_A: .long 0xfe800074 -DBTR13_A: .long 0xfe800078 -DBTR14_A: .long 0xfe80007c -DBTR15_A: .long 0xfe800080 -DBTR16_A: .long 0xfe800084 -DBTR17_A: .long 0xfe800088 -DBTR18_A: .long 0xfe80008c -DBTR19_A: .long 0xfe800090 -DBRNK0_A: .long 0xfe800100 -DBPDCNT0_A: .long 0xfe800200 -DBPDCNT1_A: .long 0xfe800204 -DBPDCNT2_A: .long 0xfe800208 -DBPDCNT3_A: .long 0xfe80020c -DBPDLCK_A: .long 0xfe800280 -DBPDRGA_A: .long 0xfe800290 -DBPDRGD_A: .long 0xfe8002a0 -DBADJ0_A: .long 0xfe8000c0 -DBADJ2_A: .long 0xfe8000c8 -DBRFCNF0_A: .long 0xfe8000e0 -DBRFCNF1_A: .long 0xfe8000e4 -DBRFCNF2_A: .long 0xfe8000e8 -DBCALCNF_A: .long 0xfe8000f4 -DBRFEN_A: .long 0xfe800014 -DBACEN_A: .long 0xfe800010 -DBWAIT_A: .long 0xfe80001c -DBCALTR_A: .long 0xfe8000f8 -DBPDNCNF_A: .long 0xfe800180 - -WAIT_OSC_TIME: .long 6000 -WAIT_30US: .long 13333 - -DBCMD_RSTL_VAL: .long 0x20000000 -DBCMD_PDEN_VAL: .long 0x1000d73c -DBCMD_WAIT_VAL: .long 0x0000d73c -DBCMD_RSTH_VAL: .long 0x2100d73c -DBCMD_PDXT_VAL: .long 0x110000c8 -DBCMD_MRS0_VAL: .long 0x28000930 -DBCMD_MRS1_VAL: .long 0x29000004 -DBCMD_MRS2_VAL: .long 0x2a000008 -DBCMD_MRS3_VAL: .long 0x2b000000 -DBCMD_ZQCL_VAL: .long 0x03000200 -DBCMD_REF_VAL: .long 0x0c000000 -DBCMD_SRXT_VAL: .long 0x19000000 -DBKIND_D: .long 0x00000007 -DBCONF_D: .long 0x0f030a01 -DBTR0_D: .long 0x00000007 -DBTR1_D: .long 0x00000006 -DBTR2_D: .long 0x00000000 -DBTR3_D: .long 0x00000007 -DBTR4_D: .long 0x00070007 -DBTR5_D: .long 0x0000001b -DBTR6_D: .long 0x00000014 -DBTR7_D: .long 0x00000004 -DBTR8_D: .long 0x00000014 -DBTR9_D: .long 0x00000004 -DBTR10_D: .long 0x00000008 -DBTR11_D: .long 0x00000007 -DBTR12_D: .long 0x0000000e -DBTR13_D: .long 0x000000a0 -DBTR14_D: .long 0x00060006 -DBTR15_D: .long 0x00000003 -DBTR16_D: .long 0x00160002 -DBTR17_D: .long 0x000c0000 -DBTR18_D: .long 0x00000200 -DBTR19_D: .long 0x00000040 -DBRNK0_D: .long 0x00000001 -DBPDCNT0_D: .long 0x00000001 -DBPDCNT1_D: .long 0x00000001 -DBPDCNT2_D: .long 0x00000000 -DBPDCNT3_D: .long 0x00004010 -DBPDLCK_D: .long 0x0000a55a -DBPDRGA_D: .long 0x00000028 -DBPDRGD_D: .long 0x00017100 - -DBADJ0_D: .long 0x00010000 -DBADJ2_D: .long 0x18061806 -DBRFCNF0_D: .long 0x000001ff -DBRFCNF1_D: .long 0x00081040 -DBRFCNF2_D: .long 0x00000000 -DBCALCNF_D: .long 0x0000ffff -DBRFEN_D: .long 0x00000001 -DBACEN_D: .long 0x00000001 -DBCALTR_D: .long 0x08200820 -DBPDNCNF_D: .long 0x00000001 - - .align 2 -exit_ddr: -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - */ - write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D - write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - - write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif /* if defined(CONFIG_SH_32BIT) */ - -exit_pmb: - /* CPU is running on ILRAM? */ - mov r14, r0 - tst #1, r0 - bt 1f - - mov.l _stack_ilram, r15 - mov.l _spiboot_main, r0 -100: bsrf r0 - nop - - .align 2 -_spiboot_main: .long (spiboot_main - (100b + 4)) -_stack_ilram: .long 0xe5204000 - -1: - write32 CCR_A, CCR_D - - rts - nop - - .align 2 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) -PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) -PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) -PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) -PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) -PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) -PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) -PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) -PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) -PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) -PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) -PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) -PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) -PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) - -PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_NOT_USE_D: .long 0x00000000 - -PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) - -PASCR_A: .long 0xff000070 -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long CCR -CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c deleted file mode 100644 index f34dec1dfabd..000000000000 --- a/board/renesas/sh7753evb/sh7753evb.c +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <flash.h> -#include <init.h> -#include <malloc.h> -#include <net.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmc.h> -#include <spi.h> -#include <spi_flash.h> -#include <linux/delay.h> - -int checkboard(void) -{ - puts("BOARD: SH7753 EVB\n"); - - return 0; -} - -static void init_gpio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - struct sermux_regs *sermux = SERMUX_BASE; - - /* GPIO */ - writew(0x0000, &gpio->pacr); /* GETHER */ - writew(0x0001, &gpio->pbcr); /* INTC */ - writew(0x0000, &gpio->pccr); /* PWMU, INTC */ - writew(0x0000, &gpio->pdcr); /* SPI0 */ - writew(0xeaff, &gpio->pecr); /* GPIO */ - writew(0x0000, &gpio->pfcr); /* WDT */ - writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ - writew(0x0000, &gpio->phcr); /* SPI1 */ - writew(0x0000, &gpio->picr); /* SDHI */ - writew(0x0000, &gpio->pjcr); /* SCIF4 */ - writew(0x0003, &gpio->pkcr); /* SerMux */ - writew(0x0000, &gpio->plcr); /* SerMux */ - writew(0x0000, &gpio->pmcr); /* RIIC */ - writew(0x0000, &gpio->pncr); /* USB, SGPIO */ - writew(0x0000, &gpio->pocr); /* SGPIO */ - writew(0xd555, &gpio->pqcr); /* GPIO */ - writew(0x0000, &gpio->prcr); /* RIIC */ - writew(0x0000, &gpio->pscr); /* RIIC */ - writew(0x0000, &gpio->ptcr); /* STATUS */ - writeb(0x00, &gpio->pudr); - writew(0x5555, &gpio->pucr); /* Debug LED */ - writew(0x0000, &gpio->pvcr); /* RSPI */ - writew(0x0000, &gpio->pwcr); /* EVC */ - writew(0x0000, &gpio->pxcr); /* LBSC */ - writew(0x0000, &gpio->pycr); /* LBSC */ - writew(0x0000, &gpio->pzcr); /* eMMC */ - writew(0xfe00, &gpio->psel0); - writew(0x0000, &gpio->psel1); - writew(0x3000, &gpio->psel2); - writew(0xff00, &gpio->psel3); - writew(0x771f, &gpio->psel4); - writew(0x0ffc, &gpio->psel5); - writew(0x00ff, &gpio->psel6); - writew(0xfc00, &gpio->psel7); - - writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ -} - -static void init_usb_phy(void) -{ - struct usb_common_regs *common0 = USB0_COMMON_BASE; - struct usb_common_regs *common1 = USB1_COMMON_BASE; - struct usb0_phy_regs *phy = USB0_PHY_BASE; - struct usb1_port_regs *port = USB1_PORT_BASE; - struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; - - writew(0x0100, &phy->reset); /* set reset */ - /* port0 = USB0, port1 = USB1 */ - writew(0x0002, &phy->portsel); - writel(0x0001, &port->port1sel); /* port1 = Host */ - writew(0x0111, &phy->reset); /* clear reset */ - - writew(0x4000, &common0->suspmode); - writew(0x4000, &common1->suspmode); - -#if defined(__LITTLE_ENDIAN) - writel(0x00000000, &align->ehcidatac); - writel(0x00000000, &align->ohcidatac); -#endif -} - -static void init_gether_mdio(void) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); - writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ -} - -static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - string_to_enetaddr(mac_string, mac); - - if (!channel) - ether = GETHER0_MAC_BASE; - else - ether = GETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -#if defined(CONFIG_SH_32BIT) -/***************************************************************** - * This PMB must be set on this timing. The lowlevel_init is run on - * Area 0(phys 0x00000000), so we have to map it. - * - * The new PMB table is following: - * ent virt phys v sz c wt - * 0 0xa0000000 0x40000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 2 0xb0000000 0x50000000 1 128M 0 1 - * 3 0xb8000000 0x58000000 1 128M 0 1 - * 4 0x80000000 0x40000000 1 128M 1 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - * 6 0x90000000 0x50000000 1 128M 1 1 - * 7 0x98000000 0x58000000 1 128M 1 1 - */ -static void set_pmb_on_board_init(void) -{ - struct mmu_regs *mmu = MMU_BASE; - - /* clear ITLB */ - writel(0x00000004, &mmu->mmucr); - - /* delete PMB for SPIBOOT */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - /* ppn ub v s1 s0 c wt */ - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); - writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); - writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); - writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); - writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); - writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); - writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); - writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); - writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); -} -#endif - -int board_init(void) -{ - struct gether_control_regs *gether = GETHER_CONTROL_BASE; - - init_gpio(); -#if defined(CONFIG_SH_32BIT) - set_pmb_on_board_init(); -#endif - - /* Sets TXnDLY to B'010 */ - writel(0x00000202, &gether->gbecont); - - init_usb_phy(); - init_gether_mdio(); - - return 0; -} - -int board_mmc_init(struct bd_info *bis) -{ - struct gpio_regs *gpio = GPIO_BASE; - - writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); - writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ - udelay(1); - writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ - udelay(200); - - return mmcif_mmc_init(); -} - -static int get_sh_eth_mac_raw(unsigned char *buf, int size) -{ -#ifdef CONFIG_DEPRECATED - struct spi_flash *spi; - int ret; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (spi == NULL) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf); - if (ret) { - printf("%s: spi_flash read failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); -#endif - - return 0; -} - -static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) -{ - memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)], - SH7753EVB_ETHERNET_MAC_SIZE); - mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ - - return 0; -} - -static void init_ethernet_mac(void) -{ - char mac_string[64]; - char env_string[64]; - int i; - unsigned char *buf; - - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return; - } - get_sh_eth_mac_raw(buf, 256); - - /* Gigabit Ethernet */ - for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i == 0) - env_set("ethaddr", mac_string); - else { - sprintf(env_string, "eth%daddr", i); - env_set(env_string, mac_string); - } - set_mac_to_sh_giga_eth_register(i, mac_string); - } - - free(buf); -} - -int board_late_init(void) -{ - init_ethernet_mac(); - - return 0; -} - -#ifdef CONFIG_DEPRECATED -int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int i, ret; - char mac_string[256]; - struct spi_flash *spi; - unsigned char *buf; - - if (argc != 3) { - buf = malloc(256); - if (!buf) { - printf("%s: malloc failed.\n", __func__); - return 1; - } - - get_sh_eth_mac_raw(buf, 256); - - /* print current MAC address */ - for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - printf("GETHERC ch%d = %s\n", i, mac_string); - } - free(buf); - return 0; - } - - /* new setting */ - memset(mac_string, 0xff, sizeof(mac_string)); - sprintf(mac_string, "%s\t%s", - argv[1], argv[2]); - - /* write MAC data to SPI rom */ - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe failed.\n", __func__); - return 1; - } - - ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, - SH7753EVB_SPI_SECTOR_SIZE); - if (ret) { - printf("%s: spi_flash erase failed.\n", __func__); - return 1; - } - - ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI, - sizeof(mac_string), mac_string); - if (ret) { - printf("%s: spi_flash write failed.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - puts("The writing of the MAC address to SPI ROM was completed.\n"); - - return 0; -} - -U_BOOT_CMD( - write_mac, 3, 1, do_write_mac, - "write MAC address for GETHERC", - "[GETHERC ch0] [GETHERC ch1]\n" -); -#endif diff --git a/board/renesas/sh7753evb/spi-boot.c b/board/renesas/sh7753evb/spi-boot.c deleted file mode 100644 index 243c6f6e883d..000000000000 --- a/board/renesas/sh7753evb/spi-boot.c +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Renesas Solutions Corp. - */ - -#include <common.h> - -#define CONFIG_SPI_ADDR 0x00000000 -#define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000) -#define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE) - -#define SPIWDMADR 0xFE001018 -#define SPIWDMCNTR 0xFE001020 -#define SPIDMCOR 0xFE001028 -#define SPIDMINTSR 0xFE001188 -#define SPIDMINTMR 0xFE001190 - -#define SPIDMINTSR_DMEND 0x00000004 - -#define TBR 0xFE002000 -#define RBR 0xFE002000 - -#define CR1 0xFE002008 -#define CR2 0xFE002010 -#define CR3 0xFE002018 -#define CR4 0xFE002020 -#define CR7 0xFE002038 -#define CR8 0xFE002040 - -/* CR1 */ -#define SPI_TBE 0x80 -#define SPI_TBF 0x40 -#define SPI_RBE 0x20 -#define SPI_RBF 0x10 -#define SPI_PFONRD 0x08 -#define SPI_SSDB 0x04 -#define SPI_SSD 0x02 -#define SPI_SSA 0x01 - -/* CR2 */ -#define SPI_RSTF 0x80 -#define SPI_LOOPBK 0x40 -#define SPI_CPOL 0x20 -#define SPI_CPHA 0x10 -#define SPI_L1M0 0x08 - -/* CR4 */ -#define SPI_TBEI 0x80 -#define SPI_TBFI 0x40 -#define SPI_RBEI 0x20 -#define SPI_RBFI 0x10 -#define SPI_SpiS0 0x02 -#define SPI_SSS 0x01 - -/* CR7 */ -#define CR7_IDX_OR12 0x12 -#define OR12_ADDR32 0x00000001 - -#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val -#define spi_read(addr) (*(volatile unsigned long *)(addr)) - -/* M25P80 */ -#define M25_READ 0x03 -#define M25_READ_4BYTE 0x13 - -extern void bss_start(void); - -#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) -static void __uses_spiboot2 spi_reset(void) -{ - int timeout = 0x00100000; - - /* Make sure the last transaction is finalized */ - spi_write(0x00, CR3); - spi_write(0x02, CR1); - while (!(spi_read(CR4) & SPI_SpiS0)) { - if (timeout-- < 0) - break; - } - spi_write(0x00, CR1); - - spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ - spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); - - spi_write(0, SPIDMCOR); -} - -static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, - unsigned long len) -{ - spi_write(CR7_IDX_OR12, CR7); - if (spi_read(CR8) & OR12_ADDR32) { - /* 4-bytes address mode */ - spi_write(M25_READ_4BYTE, TBR); - spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */ - } else { - /* 3-bytes address mode */ - spi_write(M25_READ, TBR); - } - spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */ - spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */ - spi_write(addr & 0xFF, TBR); /* ADDR7-0 */ - - spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); - spi_write((unsigned long)buf, SPIWDMADR); - spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); - spi_write(1, SPIDMCOR); - - spi_write(0xff, CR3); - spi_write(spi_read(CR1) | SPI_SSDB, CR1); - spi_write(spi_read(CR1) | SPI_SSA, CR1); - - while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) - ; - - /* Nagate SP0-SS0 */ - spi_write(0, CR1); -} - -void __uses_spiboot2 spiboot_main(void) -{ - /* - * This code rounds len up for SPIWDMCNTR. We should set it to 0 in - * lower 5-bits. - */ - void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; - volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0; - - spi_reset(); - spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len); - - _start(); -} diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig deleted file mode 100644 index c1996607a051..000000000000 --- a/configs/sh7753evb_defconfig +++ /dev/null @@ -1,38 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x5ff80000 -CONFIG_ENV_SIZE=0x10000 -CONFIG_TARGET_SH7753EVB=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC2,115200 root=/dev/nfs ip=dhcp" -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_MD5SUM=y -# CONFIG_CMD_LOADB is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_EXT2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MMC=y -CONFIG_SH_MMCIF=y -CONFIG_BITBANGMII=y -CONFIG_PHY_VITESSE=y -CONFIG_SH_ETHER=y -CONFIG_SCIF_CONSOLE=y -CONFIG_SPI=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 08c167b6b53d..a70d2de19de8 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -18,7 +18,6 @@ Board-specific doc intel/index kontron/index microchip/index - renesas/index rockchip/index sifive/index sipeed/index diff --git a/doc/board/renesas/index.rst b/doc/board/renesas/index.rst deleted file mode 100644 index 401ffcf61b25..000000000000 --- a/doc/board/renesas/index.rst +++ /dev/null @@ -1,9 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ - -Renesas -======= - -.. toctree:: - :maxdepth: 2 - - sh7753evb diff --git a/doc/board/renesas/sh7753evb.rst b/doc/board/renesas/sh7753evb.rst deleted file mode 100644 index c62a82435cbd..000000000000 --- a/doc/board/renesas/sh7753evb.rst +++ /dev/null @@ -1,79 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ - -SH7753 EVB board -================ - -This board specification ------------------------- - -The SH7753 EVB (board config name:sh7753evb) has the following device: - - - SH7753 (SH-4A) - - DDR3-SDRAM 512MB - - SPI ROM 8MB - - Gigabit Ethernet controllers - - eMMC 4GB - - -Configuration for This board ----------------------------- - -You can select the configuration as follows: - - - make sh7753evb_config - - -This board specific command ---------------------------- - -This board has the following its specific command: - -write_mac: - You can write MAC address to SPI ROM. - -Usage 1: Write MAC address - -.. code-block:: none - - write_mac [GETHERC ch0] [GETHERC ch1] - - For example: - => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f - -* We have to input the command as a single line (without carriage return) -* We have to reset after input the command. - -Usage 2: Show current data - -.. code-block:: none - - write_mac - - For example: - => write_mac - GETHERC ch0 = 74:90:50:00:33:9e - GETHERC ch1 = 74:90:50:00:33:9f - - -Update SPI ROM --------------- - -1. Copy u-boot image to RAM area. -2. Probe SPI device. - -.. code-block:: none - - => sf probe 0 - SF: Detected MX25L6405D with page size 64KiB, total 8 MiB - -3. Erase SPI ROM. - -.. code-block:: none - - => sf erase 0 80000 - -4. Write u-boot image to SPI ROM. - -.. code-block:: none - - => sf write 0x48000000 0 80000 diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h deleted file mode 100644 index 736b379ab7a1..000000000000 --- a/include/configs/sh7753evb.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the sh7753evb board - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __SH7753EVB_H -#define __SH7753EVB_H - -#define CONFIG_CPU_SH7753 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* MEMORY */ -#define SH7753EVB_SDRAM_BASE (0x40000000) -#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_CONS_SCIF2 1 - -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ - 128 * 1024 * 1024) - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 18 -#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 -#define CONFIG_SH_ETHER_USE_GETHER 1 -#define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII - -#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000 -#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024) -#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI -#define SH7753EVB_ETHERNET_MAC_SIZE 17 -#define SH7753EVB_ETHERNET_NUM_CH 2 - -/* SPI */ -#define CONFIG_SH_SPI_BASE 0xfe002000 - -/* MMCIF */ -#define CONFIG_SH_MMCIF_ADDR 0xffcb0000 -#define CONFIG_SH_MMCIF_CLK 48000000 - -/* ENV setting */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netboot=bootp; bootm\0" - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 48000000 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ -#endif /* __SH7753EVB_H */
On Wed, Feb 10, 2021 at 12:51:24PM -0500, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
As this is the last SH4A board, remove that support as well.
Cc: Marek Vasut marek.vasut+renesas@gmail.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/sh/Kconfig | 18 - arch/sh/include/asm/cpu_sh4.h | 25 -- arch/sh/include/asm/system.h | 23 - arch/sh/include/asm/unaligned-sh4a.h | 258 ----------- arch/sh/include/asm/unaligned.h | 7 +- board/renesas/sh7757lcr/Kconfig | 12 - board/renesas/sh7757lcr/MAINTAINERS | 6 - board/renesas/sh7757lcr/Makefile | 7 - board/renesas/sh7757lcr/README.sh7757lcr | 77 ---- board/renesas/sh7757lcr/lowlevel_init.S | 544 ----------------------- board/renesas/sh7757lcr/sh7757lcr.c | 433 ------------------ board/renesas/sh7757lcr/spi-boot.c | 108 ----- configs/sh7757lcr_defconfig | 40 -- drivers/net/sh_eth.h | 4 - include/configs/sh7757lcr.h | 78 ---- 15 files changed, 1 insertion(+), 1639 deletions(-) delete mode 100644 arch/sh/include/asm/unaligned-sh4a.h delete mode 100644 board/renesas/sh7757lcr/Kconfig delete mode 100644 board/renesas/sh7757lcr/MAINTAINERS delete mode 100644 board/renesas/sh7757lcr/Makefile delete mode 100644 board/renesas/sh7757lcr/README.sh7757lcr delete mode 100644 board/renesas/sh7757lcr/lowlevel_init.S delete mode 100644 board/renesas/sh7757lcr/sh7757lcr.c delete mode 100644 board/renesas/sh7757lcr/spi-boot.c delete mode 100644 configs/sh7757lcr_defconfig delete mode 100644 include/configs/sh7757lcr.h
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index d8d2a7ffe9d0..2e9ccf7632a6 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -4,19 +4,6 @@ menu "SuperH architecture" config CPU_SH4 bool
-config CPU_SH4A - bool - select CPU_SH4 - -config SH_32BIT - bool "32bit mode" - depends on CPU_SH4A - default n - help - SH4A has 2 physical memory maps. This use 32bit mode. - And this is board specific. Please check your board if you - want to use this. - choice prompt "Target select" optional @@ -25,10 +12,6 @@ config TARGET_R2DPLUS bool "Renesas R2D-PLUS" select CPU_SH4
-config TARGET_SH7757LCR - bool "SH7757LCR" - select CPU_SH4A - config TARGET_SH7763RDP bool "SH7763RDP" select CPU_SH4 @@ -44,7 +27,6 @@ config SYS_CPU source "arch/sh/lib/Kconfig"
source "board/renesas/r2dplus/Kconfig" -source "board/renesas/sh7757lcr/Kconfig" source "board/renesas/sh7763rdp/Kconfig"
endmenu diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index 5fc9c962d833..ed7c243b3bda 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -46,29 +46,4 @@ # error "Unknown SH4 variant" #endif
-#if defined(CONFIG_SH_32BIT) -#define PMB_ADDR_ARRAY 0xf6100000 -#define PMB_ADDR_ENTRY 8 -#define PMB_VPN 24 - -#define PMB_DATA_ARRAY 0xf7100000 -#define PMB_DATA_ENTRY 8 -#define PMB_PPN 24 -#define PMB_UB 9 /* Buffered write */ -#define PMB_V 8 /* Valid */ -#define PMB_SZ1 7 /* Page size (upper bit) */ -#define PMB_SZ0 4 /* Page size (lower bit) */ -#define PMB_C 3 /* Cacheability */ -#define PMB_WT 0 /* Write-through */ - -#define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY)) -#define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY)) -#define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN)) -#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \ - ((ppn << PMB_PPN) | (ub << PMB_UB) | \ - (v << PMB_V) | (sz1 << PMB_SZ1) | \ - (sz0 << PMB_SZ0) | (c << PMB_C) | \ - (wt << PMB_WT)) -#endif - #endif /* _ASM_CPU_SH4_H_ */ diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h index 24b5ce8e3042..ccc79b3c9177 100644 --- a/arch/sh/include/asm/system.h +++ b/arch/sh/include/asm/system.h @@ -70,18 +70,6 @@ static inline void sched_cacheflush(void) { }
-#ifdef CONFIG_CPU_SH4A -#define __icbi() \ -{ \ - unsigned long __addr; \ - __addr = 0xa8000000; \ - __asm__ __volatile__( \ - "icbi %0\n\t" \ - : /* no output */ \ - : "m" (__m(__addr))); \ -} -#endif - static inline unsigned long tas(volatile int *m) { unsigned long retval; @@ -100,25 +88,14 @@ static inline unsigned long tas(volatile int *m) * effect. On newer cores (like the sh4a and sh5) this is accomplished * with icbi. * - * Also note that on sh4a in the icbi case we can forego a synco for the - * write barrier, as it's not necessary for control registers. - * * Historically we have only done this type of barrier for the MMUCR, but * it's also necessary for the CCR, so we make it generic here instead. */ -#ifdef CONFIG_CPU_SH4A -#define mb() __asm__ __volatile__ ("synco": : :"memory") -#define rmb() mb() -#define wmb() __asm__ __volatile__ ("synco": : :"memory") -#define ctrl_barrier() __icbi() -#define read_barrier_depends() do { } while(0) -#else #define mb() __asm__ __volatile__ ("": : :"memory") #define rmb() mb() #define wmb() __asm__ __volatile__ ("": : :"memory") #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") #define read_barrier_depends() do { } while(0) -#endif
#ifdef CONFIG_SMP #define smp_mb() mb() diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h deleted file mode 100644 index 9f4dd252c981..000000000000 --- a/arch/sh/include/asm/unaligned-sh4a.h +++ /dev/null @@ -1,258 +0,0 @@ -#ifndef __ASM_SH_UNALIGNED_SH4A_H -#define __ASM_SH_UNALIGNED_SH4A_H - -/* - * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only. - * Support for 64-bit accesses are done through shifting and masking - * relative to the endianness. Unaligned stores are not supported by the - * instruction encoding, so these continue to use the packed - * struct. - * - * The same note as with the movli.l/movco.l pair applies here, as long - * as the load is gauranteed to be inlined, nothing else will hook in to - * r0 and we get the return value for free. - * - * NOTE: Due to the fact we require r0 encoding, care should be taken to - * avoid mixing these heavily with other r0 consumers, such as the atomic - * ops. Failure to adhere to this can result in the compiler running out - * of spill registers and blowing up when building at low optimization - * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777. - */ -#include <linux/types.h> -#include <asm/byteorder.h> - -static __always_inline u32 __get_unaligned_cpu32(const u8 *p) -{ - unsigned long unaligned; - - __asm__ __volatile__ ( - "movua.l @%1, %0\n\t" - : "=z" (unaligned) - : "r" (p) - ); - - return unaligned; -} - -struct __una_u16 { u16 x __attribute__((packed)); }; -struct __una_u32 { u32 x __attribute__((packed)); }; -struct __una_u64 { u64 x __attribute__((packed)); }; - -static inline u16 __get_unaligned_cpu16(const u8 *p) -{ -#ifdef __LITTLE_ENDIAN - return p[0] | p[1] << 8; -#else - return p[0] << 8 | p[1]; -#endif -} - -/* - * Even though movua.l supports auto-increment on the read side, it can - * only store to r0 due to instruction encoding constraints, so just let - * the compiler sort it out on its own. - */ -static inline u64 __get_unaligned_cpu64(const u8 *p) -{ -#ifdef __LITTLE_ENDIAN - return (u64)__get_unaligned_cpu32(p + 4) << 32 | - __get_unaligned_cpu32(p); -#else - return (u64)__get_unaligned_cpu32(p) << 32 | - __get_unaligned_cpu32(p + 4); -#endif -} - -static inline u16 get_unaligned_le16(const void *p) -{ - return le16_to_cpu(__get_unaligned_cpu16(p)); -} - -static inline u32 get_unaligned_le32(const void *p) -{ - return le32_to_cpu(__get_unaligned_cpu32(p)); -} - -static inline u64 get_unaligned_le64(const void *p) -{ - return le64_to_cpu(__get_unaligned_cpu64(p)); -} - -static inline u16 get_unaligned_be16(const void *p) -{ - return be16_to_cpu(__get_unaligned_cpu16(p)); -} - -static inline u32 get_unaligned_be32(const void *p) -{ - return be32_to_cpu(__get_unaligned_cpu32(p)); -} - -static inline u64 get_unaligned_be64(const void *p) -{ - return be64_to_cpu(__get_unaligned_cpu64(p)); -} - -static inline void __put_le16_noalign(u8 *p, u16 val) -{ - *p++ = val; - *p++ = val >> 8; -} - -static inline void __put_le32_noalign(u8 *p, u32 val) -{ - __put_le16_noalign(p, val); - __put_le16_noalign(p + 2, val >> 16); -} - -static inline void __put_le64_noalign(u8 *p, u64 val) -{ - __put_le32_noalign(p, val); - __put_le32_noalign(p + 4, val >> 32); -} - -static inline void __put_be16_noalign(u8 *p, u16 val) -{ - *p++ = val >> 8; - *p++ = val; -} - -static inline void __put_be32_noalign(u8 *p, u32 val) -{ - __put_be16_noalign(p, val >> 16); - __put_be16_noalign(p + 2, val); -} - -static inline void __put_be64_noalign(u8 *p, u64 val) -{ - __put_be32_noalign(p, val >> 32); - __put_be32_noalign(p + 4, val); -} - -static inline void put_unaligned_le16(u16 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - ((struct __una_u16 *)p)->x = val; -#else - __put_le16_noalign(p, val); -#endif -} - -static inline void put_unaligned_le32(u32 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - ((struct __una_u32 *)p)->x = val; -#else - __put_le32_noalign(p, val); -#endif -} - -static inline void put_unaligned_le64(u64 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - ((struct __una_u64 *)p)->x = val; -#else - __put_le64_noalign(p, val); -#endif -} - -static inline void put_unaligned_be16(u16 val, void *p) -{ -#ifdef __BIG_ENDIAN - ((struct __una_u16 *)p)->x = val; -#else - __put_be16_noalign(p, val); -#endif -} - -static inline void put_unaligned_be32(u32 val, void *p) -{ -#ifdef __BIG_ENDIAN - ((struct __una_u32 *)p)->x = val; -#else - __put_be32_noalign(p, val); -#endif -} - -static inline void put_unaligned_be64(u64 val, void *p) -{ -#ifdef __BIG_ENDIAN - ((struct __una_u64 *)p)->x = val; -#else - __put_be64_noalign(p, val); -#endif -} - -/* - * Cause a link-time error if we try an unaligned access other than - * 1,2,4 or 8 bytes long - */ -extern void __bad_unaligned_access_size(void); - -#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({ \ - __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \ - __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)), \ - __bad_unaligned_access_size())))); \ - })) - -#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({ \ - __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \ - __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)), \ - __bad_unaligned_access_size())))); \ - })) - -#define __put_unaligned_le(val, ptr) ({ \ - void *__gu_p = (ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: \ - *(u8 *)__gu_p = (__force u8)(val); \ - break; \ - case 2: \ - put_unaligned_le16((__force u16)(val), __gu_p); \ - break; \ - case 4: \ - put_unaligned_le32((__force u32)(val), __gu_p); \ - break; \ - case 8: \ - put_unaligned_le64((__force u64)(val), __gu_p); \ - break; \ - default: \ - __bad_unaligned_access_size(); \ - break; \ - } \ - (void)0; }) - -#define __put_unaligned_be(val, ptr) ({ \ - void *__gu_p = (ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: \ - *(u8 *)__gu_p = (__force u8)(val); \ - break; \ - case 2: \ - put_unaligned_be16((__force u16)(val), __gu_p); \ - break; \ - case 4: \ - put_unaligned_be32((__force u32)(val), __gu_p); \ - break; \ - case 8: \ - put_unaligned_be64((__force u64)(val), __gu_p); \ - break; \ - default: \ - __bad_unaligned_access_size(); \ - break; \ - } \ - (void)0; }) - -#ifdef __LITTLE_ENDIAN -# define get_unaligned __get_unaligned_le -# define put_unaligned __put_unaligned_le -#else -# define get_unaligned __get_unaligned_be -# define put_unaligned __put_unaligned_be -#endif - -#endif /* __ASM_SH_UNALIGNED_SH4A_H */ diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h index 06096eeac574..5acf0819620e 100644 --- a/arch/sh/include/asm/unaligned.h +++ b/arch/sh/include/asm/unaligned.h @@ -3,11 +3,7 @@
/* Copy from linux-kernel. */
-#ifdef CONFIG_CPU_SH4A -/* SH-4A can handle unaligned loads in a relatively neutered fashion. */ -#include <asm/unaligned-sh4a.h> -#else -/* Otherwise, SH can't handle unaligned accesses. */ +/* Other than SH4A, SH can't handle unaligned accesses. */ #include <linux/compiler.h> #if defined(__BIG_ENDIAN__) #define get_unaligned __get_unaligned_be @@ -20,6 +16,5 @@ #include <linux/unaligned/le_byteshift.h> #include <linux/unaligned/be_byteshift.h> #include <linux/unaligned/generic.h> -#endif
#endif /* _ASM_SH_UNALIGNED_H */ diff --git a/board/renesas/sh7757lcr/Kconfig b/board/renesas/sh7757lcr/Kconfig deleted file mode 100644 index 3fba80ddcab2..000000000000 --- a/board/renesas/sh7757lcr/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SH7757LCR - -config SYS_BOARD - default "sh7757lcr" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "sh7757lcr" - -endif diff --git a/board/renesas/sh7757lcr/MAINTAINERS b/board/renesas/sh7757lcr/MAINTAINERS deleted file mode 100644 index 20aca678a672..000000000000 --- a/board/renesas/sh7757lcr/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SH7757LCR BOARD -#M: - -S: Maintained -F: board/renesas/sh7757lcr/ -F: include/configs/sh7757lcr.h -F: configs/sh7757lcr_defconfig diff --git a/board/renesas/sh7757lcr/Makefile b/board/renesas/sh7757lcr/Makefile deleted file mode 100644 index ed3be4b6ab64..000000000000 --- a/board/renesas/sh7757lcr/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com -# - -obj-y := sh7757lcr.o spi-boot.o -extra-y += lowlevel_init.o diff --git a/board/renesas/sh7757lcr/README.sh7757lcr b/board/renesas/sh7757lcr/README.sh7757lcr deleted file mode 100644 index 9453839d2ce0..000000000000 --- a/board/renesas/sh7757lcr/README.sh7757lcr +++ /dev/null @@ -1,77 +0,0 @@ -======================================== -Renesas R0P7757LC0030RL board -======================================== - -This board specification: -========================= - -The R0P7757LC0030RL(board config name:sh7757lcr) has the following device: - - - SH7757 (SH-4A) - - DDR3-SDRAM 256MB (with ECC) - - SPI ROM 8MB - - 2D Graphic controller - - Ethernet controller - - eMMC 2GB - - -configuration for This board: -============================= - -You can select the configuration as follows: - - - make sh7757lcr_config - - -This board specific command: -============================ - -This board has the following its specific command: - - - sh_g200 - - write_mac - - -1. sh_g200 - -If we run this command, SH4 can control the G200. -The default setting is that SH4 cannot control the G200. - - -2. write_mac - -You can write MAC address to SPI ROM. - - Usage 1) Write MAC address - - write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1] - - For example) - => write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83 - *) We have to input the command as a single line - (without carriage return) - *) We have to reset after input the command. - - Usage 2) Show current data - - write_mac - - For example) - => write_mac - ETHERC ch0 = 00:00:87:6c:21:80 - ETHERC ch1 = 00:00:87:6c:21:81 - GETHERC ch0 = 00:00:87:6c:21:82 - GETHERC ch1 = 00:00:87:6c:21:83 - - -Update SPI ROM: -============================ - -1. Copy u-boot image to RAM area. -2. Probe SPI device. - => sf probe 0 - 8192 KiB M25P64 at 0:0 is now current device -3. Erase SPI ROM. - => sf erase 0 80000 -4. Write u-boot image to SPI ROM. - => sf write 0x89000000 0 80000 diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S deleted file mode 100644 index ee288f807f5e..000000000000 --- a/board/renesas/sh7757lcr/lowlevel_init.S +++ /dev/null @@ -1,544 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - */ - -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -.macro or32, addr, data - mov.l \addr, r1 - mov.l \data, r0 - mov.l @r1, r2 - or r2, r0 - mov.l r0, @r1 -.endm - -.macro wait_DBCMD - mov.l DBWAIT_A, r0 - mov.l @r0, r1 -.endm - - .global lowlevel_init - .section .spiboot1.text - .align 2 - -lowlevel_init: - - /*------- GPIO -------*/ - write8 PGDR_A, PGDR_D /* eMMC power off */ - - write16 PACR_A, PACR_D - write16 PBCR_A, PBCR_D - write16 PCCR_A, PCCR_D - write16 PDCR_A, PDCR_D - write16 PECR_A, PECR_D - write16 PFCR_A, PFCR_D - write16 PGCR_A, PGCR_D - write16 PHCR_A, PHCR_D - write16 PICR_A, PICR_D - write16 PJCR_A, PJCR_D - write16 PKCR_A, PKCR_D - write16 PLCR_A, PLCR_D - write16 PMCR_A, PMCR_D - write16 PNCR_A, PNCR_D - write16 POCR_A, POCR_D - write16 PQCR_A, PQCR_D - write16 PRCR_A, PRCR_D - write16 PSCR_A, PSCR_D - write16 PTCR_A, PTCR_D - write16 PUCR_A, PUCR_D - write16 PVCR_A, PVCR_D - write16 PWCR_A, PWCR_D - write16 PXCR_A, PXCR_D - write16 PYCR_A, PYCR_D - write16 PZCR_A, PZCR_D - write16 PSEL0_A, PSEL0_D - write16 PSEL1_A, PSEL1_D - write16 PSEL2_A, PSEL2_D - write16 PSEL3_A, PSEL3_D - write16 PSEL4_A, PSEL4_D - write16 PSEL5_A, PSEL5_D - write16 PSEL6_A, PSEL6_D - write16 PSEL7_A, PSEL7_D - write16 PSEL8_A, PSEL8_D - - bra exit_gpio - nop - - .align 4 - -/*------- GPIO -------*/ -PGDR_A: .long 0xffec0040 -PACR_A: .long 0xffec0000 -PBCR_A: .long 0xffec0002 -PCCR_A: .long 0xffec0004 -PDCR_A: .long 0xffec0006 -PECR_A: .long 0xffec0008 -PFCR_A: .long 0xffec000a -PGCR_A: .long 0xffec000c -PHCR_A: .long 0xffec000e -PICR_A: .long 0xffec0010 -PJCR_A: .long 0xffec0012 -PKCR_A: .long 0xffec0014 -PLCR_A: .long 0xffec0016 -PMCR_A: .long 0xffec0018 -PNCR_A: .long 0xffec001a -POCR_A: .long 0xffec001c -PQCR_A: .long 0xffec0020 -PRCR_A: .long 0xffec0022 -PSCR_A: .long 0xffec0024 -PTCR_A: .long 0xffec0026 -PUCR_A: .long 0xffec0028 -PVCR_A: .long 0xffec002a -PWCR_A: .long 0xffec002c -PXCR_A: .long 0xffec002e -PYCR_A: .long 0xffec0030 -PZCR_A: .long 0xffec0032 -PSEL0_A: .long 0xffec0070 -PSEL1_A: .long 0xffec0072 -PSEL2_A: .long 0xffec0074 -PSEL3_A: .long 0xffec0076 -PSEL4_A: .long 0xffec0078 -PSEL5_A: .long 0xffec007a -PSEL6_A: .long 0xffec007c -PSEL7_A: .long 0xffec0082 -PSEL8_A: .long 0xffec0084 - -PGDR_D: .long 0x80 -PACR_D: .long 0x0000 -PBCR_D: .long 0x0001 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PFCR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x0000 -PICR_D: .long 0x0000 -PJCR_D: .long 0x0000 -PKCR_D: .long 0x0003 -PLCR_D: .long 0x0000 -PMCR_D: .long 0x0000 -PNCR_D: .long 0x0000 -POCR_D: .long 0x0000 -PQCR_D: .long 0xc000 -PRCR_D: .long 0x0000 -PSCR_D: .long 0x0000 -PTCR_D: .long 0x0000 -#if defined(CONFIG_SH7757_OFFSET_SPI) -PUCR_D: .long 0x0055 -#else -PUCR_D: .long 0x0000 -#endif -PVCR_D: .long 0x0000 -PWCR_D: .long 0x0000 -PXCR_D: .long 0x0000 -PYCR_D: .long 0x0000 -PZCR_D: .long 0x0000 -PSEL0_D: .long 0xfe00 -PSEL1_D: .long 0x0000 -PSEL2_D: .long 0x3000 -PSEL3_D: .long 0xff00 -PSEL4_D: .long 0x771f -PSEL5_D: .long 0x0ffc -PSEL6_D: .long 0x00ff -PSEL7_D: .long 0xfc00 -PSEL8_D: .long 0x0000 - - .align 2 - -exit_gpio: - mov #0, r14 - mova 2f, r0 - mov.l PC_MASK, r1 - tst r0, r1 - bf 2f - - bra exit_pmb - nop - - .align 2 - -/* If CPU runs on SDRAM, PC is 0x8???????. */ -PC_MASK: .long 0x20000000 - -2: - mov #1, r14 - - mov.l EXPEVT_A, r0 - mov.l @r0, r0 - mov.l EXPEVT_POWER_ON_RESET, r1 - cmp/eq r0, r1 - bt 1f - - /* - * If EXPEVT value is manual reset or tlb multipul-hit, - * initialization of DDR3IF is not necessary. - */ - bra exit_ddr - nop - -1: - /* For Core Reset */ - mov.l DBACEN_A, r0 - mov.l @r0, r0 - cmp/eq #0, r0 - bt 3f - - /* - * If DBACEN == 1(DBSC was already enabled), we have to avoid the - * initialization of DDR3-SDRAM. - */ - bra exit_ddr - nop - -3: - /*------- DDR3IF -------*/ - /* oscillation stabilization time */ - wait_timer WAIT_OSC_TIME - - /* step 3 */ - write32 DBCMD_A, DBCMD_RSTL_VAL - wait_timer WAIT_30US - - /* step 4 */ - write32 DBCMD_A, DBCMD_PDEN_VAL - - /* step 5 */ - write32 DBKIND_A, DBKIND_D - - /* step 6 */ - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBTR4_A, DBTR4_D - write32 DBTR5_A, DBTR5_D - write32 DBTR6_A, DBTR6_D - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D - write32 DBTR13_A, DBTR13_D - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D - write32 DBTR17_A, DBTR17_D - write32 DBTR18_A, DBTR18_D - write32 DBTR19_A, DBTR19_D - write32 DBRNK0_A, DBRNK0_D - - /* step 7 */ - write32 DBPDCNT3_A, DBPDCNT3_D - - /* step 8 */ - write32 DBPDCNT1_A, DBPDCNT1_D - write32 DBPDCNT2_A, DBPDCNT2_D - write32 DBPDLCK_A, DBPDLCK_D - write32 DBPDRGA_A, DBPDRGA_D - write32 DBPDRGD_A, DBPDRGD_D - - /* step 9 */ - wait_timer WAIT_30US - - /* step 10 */ - write32 DBPDCNT0_A, DBPDCNT0_D - - /* step 11 */ - wait_timer WAIT_30US - wait_timer WAIT_30US - - /* step 12 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - wait_DBCMD - - /* step 13 */ - write32 DBCMD_A, DBCMD_RSTH_VAL - wait_DBCMD - - /* step 14 */ - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - write32 DBCMD_A, DBCMD_WAIT_VAL - - /* step 15 */ - write32 DBCMD_A, DBCMD_PDXT_VAL - - /* step 16 */ - write32 DBCMD_A, DBCMD_MRS2_VAL - - /* step 17 */ - write32 DBCMD_A, DBCMD_MRS3_VAL - - /* step 18 */ - write32 DBCMD_A, DBCMD_MRS1_VAL - - /* step 19 */ - write32 DBCMD_A, DBCMD_MRS0_VAL - - /* step 20 */ - write32 DBCMD_A, DBCMD_ZQCL_VAL - - write32 DBCMD_A, DBCMD_REF_VAL - write32 DBCMD_A, DBCMD_REF_VAL - wait_DBCMD - - /* step 21 */ - write32 DBADJ0_A, DBADJ0_D - write32 DBADJ1_A, DBADJ1_D - write32 DBADJ2_A, DBADJ2_D - - /* step 22 */ - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D - write32 DBRFCNF2_A, DBRFCNF2_D - - /* step 23 */ - write32 DBCALCNF_A, DBCALCNF_D - - /* step 24 */ - write32 DBRFEN_A, DBRFEN_D - write32 DBCMD_A, DBCMD_SRXT_VAL - - /* step 25 */ - write32 DBACEN_A, DBACEN_D - - /* step 26 */ - wait_DBCMD - -#if defined(CONFIG_SH7757LCR_DDR_ECC) - /* enable DDR-ECC */ - write32 ECD_ECDEN_A, ECD_ECDEN_D - write32 ECD_INTSR_A, ECD_INTSR_D - write32 ECD_SPACER_A, ECD_SPACER_D - write32 ECD_MCR_A, ECD_MCR_D -#endif - bra exit_ddr - nop - - .align 4 - -EXPEVT_A: .long 0xff000024 -EXPEVT_POWER_ON_RESET: .long 0x00000000 - -/*------- DDR3IF -------*/ -DBCMD_A: .long 0xfe800018 -DBKIND_A: .long 0xfe800020 -DBCONF_A: .long 0xfe800024 -DBTR0_A: .long 0xfe800040 -DBTR1_A: .long 0xfe800044 -DBTR2_A: .long 0xfe800048 -DBTR3_A: .long 0xfe800050 -DBTR4_A: .long 0xfe800054 -DBTR5_A: .long 0xfe800058 -DBTR6_A: .long 0xfe80005c -DBTR7_A: .long 0xfe800060 -DBTR8_A: .long 0xfe800064 -DBTR9_A: .long 0xfe800068 -DBTR10_A: .long 0xfe80006c -DBTR11_A: .long 0xfe800070 -DBTR12_A: .long 0xfe800074 -DBTR13_A: .long 0xfe800078 -DBTR14_A: .long 0xfe80007c -DBTR15_A: .long 0xfe800080 -DBTR16_A: .long 0xfe800084 -DBTR17_A: .long 0xfe800088 -DBTR18_A: .long 0xfe80008c -DBTR19_A: .long 0xfe800090 -DBRNK0_A: .long 0xfe800100 -DBPDCNT0_A: .long 0xfe800200 -DBPDCNT1_A: .long 0xfe800204 -DBPDCNT2_A: .long 0xfe800208 -DBPDCNT3_A: .long 0xfe80020c -DBPDLCK_A: .long 0xfe800280 -DBPDRGA_A: .long 0xfe800290 -DBPDRGD_A: .long 0xfe8002a0 -DBADJ0_A: .long 0xfe8000c0 -DBADJ1_A: .long 0xfe8000c4 -DBADJ2_A: .long 0xfe8000c8 -DBRFCNF0_A: .long 0xfe8000e0 -DBRFCNF1_A: .long 0xfe8000e4 -DBRFCNF2_A: .long 0xfe8000e8 -DBCALCNF_A: .long 0xfe8000f4 -DBRFEN_A: .long 0xfe800014 -DBACEN_A: .long 0xfe800010 -DBWAIT_A: .long 0xfe80001c - -WAIT_OSC_TIME: .long 6000 -WAIT_30US: .long 13333 - -DBCMD_RSTL_VAL: .long 0x20000000 -DBCMD_PDEN_VAL: .long 0x1000d73c -DBCMD_WAIT_VAL: .long 0x0000d73c -DBCMD_RSTH_VAL: .long 0x2100d73c -DBCMD_PDXT_VAL: .long 0x110000c8 -DBCMD_MRS0_VAL: .long 0x28000930 -DBCMD_MRS1_VAL: .long 0x29000004 -DBCMD_MRS2_VAL: .long 0x2a000008 -DBCMD_MRS3_VAL: .long 0x2b000000 -DBCMD_ZQCL_VAL: .long 0x03000200 -DBCMD_REF_VAL: .long 0x0c000000 -DBCMD_SRXT_VAL: .long 0x19000000 -DBKIND_D: .long 0x00000007 -DBCONF_D: .long 0x0f030a01 -DBTR0_D: .long 0x00000007 -DBTR1_D: .long 0x00000006 -DBTR2_D: .long 0x00000000 -DBTR3_D: .long 0x00000007 -DBTR4_D: .long 0x00070007 -DBTR5_D: .long 0x0000001b -DBTR6_D: .long 0x00000014 -DBTR7_D: .long 0x00000005 -DBTR8_D: .long 0x00000015 -DBTR9_D: .long 0x00000006 -DBTR10_D: .long 0x00000008 -DBTR11_D: .long 0x00000007 -DBTR12_D: .long 0x0000000e -DBTR13_D: .long 0x00000056 -DBTR14_D: .long 0x00000006 -DBTR15_D: .long 0x00000004 -DBTR16_D: .long 0x00150002 -DBTR17_D: .long 0x000c0017 -DBTR18_D: .long 0x00000200 -DBTR19_D: .long 0x00000040 -DBRNK0_D: .long 0x00000001 -DBPDCNT0_D: .long 0x00000001 -DBPDCNT1_D: .long 0x00000001 -DBPDCNT2_D: .long 0x00000000 -DBPDCNT3_D: .long 0x00004010 -DBPDLCK_D: .long 0x0000a55a -DBPDRGA_D: .long 0x00000028 -DBPDRGD_D: .long 0x00017100 - -DBADJ0_D: .long 0x00000000 -DBADJ1_D: .long 0x00000000 -DBADJ2_D: .long 0x18061806 -DBRFCNF0_D: .long 0x000001ff -DBRFCNF1_D: .long 0x08001000 -DBRFCNF2_D: .long 0x00000000 -DBCALCNF_D: .long 0x0000ffff -DBRFEN_D: .long 0x00000001 -DBACEN_D: .long 0x00000001 - -/*------- DDR-ECC -------*/ -ECD_ECDEN_A: .long 0xffc1012c -ECD_ECDEN_D: .long 0x00000001 -ECD_INTSR_A: .long 0xfe900024 -ECD_INTSR_D: .long 0xffffffff -ECD_SPACER_A: .long 0xfe900018 -ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING -ECD_MCR_A: .long 0xfe900010 -ECD_MCR_D: .long 0x00000001 - - .align 2 -exit_ddr: - -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - */ - write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D - write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - - write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D - write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif /* if defined(CONFIG_SH_32BIT) */ - -exit_pmb: - /* CPU is running on ILRAM? */ - mov r14, r0 - tst #1, r0 - bt 1f - - mov.l _bss_start, r15 - mov.l _spiboot_main, r0 -100: bsrf r0 - nop - - .align 2 -_spiboot_main: .long (spiboot_main - (100b + 4)) -_bss_start: .long bss_start - -1: - - write32 CCR_A, CCR_D - - rts - nop - - .align 4 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) -PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) -PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) -PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) -PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) -PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) -PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) -PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) -PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) -PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) -PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) -PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) -PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) -PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) - -PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_NOT_USE_D: .long 0x00000000 - -PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) - -PASCR_A: .long 0xff000070 -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long CCR -CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c deleted file mode 100644 index e933e3e73061..000000000000 --- a/board/renesas/sh7757lcr/sh7757lcr.c +++ /dev/null @@ -1,433 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <flash.h> -#include <init.h> -#include <malloc.h> -#include <net.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmc.h> -#include <spi.h> -#include <spi_flash.h> - -int checkboard(void) -{ - puts("BOARD: R0P7757LC0030RL board\n"); - - return 0; -} - -static void init_gctrl(void) -{ - struct gctrl_regs *gctrl = GCTRL_BASE; - unsigned long graofst; - - graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; - writel(graofst | 0x20000f00, &gctrl->gracr3); -} - -static int init_pcie_bridge_from_spi(void *buf, size_t size) -{ -#ifdef CONFIG_DEPRECATED - struct spi_flash *spi; - int ret; - unsigned long pcie_addr; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe error.\n", __func__); - return 1; - } - - if (is_sh7757_b0()) - pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0; - else - pcie_addr = SH7757LCR_PCIEBRG_ADDR; - - ret = spi_flash_read(spi, pcie_addr, size, buf); - if (ret) { - printf("%s: spi_flash read error.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - return 0; -#else - printf("No SPI support so no PCIe support\n"); - return 1; -#endif -} - -static void init_pcie_bridge(void) -{ - struct pciebrg_regs *pciebrg = PCIEBRG_BASE; - struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; - int i; - unsigned char *data; - unsigned short tmp; - unsigned long pcie_size; - - if (!(readw(&pciebrg->ctrl_h8s) & 0x0001)) - return; - - if (is_sh7757_b0()) - pcie_size = SH7757LCR_PCIEBRG_SIZE_B0; - else - pcie_size = SH7757LCR_PCIEBRG_SIZE; - - data = malloc(pcie_size); - if (!data) { - printf("%s: malloc error.\n", __func__); - return; - } - if (init_pcie_bridge_from_spi(data, pcie_size)) { - free(data); - return; - } - - if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff && - data[3] == 0xff) { - free(data); - printf("%s: skipped initialization\n", __func__); - return; - } - - writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ - writew(0x0000, &pciebrg->cp_ctrl); - writew(0x0000, &pciebrg->cp_addr); - - for (i = 0; i < pcie_size; i += 2) { - tmp = (data[i] << 8) | data[i + 1]; - writew(tmp, &pciebrg->cp_data); - } - - writew(0xa500, &pciebrg->ctrl_h8s); /* start */ - if (!is_sh7757_b0()) - writel(0x00000001, &pcie_setup->pbictl3); - - free(data); -} - -static void init_usb_phy(void) -{ - struct usb_common_regs *common0 = USB0_COMMON_BASE; - struct usb_common_regs *common1 = USB1_COMMON_BASE; - struct usb0_phy_regs *phy = USB0_PHY_BASE; - struct usb1_port_regs *port = USB1_PORT_BASE; - struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; - - writew(0x0100, &phy->reset); /* set reset */ - /* port0 = USB0, port1 = USB1 */ - writew(0x0002, &phy->portsel); - writel(0x0001, &port->port1sel); /* port1 = Host */ - writew(0x0111, &phy->reset); /* clear reset */ - - writew(0x4000, &common0->suspmode); - writew(0x4000, &common1->suspmode); - -#if defined(__LITTLE_ENDIAN) - writel(0x00000000, &align->ehcidatac); - writel(0x00000000, &align->ohcidatac); -#endif -} - -static void set_mac_to_sh_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - string_to_enetaddr(mac_string, mac); - - if (!channel) - ether = ETHER0_MAC_BASE; - else - ether = ETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) -{ - struct ether_mac_regs *ether; - unsigned char mac[6]; - unsigned long val; - - string_to_enetaddr(mac_string, mac); - - if (!channel) - ether = GETHER0_MAC_BASE; - else - ether = GETHER1_MAC_BASE; - - val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; - writel(val, ðer->mahr); - val = (mac[4] << 8) | mac[5]; - writel(val, ðer->malr); -} - -/***************************************************************** - * This PMB must be set on this timing. The lowlevel_init is run on - * Area 0(phys 0x00000000), so we have to map it. - * - * The new PMB table is following: - * ent virt phys v sz c wt - * 0 0xa0000000 0x40000000 1 128M 0 1 - * 1 0xa8000000 0x48000000 1 128M 0 1 - * 2 0xb0000000 0x50000000 1 128M 0 1 - * 3 0xb8000000 0x58000000 1 128M 0 1 - * 4 0x80000000 0x40000000 1 128M 1 1 - * 5 0x88000000 0x48000000 1 128M 1 1 - * 6 0x90000000 0x50000000 1 128M 1 1 - * 7 0x98000000 0x58000000 1 128M 1 1 - */ -static void set_pmb_on_board_init(void) -{ - struct mmu_regs *mmu = MMU_BASE; - - /* clear ITLB */ - writel(0x00000004, &mmu->mmucr); - - /* delete PMB for SPIBOOT */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - /* ppn ub v s1 s0 c wt */ - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); - writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); - writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); - writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); - writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); - writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); - writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); - writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); - writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); -} - -int board_init(void) -{ - struct gether_control_regs *gether = GETHER_CONTROL_BASE; - - set_pmb_on_board_init(); - - /* enable RMII's MDIO (disable GRMII's MDIO) */ - writel(0x00030000, &gether->gbecont); - - init_gctrl(); - init_usb_phy(); - - return 0; -} - -int board_mmc_init(struct bd_info *bis) -{ - return mmcif_mmc_init(); -} - -static int get_sh_eth_mac_raw(unsigned char *buf, int size) -{ -#ifdef CONFIG_DEPRECATED - struct spi_flash *spi; - int ret; - - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (spi == NULL) { - printf("%s: spi_flash probe error.\n", __func__); - return 1; - } - - ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf); - if (ret) { - printf("%s: spi_flash read error.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); -#endif - - return 0; -} - -static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) -{ - memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)], - SH7757LCR_ETHERNET_MAC_SIZE); - mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ - - return 0; -} - -static void init_ethernet_mac(void) -{ - char mac_string[64]; - char env_string[64]; - int i; - unsigned char *buf; - - buf = malloc(256); - if (!buf) { - printf("%s: malloc error.\n", __func__); - return; - } - get_sh_eth_mac_raw(buf, 256); - - /* Fast Ethernet */ - for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i == 0) - env_set("ethaddr", mac_string); - else { - sprintf(env_string, "eth%daddr", i); - env_set(env_string, mac_string); - } - - set_mac_to_sh_eth_register(i, mac_string); - } - - /* Gigabit Ethernet */ - for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) { - get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf); - sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH); - env_set(env_string, mac_string); - - set_mac_to_sh_giga_eth_register(i, mac_string); - } - - free(buf); -} - -static void init_pcie(void) -{ - struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; - struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE; - - writel(0x00000ff2, &pcie_setup->ladmsk0); - writel(0x00000001, &pcie_setup->barmap); - writel(0xffcaa000, &pcie_setup->lad0); - writel(0x00030000, &pcie_sysbus->endictl0); - writel(0x00000003, &pcie_sysbus->endictl1); - writel(0x00000004, &pcie_setup->pbictl2); -} - -static void finish_spiboot(void) -{ - struct gctrl_regs *gctrl = GCTRL_BASE; - /* - * SH7757 B0 does not use LBSC. - * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0. - * This setting is not cleared by manual reset, So we have to set it - * to 0. - */ - writel(0x00000000, &gctrl->spibootcan); -} - -int board_late_init(void) -{ - init_ethernet_mac(); - init_pcie_bridge(); - init_pcie(); - finish_spiboot(); - - return 0; -} - -int do_sh_g200(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - struct gctrl_regs *gctrl = GCTRL_BASE; - unsigned long graofst; - - writel(0xfedcba98, &gctrl->wprotect); - graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; - writel(graofst | 0xa0000f00, &gctrl->gracr3); - - return 0; -} - -U_BOOT_CMD( - sh_g200, 1, 1, do_sh_g200, - "enable sh-g200", - "enable SH-G200 bus (disable PCIe-G200)" -); - -#ifdef CONFIG_DEPRECATED -int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int i, ret; - char mac_string[256]; - struct spi_flash *spi; - unsigned char *buf; - - if (argc != 5) { - buf = malloc(256); - if (!buf) { - printf("%s: malloc error.\n", __func__); - return 1; - } - - get_sh_eth_mac_raw(buf, 256); - - /* print current MAC address */ - for (i = 0; i < 4; i++) { - get_sh_eth_mac(i, mac_string, buf); - if (i < 2) - printf(" ETHERC ch%d = %s\n", i, mac_string); - else - printf("GETHERC ch%d = %s\n", i-2, mac_string); - } - free(buf); - return 0; - } - - /* new setting */ - memset(mac_string, 0xff, sizeof(mac_string)); - sprintf(mac_string, "%s\t%s\t%s\t%s", - argv[1], argv[2], argv[3], argv[4]); - - /* write MAC data to SPI rom */ - spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); - if (!spi) { - printf("%s: spi_flash probe error.\n", __func__); - return 1; - } - - ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, - SH7757LCR_SPI_SECTOR_SIZE); - if (ret) { - printf("%s: spi_flash erase error.\n", __func__); - return 1; - } - - ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, - sizeof(mac_string), mac_string); - if (ret) { - printf("%s: spi_flash write error.\n", __func__); - spi_flash_free(spi); - return 1; - } - spi_flash_free(spi); - - puts("The writing of the MAC address to SPI ROM was completed.\n"); - - return 0; -} - -U_BOOT_CMD( - write_mac, 5, 1, do_write_mac, - "write MAC address for ETHERC/GETHERC", - "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n" -); -#endif diff --git a/board/renesas/sh7757lcr/spi-boot.c b/board/renesas/sh7757lcr/spi-boot.c deleted file mode 100644 index 71dcf5d4454d..000000000000 --- a/board/renesas/sh7757lcr/spi-boot.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License. See the file "COPYING.LIB" in the main - * directory of this archive for more details. - */ - -#include <common.h> - -#define CONFIG_RAM_BOOT_PHYS 0x4ef80000 -#if defined(CONFIG_SH7757_OFFSET_SPI) -#define CONFIG_SPI_ADDR 0x00010000 -#else -#define CONFIG_SPI_ADDR 0x00000000 -#endif -#define CONFIG_SPI_LENGTH 0x00030000 -#define CONFIG_RAM_BOOT 0x8ef80000 - -#define SPIWDMADR 0xFE001018 -#define SPIWDMCNTR 0xFE001020 -#define SPIDMCOR 0xFE001028 -#define SPIDMINTSR 0xFE001188 -#define SPIDMINTMR 0xFE001190 - -#define SPIDMINTSR_DMEND 0x00000004 - -#define TBR 0xFE002000 -#define RBR 0xFE002000 - -#define CR1 0xFE002008 -#define CR2 0xFE002010 -#define CR3 0xFE002018 -#define CR4 0xFE002020 - -/* CR1 */ -#define SPI_TBE 0x80 -#define SPI_TBF 0x40 -#define SPI_RBE 0x20 -#define SPI_RBF 0x10 -#define SPI_PFONRD 0x08 -#define SPI_SSDB 0x04 -#define SPI_SSD 0x02 -#define SPI_SSA 0x01 - -/* CR2 */ -#define SPI_RSTF 0x80 -#define SPI_LOOPBK 0x40 -#define SPI_CPOL 0x20 -#define SPI_CPHA 0x10 -#define SPI_L1M0 0x08 - -/* CR4 */ -#define SPI_TBEI 0x80 -#define SPI_TBFI 0x40 -#define SPI_RBEI 0x20 -#define SPI_RBFI 0x10 -#define SPI_SSS 0x01 - -#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val -#define spi_read(addr) (*(volatile unsigned long *)(addr)) - -/* M25P80 */ -#define M25_READ 0x03 - -#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) -static void __uses_spiboot2 spi_reset(void) -{ - spi_write(0xfe, CR1); - - spi_write(0, SPIDMCOR); - spi_write(0x00, CR1); - - spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ - spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); -} - -static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, - unsigned long len) -{ - spi_write(M25_READ, TBR); - spi_write((addr >> 16) & 0xFF, TBR); - spi_write((addr >> 8) & 0xFF, TBR); - spi_write(addr & 0xFF, TBR); - - spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); - spi_write((unsigned long)buf, SPIWDMADR); - spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); - spi_write(1, SPIDMCOR); - - spi_write(0xff, CR3); - spi_write(spi_read(CR1) | SPI_SSDB, CR1); - spi_write(spi_read(CR1) | SPI_SSA, CR1); - - while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) - ; -} - -void __uses_spiboot2 spiboot_main(void) -{ - void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; - - spi_reset(); - spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, - CONFIG_SPI_LENGTH); - - _start(); -} diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig deleted file mode 100644 index 4e5bfea8bbcd..000000000000 --- a/configs/sh7757lcr_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x8ef80000 -CONFIG_ENV_SIZE=0x10000 -CONFIG_SH_32BIT=y -CONFIG_TARGET_SH7757LCR=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC2,115200 root=/dev/nfs ip=dhcp" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_MD5SUM=y -# CONFIG_CMD_LOADB is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_EXT2=y -CONFIG_MAC_PARTITION=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_VERSION_VARIABLE=y -CONFIG_MMC=y -CONFIG_SH_MMCIF=y -CONFIG_BITBANGMII=y -CONFIG_SH_ETHER=y -CONFIG_SCIF_CONSOLE=y -CONFIG_SPI=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index d197dfdc4015..520f7f732574 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -18,11 +18,7 @@ #define ADDR_TO_P2(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0xa0000000))
/* The ethernet controller needs to use physical addresses */ -#if defined(CONFIG_SH_32BIT) -#define ADDR_TO_PHY(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0x40000000)) -#else #define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000) -#endif #elif defined(CONFIG_ARM) #ifndef inl #define inl readl diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h deleted file mode 100644 index 7067ad13bde4..000000000000 --- a/include/configs/sh7757lcr.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the sh7757lcr board - * - * Copyright (C) 2011 Renesas Solutions Corp. - */ - -#ifndef __SH7757LCR_H -#define __SH7757LCR_H - -#define CONFIG_CPU_SH7757 1 -#define CONFIG_SH7757LCR_DDR_ECC 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* MEMORY */ -#define SH7757LCR_SDRAM_BASE (0x80000000) -#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) -#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ -#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_CONS_SCIF2 1 - -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 + 16) * 1024 * 1024) - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 1 -#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 -#define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII - -#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 -#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) -#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI -#define SH7757LCR_ETHERNET_MAC_SIZE 17 -#define SH7757LCR_ETHERNET_NUM_CH 2 - -/* Gigabit Ether */ -#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 - -/* SPI */ -#define CONFIG_SH_SPI_BASE 0xfe002000 - -/* MMCIF */ -#define CONFIG_SH_MMCIF_ADDR 0xffcb0000 -#define CONFIG_SH_MMCIF_CLK 48000000 - -/* SH7757 board */ -#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 -#define SH7757LCR_GRA_OFFSET 0x1f000000 -#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 -#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) -#define SH7757LCR_PCIEBRG_ADDR 0x00090000 -#define SH7757LCR_PCIEBRG_SIZE (96 * 1024) - -/* ENV setting */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netboot=bootp; bootm\0" - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 48000000 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ -#endif /* __SH7757LCR_H */
On Wed, Feb 10, 2021 at 12:51:25PM -0500, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
As this is the last SH4A board, remove that support as well.
Cc: Marek Vasut marek.vasut+renesas@gmail.com Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Signed-off-by: Tom Rini trini@konsulko.com --- arch/sh/Kconfig | 5 - board/renesas/sh7763rdp/Kconfig | 12 -- board/renesas/sh7763rdp/MAINTAINERS | 7 - board/renesas/sh7763rdp/Makefile | 10 - board/renesas/sh7763rdp/lowlevel_init.S | 259 ------------------------ board/renesas/sh7763rdp/sh7763rdp.c | 54 ----- configs/sh7763rdp_defconfig | 42 ---- include/configs/sh7763rdp.h | 66 ------ 8 files changed, 455 deletions(-) delete mode 100644 board/renesas/sh7763rdp/Kconfig delete mode 100644 board/renesas/sh7763rdp/MAINTAINERS delete mode 100644 board/renesas/sh7763rdp/Makefile delete mode 100644 board/renesas/sh7763rdp/lowlevel_init.S delete mode 100644 board/renesas/sh7763rdp/sh7763rdp.c delete mode 100644 configs/sh7763rdp_defconfig delete mode 100644 include/configs/sh7763rdp.h
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 2e9ccf7632a6..7836869c55dc 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -12,10 +12,6 @@ config TARGET_R2DPLUS bool "Renesas R2D-PLUS" select CPU_SH4
-config TARGET_SH7763RDP - bool "SH7763RDP" - select CPU_SH4 - endchoice
config SYS_ARCH @@ -27,6 +23,5 @@ config SYS_CPU source "arch/sh/lib/Kconfig"
source "board/renesas/r2dplus/Kconfig" -source "board/renesas/sh7763rdp/Kconfig"
endmenu diff --git a/board/renesas/sh7763rdp/Kconfig b/board/renesas/sh7763rdp/Kconfig deleted file mode 100644 index 101d2b5a32e4..000000000000 --- a/board/renesas/sh7763rdp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SH7763RDP - -config SYS_BOARD - default "sh7763rdp" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "sh7763rdp" - -endif diff --git a/board/renesas/sh7763rdp/MAINTAINERS b/board/renesas/sh7763rdp/MAINTAINERS deleted file mode 100644 index 6ee8f9f87bc8..000000000000 --- a/board/renesas/sh7763rdp/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -SH7763RDP BOARD -M: Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com -M: Nobuhiro Iwamatsu iwamatsu@nigauri.org -S: Maintained -F: board/renesas/sh7763rdp/ -F: include/configs/sh7763rdp.h -F: configs/sh7763rdp_defconfig diff --git a/board/renesas/sh7763rdp/Makefile b/board/renesas/sh7763rdp/Makefile deleted file mode 100644 index 0db63c5d2bb8..000000000000 --- a/board/renesas/sh7763rdp/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2008 Renesas Solutions Corp. -# Copyright (C) 2008 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com -# Copyright (C) 2007 Kenati Technologies, Inc. -# -# board/sh7763rdp/Makefile - -obj-y := sh7763rdp.o -extra-y += lowlevel_init.o diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S deleted file mode 100644 index 80ef2580515e..000000000000 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ /dev/null @@ -1,259 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com - * Copyright (C) 2007 Kenati Technologies, Inc. - * - * board/sh7763rdp/lowlevel_init.S - */ - -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */ - - write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */ - - write32 WDTBST_A, WDTBST_D /* - * 0xFFCC0008 - * Watchdog Base Stop Time Register - */ - - write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */ - /* Instruction Cache Invalidate */ - - write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */ - /* TI == TLB Invalidate bit */ - - write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */ - - write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */ - - write32 RAMCR_A, RAMCR_D - - mov.l MMSELR_A, r1 - mov.l MMSELR_D, r0 - synco - mov.l r0, @r1 - - mov.l @r1, r2 /* execute two reads after setting MMSELR */ - mov.l @r1, r2 - synco - - /* issue memory read */ - mov.l DDRSD_START_A, r1 /* memory address to read*/ - mov.l @r1, r0 - synco - - write32 MIM8_A, MIM8_D - - write32 MIMC_A, MIMC_D1 - - write32 STRC_A, STRC_D - - write32 SDR4_A, SDR4_D - - write32 MIMC_A, MIMC_D2 - - nop - nop - nop - - write32 SCR4_A, SCR4_D3 - - write32 SCR4_A, SCR4_D2 - - write32 SDMR02000_A, SDMR02000_D - - write32 SDMR00B08_A, SDMR00B08_D - - write32 SCR4_A, SCR4_D2 - - write32 SCR4_A, SCR4_D4 - - nop - nop - nop - nop - - write32 SCR4_A, SCR4_D4 - - nop - nop - nop - nop - - write32 SDMR00308_A, SDMR00308_D - - write32 MIMC_A, MIMC_D3 - - mov.l SCR4_A, r1 - mov.l SCR4_D1, r0 - mov.l DELAY60_D, r3 - -delay_loop_60: - mov.l r0, @r1 - dt r3 - bf delay_loop_60 - nop - - write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */ - -bsc_init: - write32 BCR_A, BCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS1BCR_A, CS1BCR_D - - write32 CS2BCR_A, CS2BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5BCR_A, CS5BCR_D - - write32 CS6BCR_A, CS6BCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS1WCR_A, CS1WCR_D - - write32 CS2WCR_A, CS2WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5WCR_A, CS5WCR_D - - write32 CS6WCR_A, CS6WCR_D - - write32 CS5PCR_A, CS5PCR_D - - write32 CS6PCR_A, CS6PCR_D - - mov.l DELAY200_D, r3 - -delay_loop_200: - dt r3 - bf delay_loop_200 - nop - - write16 PSEL0_A, PSEL0_D - - write16 PSEL1_A, PSEL1_D - - write32 ICR0_A, ICR0_D - - stc sr, r0 /* BL bit off(init=ON) */ - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - nop - - .align 2 - -DELAY60_D: .long 60 -DELAY200_D: .long 17800 - -CCR_A: .long 0xFF00001C -MMUCR_A: .long 0xFF000010 -RAMCR_A: .long 0xFF000074 - -/* Low power mode control */ -MSTPCR0_A: .long 0xFFC80030 -MSTPCR1_A: .long 0xFFC80038 - -/* RWBT */ -WDTST_A: .long 0xFFCC0000 -WDTCSR_A: .long 0xFFCC0004 -WDTBST_A: .long 0xFFCC0008 - -/* BSC */ -MMSELR_A: .long 0xFE600020 -BCR_A: .long 0xFF801000 -CS0BCR_A: .long 0xFF802000 -CS1BCR_A: .long 0xFF802010 -CS2BCR_A: .long 0xFF802020 -CS4BCR_A: .long 0xFF802040 -CS5BCR_A: .long 0xFF802050 -CS6BCR_A: .long 0xFF802060 -CS0WCR_A: .long 0xFF802008 -CS1WCR_A: .long 0xFF802018 -CS2WCR_A: .long 0xFF802028 -CS4WCR_A: .long 0xFF802048 -CS5WCR_A: .long 0xFF802058 -CS6WCR_A: .long 0xFF802068 -CS5PCR_A: .long 0xFF802070 -CS6PCR_A: .long 0xFF802080 -DDRSD_START_A: .long 0xAC000000 - -/* INTC */ -ICR0_A: .long 0xFFD00000 - -/* DDR I/F */ -MIM8_A: .long 0xFE800008 -MIMC_A: .long 0xFE80000C -SCR4_A: .long 0xFE800014 -STRC_A: .long 0xFE80001C -SDR4_A: .long 0xFE800034 -SDMR00308_A: .long 0xFE900308 -SDMR00B08_A: .long 0xFE900B08 -SDMR02000_A: .long 0xFE902000 - -/* GPIO */ -PSEL0_A: .long 0xFFEF0070 -PSEL1_A: .long 0xFFEF0072 - -CCR_CACHE_ICI_D:.long 0x00000800 -CCR_CACHE_D_2: .long 0x00000103 -MMU_CONTROL_TI_D:.long 0x00000004 -RAMCR_D: .long 0x00000200 -MSTPCR0_D: .long 0x00000000 -MSTPCR1_D: .long 0x00000000 - -MMSELR_D: .long 0xa5a50000 -BCR_D: .long 0x00000000 -CS0BCR_D: .long 0x77777770 -CS1BCR_D: .long 0x77777670 -CS2BCR_D: .long 0x77777670 -CS4BCR_D: .long 0x77777670 -CS5BCR_D: .long 0x77777670 -CS6BCR_D: .long 0x77777670 -CS0WCR_D: .long 0x7777770F -CS1WCR_D: .long 0x22000002 -CS2WCR_D: .long 0x7777770F -CS4WCR_D: .long 0x7777770F -CS5WCR_D: .long 0x7777770F -CS6WCR_D: .long 0x7777770F -CS5PCR_D: .long 0x77000000 -CS6PCR_D: .long 0x77000000 -ICR0_D: .long 0x00E00000 -MIM8_D: .long 0x00000000 -MIMC_D1: .long 0x01d10008 -MIMC_D2: .long 0x01d10009 -MIMC_D3: .long 0x01d10209 -SCR4_D1: .long 0x00000001 -SCR4_D2: .long 0x00000002 -SCR4_D3: .long 0x00000003 -SCR4_D4: .long 0x00000004 -STRC_D: .long 0x000f3980 -SDR4_D: .long 0x00000300 -SDMR00308_D: .long 0x00000000 -SDMR00B08_D: .long 0x00000000 -SDMR02000_D: .long 0x00000000 -PSEL0_D: .word 0x00000001 -PSEL1_D: .word 0x00000244 -SR_MASK_D: .long 0xEFFFFF0F -WDTST_D: .long 0x5A000FFF -WDTCSR_D: .long 0xA5000000 -WDTBST_D: .long 0x55000000 diff --git a/board/renesas/sh7763rdp/sh7763rdp.c b/board/renesas/sh7763rdp/sh7763rdp.c deleted file mode 100644 index 73a53c1e5acf..000000000000 --- a/board/renesas/sh7763rdp/sh7763rdp.c +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com - * Copyright (C) 2007 Kenati Technologies, Inc. - * - * board/sh7763rdp/sh7763rdp.c - */ - -#include <common.h> -#include <init.h> -#include <asm/io.h> -#include <asm/processor.h> - -#define CPU_CMDREG 0xB1000006 -#define PDCR 0xffef0006 -#define PECR 0xffef0008 -#define PFCR 0xffef000a -#define PGCR 0xffef000c -#define PHCR 0xffef000e -#define PJCR 0xffef0012 -#define PKCR 0xffef0014 -#define PLCR 0xffef0016 -#define PMCR 0xffef0018 -#define PSEL1 0xffef0072 -#define PSEL2 0xffef0074 -#define PSEL3 0xffef0076 - -int checkboard(void) -{ - puts("BOARD: Renesas SH7763 RDP\n"); - return 0; -} - -int board_init(void) -{ - vu_short dat; - - /* Enable mode */ - writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); - - /* GPIO Setting (eth1) */ - dat = inw(PSEL1); - writew(((dat & ~0xff00) | 0x2400), PSEL1); - writew(0, PFCR); - writew(0, PGCR); - writew(0, PHCR); - - return 0; -} - -void led_set_state(unsigned short value) -{ -} diff --git a/configs/sh7763rdp_defconfig b/configs/sh7763rdp_defconfig deleted file mode 100644 index 072202efe88b..000000000000 --- a/configs/sh7763rdp_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x8FFC0000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_TARGET_SH7763RDP=y -CONFIG_BOOTDELAY=-1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC2,115200 root=1f01" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_RUN is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_SLEEP is not set -CONFIG_CMD_JFFS2=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xA0020000 -CONFIG_ENV_ADDR_REDUND=0xA0040000 -CONFIG_VERSION_VARIABLE=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_BITBANGMII=y -CONFIG_SH_ETHER=y -CONFIG_SCIF_CONSOLE=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h deleted file mode 100644 index 5e27f3b8f155..000000000000 --- a/include/configs/sh7763rdp.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Renesas SH7763RDP board - * - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com - */ - -#ifndef __SH7763RDP_H -#define __SH7763RDP_H - -#define CONFIG_CPU_SH7763 1 -#define __LITTLE_ENDIAN 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* SCIF */ -#define CONFIG_CONS_SCIF2 1 - -#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate - settings for this board */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE (0x8C000000) -#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) - -/* Flash(NOR) */ -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) -#define CONFIG_SYS_MAX_FLASH_BANKS (1) -#define CONFIG_SYS_MAX_FLASH_SECT (520) - -/* U-Boot setting */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_MONITOR_LEN (128 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -#undef CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/* Timeout for Flash erase operations (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) -/* Timeout for Flash write operations (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) -/* Timeout for Flash set sector lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) -/* Timeout for Flash clear lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) -/* Use hardware flash sectors protection instead of U-Boot software protection */ -#undef CONFIG_SYS_DIRECT_FLASH_TFTP -/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ - -/* Clock */ -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -/* Ether */ -#define CONFIG_SH_ETHER_USE_PORT (1) -#define CONFIG_SH_ETHER_PHY_ADDR (0x01) -#define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII - -#endif /* __SH7763RDP_H */
On Wed, Feb 10, 2021 at 12:51:26PM -0500, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
On Wed, Feb 10, 2021 at 12:51:21PM -0500, Tom Rini wrote:
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it.
Signed-off-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
participants (1)
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Tom Rini