[PATCH u-boot-marvell v2 00/18] Upgrade A38x DDR3 training to version 14.0.0
Hi Stefan,
this is v2 of series that syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
I have tested how the SPL image increases for all a38x boards. Here are sizes of spl/u-boot-spl.bin before applying this series (in bytes, hexadecimal), by how much these files are increased after applying this series (in bytes, decimal).
before inc ------ --- clearfog 0x1f9c9 28 controlcenterdc 0x2263c 108 db-88f6820-amc 0x241d0 108 SPL too big (before and after) db-88f6820-gp 0x23c14 108 helios4 0x1f68d 28 turris_omnia 0x1c932 36 x530 0x249ed 108 SPL too big (before and after)
As can be seen, these patches do not increase the size of SPL much, and the only boards where SPL is too big after the series have the same problem even before applying this series.
For these boards I recommend increasing in include/configs/*.h CONFIG_SPL_SIZE from (140 << 10) to (160 << 10) and in configs/*_defconfig CONFIG_SYS_SPI_U_BOOT_OFFS from 0x24000 to 0x29000
Changes from v1: - original author names are now in the From headers - added Chris' Tested-by
Marek
Alex Leibovich (2): ddr: marvell: a38x: add ddr32 support ddr: marvell: a38x: add ddr 32bit ECC support
Baruch Siach (1): ddr: marvell: a38x: allow board specific ODT configuration
Marek Behún (7): ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import code change from upstream ddr: marvell: a38x: bump version to 14.0.0 ddr: marvell: a38x: fix comment in conditional macro
Moti Buskila (7): ddr: marvell: a38x: fix write leveling suplementary algo ddr: marvell: a38x: fix 32bit ddr: marvell: a38x: fix memory size calculation using 32bit bus width ddr: marvell: a38x: add 16Gbit memory devices support ddr: marvell: a38x: add support for twin-die combined memory device ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit ddr: marvell: a38x: fix memory cs size function
heaterC (1): ddr: marvell: a38x: enum mv_ddr_twin_die: change order
board/CZ.NIC/turris_omnia/turris_omnia.c | 2 ++ board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 1 + board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 1 + board/alliedtelesis/x530/x530.c | 1 + board/gdsys/a38x/controlcenterdc.c | 1 + board/kobol/helios4/helios4.c | 1 + board/solidrun/clearfog/clearfog.c | 1 + drivers/ddr/marvell/a38x/ddr3_init.c | 5 ++++ drivers/ddr/marvell/a38x/ddr3_training.c | 5 +++- drivers/ddr/marvell/a38x/ddr3_training_db.c | 3 +++ .../ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++ .../marvell/a38x/ddr3_training_ip_engine.c | 5 +++- drivers/ddr/marvell/a38x/ddr_topology_def.h | 23 ++++++++++++++++++- .../ddr/marvell/a38x/mv_ddr_build_message.c | 2 +- drivers/ddr/marvell/a38x/mv_ddr_plat.c | 9 ++++++-- drivers/ddr/marvell/a38x/mv_ddr_topology.c | 14 ++++++++--- drivers/ddr/marvell/a38x/mv_ddr_topology.h | 2 ++ drivers/ddr/marvell/a38x/xor.c | 6 ++--- 18 files changed, 72 insertions(+), 12 deletions(-)
From: Moti Buskila motib@marvell.com
commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.
- fix JIRA A7K8K-5056 - remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage - the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory then the algorithm will fail, since it think that there are no phase to correct
Signed-off-by: Moti Buskila motib@marvell.com Reviewed-by: Kostya Porotchkin kostap@marvell.com Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c index 979f3530b7..5fd9a052fa 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c @@ -864,8 +864,11 @@ int ddr3_tip_load_all_pattern_to_mem(u32 dev_num) DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3))); }
- for (pattern = 0; pattern < PATTERN_LAST; pattern++) + for (pattern = 0; pattern < PATTERN_LAST; pattern++) { + if (pattern == PATTERN_TEST) + continue; ddr3_tip_load_pattern_to_mem(dev_num, pattern); + }
return MV_OK; }
commit a165037ec26f301be75e1fabc263643683e85255 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 34196b1662..c55e3b57e4 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -148,7 +148,8 @@ enum mv_ddr_validation { MV_DDR_VAL_DIS, MV_DDR_VAL_RX, MV_DDR_VAL_TX, - MV_DDR_VAL_RX_TX + MV_DDR_VAL_RX_TX, + MV_DDR_MEMORY_CHECK };
struct mv_ddr_iface {
From: Alex Leibovich alexl@marvell.com
commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream.
Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c
Signed-off-by: Alex Leibovich alexl@marvell.com Reviewed-by: Nadav Haklai Nadav.Haklai@cavium.com Reviewed-by: Kostya Porotchkin Kostya.Porotchkin@cavium.com Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/mv_ddr_topology.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index 09840b1e70..f2cd7c0ef3 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -144,6 +144,9 @@ unsigned short mv_ddr_bus_bit_mask_get(void) unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
if (tm->cfg_src == MV_DDR_CFG_SPD) { + if (tm->bus_act_mask == BUS_MASK_32BIT) + tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32; + enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data); enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
@@ -151,7 +154,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void) case MV_DDR_PRI_BUS_WIDTH_16: pri_and_ext_bus_width = BUS_MASK_16BIT; break; - case MV_DDR_PRI_BUS_WIDTH_32: + case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/ pri_and_ext_bus_width = BUS_MASK_32BIT; break; case MV_DDR_PRI_BUS_WIDTH_64:
From: Alex Leibovich alexl@marvell.com
commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.
Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c
Signed-off-by: Alex Leibovich alexl@marvell.com Reviewed-by: Kostya Porotchkin Kostya.Porotchkin@cavium.com Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/mv_ddr_spd.c | 5 +++++ drivers/ddr/marvell/a38x/mv_ddr_spd.h | 1 + drivers/ddr/marvell/a38x/mv_ddr_topology.c | 6 +++++- 3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c b/drivers/ddr/marvell/a38x/mv_ddr_spd.c index 04dbfe94d6..cb90d30a6a 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c @@ -217,6 +217,11 @@ enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_ return ret_val; }
+void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity) +{ + spd_data->byte_fields.byte_4.bit_fields.die_capacity = capacity; +} + unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data) { unsigned char mem_mirror = spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h index b4bfef3103..ee35377af5 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h @@ -277,6 +277,7 @@ union mv_ddr_spd_data { int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]); enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data); enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data); +void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity); unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data); unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data); unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data); diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index f2cd7c0ef3..0cbe8d3d1e 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -74,6 +74,10 @@ int mv_ddr_topology_map_update(void) /* update device width in topology map */ iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
+ /* overwrite SPD configuration, with what the user set */ + if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) + mv_ddr_spd_die_capacity_user_get(&tm->spd_data, tm->interface_params[0].memory_size); + /* update die capacity in topology map */ iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
@@ -144,7 +148,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void) unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
if (tm->cfg_src == MV_DDR_CFG_SPD) { - if (tm->bus_act_mask == BUS_MASK_32BIT) + if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32;
enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header mv_ddr_topology.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/mv_ddr_topology.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h index 4fca47689f..1cb69ad085 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h @@ -179,7 +179,9 @@ enum mv_ddr_dic_evalue {
/* phy electrical configuration values */ enum mv_ddr_ohm_evalue { + MV_DDR_OHM_20 = 20,/*relevant for Synopsys C/A Drive strength only*/ MV_DDR_OHM_30 = 30, + MV_DDR_OHM_40 = 40,/*relevant for Synopsys C/A Drive strength only*/ MV_DDR_OHM_48 = 48, MV_DDR_OHM_60 = 60, MV_DDR_OHM_80 = 80,
From: Moti Buskila motib@marvell.com
commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream.
Signed-off-by: Moti Buskila motib@marvell.com Reviewed-by: Alex Leibovich alexl@marvell.com Reviewed-by: Kostya Porotchkin Kostya.Porotchkin@cavium.com Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/mv_ddr_topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index 0cbe8d3d1e..3feb65ea46 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -149,7 +149,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
if (tm->cfg_src == MV_DDR_CFG_SPD) { if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) - tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32; + tm->spd_data.byte_fields.byte_13.bit_fields.primary_bus_width = MV_DDR_PRI_BUS_WIDTH_32;
enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data); enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
From: Moti Buskila motib@marvell.com
commit ab9240402a70cc02496683971779e75eff410ab4 upstream.
- function mv_ddr_spd_die_capacity_user_get() has a bug, since it insert a user memory enum to it, instead of SPD memory enum (which are different) - fix: remove mv_ddr_spd_die_capacity_user_get() function. - memory size with 64 and 32 bit already calculated correctly at mv_ddr_mem_sz_per_cs_get() function
Signed-off-by: Moti Buskila motib@marvell.com Reviewed-by: Stefan Chulski Stefan.Chulski@cavium.com Reviewed-by: Alex Leibovich alexl@marvell.com Reviewed-by: Kostya Porotchkin Kostya.Porotchkin@cavium.com Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/mv_ddr_spd.c | 5 ----- drivers/ddr/marvell/a38x/mv_ddr_spd.h | 1 - drivers/ddr/marvell/a38x/mv_ddr_topology.c | 4 ---- 3 files changed, 10 deletions(-)
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c b/drivers/ddr/marvell/a38x/mv_ddr_spd.c index cb90d30a6a..04dbfe94d6 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c @@ -217,11 +217,6 @@ enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_ return ret_val; }
-void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity) -{ - spd_data->byte_fields.byte_4.bit_fields.die_capacity = capacity; -} - unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data) { unsigned char mem_mirror = spd_data->byte_fields.byte_131.bit_fields.rank_1_mapping; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h index ee35377af5..b4bfef3103 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h @@ -277,7 +277,6 @@ union mv_ddr_spd_data { int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]); enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data); enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data); -void mv_ddr_spd_die_capacity_user_get(union mv_ddr_spd_data *spd_data, enum mv_ddr_die_capacity capacity); unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data); unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data); unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data); diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index 3feb65ea46..31711fdd49 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -74,10 +74,6 @@ int mv_ddr_topology_map_update(void) /* update device width in topology map */ iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
- /* overwrite SPD configuration, with what the user set */ - if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) - mv_ddr_spd_die_capacity_user_get(&tm->spd_data, tm->interface_params[0].memory_size); - /* update die capacity in topology map */ iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/ddr_topology_def.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index c55e3b57e4..342c2cf451 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -152,6 +152,11 @@ enum mv_ddr_validation { MV_DDR_MEMORY_CHECK };
+enum mv_ddr_sscg { + SSCG_EN, + SSCG_DIS, +}; + struct mv_ddr_iface { /* base addr of ap ddr interface belongs to */ unsigned int ap_base; @@ -180,6 +185,9 @@ struct mv_ddr_iface { /* ddr interface validation mode */ enum mv_ddr_validation validation;
+ /* ddr interface validation mode */ + enum mv_ddr_sscg sscg; + /* ddr interface topology map */ struct mv_ddr_topology_map tm; };
From: Baruch Siach baruch@tkos.co.il
commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.
The ODT enable heuristic based on active chip-selects is not always correct. Some board might use two chip-selects, but have only one ODT line connected. Allow board specific mv_ddr_topology_map to directly set the ODT configuration register value.
Signed-off-by: Baruch Siach baruch@tkos.co.il Reviewed-by: Moti Buskila motib@marvell.com Reviewed-by: Nadav Haklai Nadav.Haklai@cavium.com Reviewed-by: Kostya Porotchkin Kostya.Porotchkin@cavium.com Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/ddr3_init.c | 5 +++++ drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 +++ 2 files changed, 8 insertions(+)
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c index a971cc155a..7488770268 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.c +++ b/drivers/ddr/marvell/a38x/ddr3_init.c @@ -104,6 +104,7 @@ int ddr3_init(void) static int mv_ddr_training_params_set(u8 dev_num) { struct tune_train_params params; + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); int status; u32 cs_num; int ck_delay; @@ -136,6 +137,10 @@ static int mv_ddr_training_params_set(u8 dev_num) if (ck_delay > 0) params.ck_delay = ck_delay;
+ /* Use platform specific override ODT value */ + if (tm->odt_config) + params.g_odt_config = tm->odt_config; + status = ddr3_tip_tune_training_params(dev_num, ¶ms); if (MV_OK != status) { printf("%s Training Sequence - FAILED\n", ddr_type); diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 342c2cf451..3991fec272 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -125,6 +125,9 @@ struct mv_ddr_topology_map { /* electrical parameters */ unsigned int electrical_data[MV_DDR_EDATA_LAST];
+ /* ODT configuration */ + u32 odt_config; + /* Clock enable mask */ u32 clk_enable;
From: Moti Buskila motib@marvell.com
commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream.
Signed-off-by: Moti Buskila motib@marvell.com Reviewed-by: Kostya Porotchkin kostap@marvell.com Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++ drivers/ddr/marvell/a38x/mv_ddr_topology.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h index 2a68669f36..8765df7cfb 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h @@ -80,6 +80,8 @@ #define ADDR_SIZE_2GB 0x10000000 #define ADDR_SIZE_4GB 0x20000000 #define ADDR_SIZE_8GB 0x40000000 +#define ADDR_SIZE_16GB 0x80000000 +
enum hws_edge_compare { EDGE_PF, diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index 31711fdd49..c4c3ab72b2 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -248,7 +248,8 @@ static unsigned int mem_size[] = { ADDR_SIZE_1GB, ADDR_SIZE_2GB, ADDR_SIZE_4GB, - ADDR_SIZE_8GB + ADDR_SIZE_8GB, + ADDR_SIZE_16GB /* TODO: add capacity up to 256GB */ };
From: Moti Buskila motib@marvell.com
commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.
the twin-die combined memory device should be treatened as X8 device and not as X16 one
Signed-off-by: Moti Buskila motib@marvell.com Reviewed-by: Kostya Porotchkin kostap@marvell.com [ - the default value for twin_die_combined is set to NOT_COMBINED for all boards, as this was default behaviour prior this change ] Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- board/CZ.NIC/turris_omnia/turris_omnia.c | 2 ++ board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 1 + board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 1 + board/alliedtelesis/x530/x530.c | 1 + board/gdsys/a38x/controlcenterdc.c | 1 + board/kobol/helios4/helios4.c | 1 + board/solidrun/clearfog/clearfog.c | 1 + drivers/ddr/marvell/a38x/ddr_topology_def.h | 12 ++++++++++++ drivers/ddr/marvell/a38x/mv_ddr_topology.c | 6 +++++- 9 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 0353d58a36..1d3cefe703 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -286,6 +286,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = { MV_DDR_TIM_2T} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ }; @@ -308,6 +309,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = { MV_DDR_TIM_2T} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ }; diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index 163a1b3de9..122c63d11f 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -73,6 +73,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ }; diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index 06307e582c..1edc1cb651 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -94,6 +94,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ }; diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index d602092d73..7bcfa828d7 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -68,6 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_TIM_2T} }, /* timing */ BUS_MASK_32BIT_ECC, /* subphys mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ { {0} }, /* electrical configuration */ diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index ba57a27218..4f1dc3b431 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -71,6 +71,7 @@ static struct mv_ddr_topology_map ddr_topology_map = { MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */
diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c index adb091ce4f..9c5b687b3e 100644 --- a/board/kobol/helios4/helios4.c +++ b/board/kobol/helios4/helios4.c @@ -71,6 +71,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT_ECC, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0} /* timing parameters */ }; diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 7b2accf01d..c920cf8d6b 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -142,6 +142,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ { {0} }, /* electrical configuration */ diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 3991fec272..461f091472 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -14,6 +14,11 @@ #define MV_DDR_MAX_BUS_NUM 9 #define MV_DDR_MAX_IFACE_NUM 1
+enum mv_ddr_twin_die { + COMBINED, + NOT_COMBINED, +}; + struct bus_params { /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ u8 cs_bitmask; @@ -47,6 +52,9 @@ struct if_params { /* The DDR frequency for each interfaces */ enum mv_ddr_freq memory_freq;
+ /* ddr twin-die */ + enum mv_ddr_twin_die twin_die_combined; + /* * delay CAS Write Latency * - 0 for using default value (jedec suggested) @@ -113,6 +121,9 @@ struct mv_ddr_topology_map { /* source of ddr configuration data */ enum mv_ddr_cfg_src cfg_src;
+ /* ddr twin-die */ + enum mv_ddr_twin_die twin_die_combined; + /* raw spd data */ union mv_ddr_spd_data spd_data;
@@ -193,6 +204,7 @@ struct mv_ddr_iface {
/* ddr interface topology map */ struct mv_ddr_topology_map tm; + };
struct mv_ddr_iface *mv_ddr_iface_get(void); diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c index c4c3ab72b2..2db6283c23 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c @@ -127,6 +127,11 @@ int mv_ddr_topology_map_update(void) speed_bin_index = iface_params->speed_bin_index; freq = iface_params->memory_freq;
+ if (tm->twin_die_combined == COMBINED) { + iface_params->bus_width = MV_DDR_DEV_WIDTH_8BIT; + iface_params->memory_size -= 1; + } + if (iface_params->cas_l == 0) iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
@@ -281,7 +286,6 @@ unsigned long long mv_ddr_mem_sz_per_cs_get(void) mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] * (unsigned long long)sphys / (unsigned long long)sphys_per_dunit; - return mem_sz_per_cs; }
From: Moti Buskila motib@marvell.com
commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream.
WL phase correcion stage is failing while using bus_width of 16bit, not to be fix this stage is un-necessary when working with bus_width of 16 bit.
Signed-off-by: Moti Buskila motib@marvell.com Reviewed-by: Kostya Porotchkin kostap@marvell.com Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/ddr3_training_db.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c index b2f11a8399..6aa7b6069e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_db.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c @@ -833,6 +833,9 @@ u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index) pattern = pattern_table_get_isi_word16(index); break; default: + if (((int)type == 29) || ((int)type == 30)) + break; + printf("error: %s: unsupported pattern type [%d] found\n", __func__, (int)type); pattern = 0;
commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h.
Import this header change to remain consistent with upstream.
Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 --- 1 file changed, 3 deletions(-)
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 461f091472..2cca5676a0 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -52,9 +52,6 @@ struct if_params { /* The DDR frequency for each interfaces */ enum mv_ddr_freq memory_freq;
- /* ddr twin-die */ - enum mv_ddr_twin_die twin_die_combined; - /* * delay CAS Write Latency * - 0 for using default value (jedec suggested)
From: Moti Buskila motib@marvell.com
commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.
The funtion returnd cs size in byte instead of MB, that cause calculation error since the caller was expected to get u32 and when he got above 4G it refers it as 0. The fix was to get the cs memory size from function as in MB and then multiply it by 1MB.
Signed-off-by: Moti Buskila motib@marvell.com Reviewed-by: Kostya Porotchkin kostap@marvell.com Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/mv_ddr_plat.c | 9 +++++++-- drivers/ddr/marvell/a38x/xor.c | 6 +++--- 2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 72f0dfbbbb..0d1df189e8 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -4,6 +4,7 @@ */
#include "ddr3_init.h" +#include "mv_ddr_common.h" #include "mv_ddr_training_db.h" #include "mv_ddr_regs.h" #include "mv_ddr_sys_env_lib.h" @@ -1016,7 +1017,7 @@ int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size) return MV_BAD_VALUE; }
- *cs_size = cs_mem_size << 20; /* write cs size in bytes */ + *cs_size = cs_mem_size;
return MV_OK; } @@ -1025,9 +1026,11 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) { u32 reg, cs; uint64_t mem_total_size = 0; + uint64_t cs_mem_size_mb = 0; uint64_t cs_mem_size = 0; uint64_t mem_total_size_c, cs_mem_size_c;
+ #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE u32 physical_mem_size; u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE; @@ -1038,8 +1041,9 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) for (cs = 0; cs < MAX_CS_NUM; cs++) { if (cs_ena & (1 << cs)) { /* get CS size */ - if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK) + if (ddr3_calc_mem_cs_size(cs, &cs_mem_size_mb) != MV_OK) return MV_FAIL; + cs_mem_size = cs_mem_size_mb * _1M;
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE /* @@ -1088,6 +1092,7 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) */ mem_total_size_c = (mem_total_size >> 16) & 0xffffffffffff; cs_mem_size_c = (cs_mem_size >> 16) & 0xffffffffffff; + /* if the sum less than 2 G - calculate the value */ if (mem_total_size_c + cs_mem_size_c < 0x10000) mem_total_size += cs_mem_size; diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c index 5fb9e216d3..98fb39eaf0 100644 --- a/drivers/ddr/marvell/a38x/xor.c +++ b/drivers/ddr/marvell/a38x/xor.c @@ -340,7 +340,7 @@ void ddr3_new_tip_ecc_scrub(void) { u32 cs_c, max_cs; u32 cs_ena = 0; - uint64_t total_mem_size, cs_mem_size = 0; + uint64_t total_mem_size, cs_mem_size_mb = 0, cs_mem_size = 0;
printf("DDR Training Sequence - Start scrubbing\n"); max_cs = mv_ddr_cs_num_get(); @@ -349,9 +349,9 @@ void ddr3_new_tip_ecc_scrub(void)
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) /* all chip-selects are of same size */ - ddr3_calc_mem_cs_size(0, &cs_mem_size); + ddr3_calc_mem_cs_size(0, &cs_mem_size_mb); #endif - + cs_mem_size = cs_mem_size_mb * _1M; mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); total_mem_size = max_cs * cs_mem_size; mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef);
commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.
The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes code in ddr3_training.c.
Import this change to remain consistent with upstream.
Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/ddr3_training.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 34cc170910..0358f6287a 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -143,6 +143,7 @@ static struct reg_data odpg_default_value[] = { {0x15a4, 0x0, MASK_ALL_BITS}, {0x15a8, 0x0, MASK_ALL_BITS}, {0x15ac, 0x0, MASK_ALL_BITS}, + {0x1600, 0x0, MASK_ALL_BITS}, {0x1604, 0x0, MASK_ALL_BITS}, {0x1608, 0x0, MASK_ALL_BITS}, {0x160c, 0x0, MASK_ALL_BITS}, @@ -1569,6 +1570,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, val = ((cl_mask_table[cl_value] & 0x1) << 2) | ((cl_mask_table[cl_value] & 0xe) << 3);
+ cs_mask[0] = 0xc; + CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0, val, (0x7 << 4) | (0x1 << 2)));
From: heaterC airyguy@gmx.de
commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream.
@pali suggested this change In commit 6285efb ("mv_ddr: add support for twin-die combined memory device") was added support for twin-die combined memory device and default value for explicitly uninitialized structure members is zero, s also twin_die_combined is initialized to zero. Which means COMBINED value. As prior this commit there was no support for twin-die combined memory device, default value for twin_die_combined should be NOT_COMBINED. This change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED has value zero.
Signed-off-by: heaterC airyguy@gmx.de Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/ddr_topology_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 2cca5676a0..7f2317edfa 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -15,8 +15,8 @@ #define MV_DDR_MAX_IFACE_NUM 1
enum mv_ddr_twin_die { - COMBINED, NOT_COMBINED, + COMBINED, };
struct bus_params {
Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the version in the mv-ddr-devel branch of upstream repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
There is a new version numbering system, where after 18.12.0 came 1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.
Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/mv_ddr_build_message.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c index cc6234fd40..a2bb8a96a6 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c @@ -1,3 +1,3 @@ // SPDX-License-Identifier: GPL-2.0 const char mv_ddr_build_message[] = ""; -const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2"; +const char mv_ddr_version_string[] = "mv_ddr: 14.0.0";
The code was processed with unifdef utility to omit portions not relevant to A38x and DDR3. This removes usage of many macros, including A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove the macros from #else comment.
Signed-off-by: Marek Behún marek.behun@nic.cz Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz --- drivers/ddr/marvell/a38x/ddr3_training.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 0358f6287a..2b3af23202 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -219,7 +219,7 @@ static int ddr3_tip_pad_inv(void) DDR_PHY_CONTROL, PHY_CTRL_PHY_REG, data, data); -#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 && !A3900 */ +#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */ #pragma message "unknown platform to configure ddr clock swap" #endif }
From: "From: Sujeet Baranwal" sbaranwal@marvell.com
commit 258be123226f8f5cd516b7813fe201fb7d7416e9 upstream.
At this moment, only page 0 of SPD is being read but to support smbios, we need to read page 1 also which has more info. In order to do that, we need to allocate more space.
Signed-off-by: Sujeet Baranwal sujeet.baranwal@cavium.com Tested-by: sa_ip-sw-jenkins sa_ip-sw-jenkins@marvell.com Reviewed-by: Sujeet Kumar Baranwal Sujeet.Baranwal@cavium.com Reviewed-by: Nadav Haklai nadavh@marvell.com Signed-off-by: Marek Behún marek.behun@nic.cz ---
Stefan, last time I overlooked this commit. I am sending it as part of series 2, since it can be applied on top of it.
With the first 18 patches the SPL binary size for turris_omnia_defconfig rose 36 bytes. With this change it is 424 bytes (which makes sense since the change is making some structures bigger). It is still okay for all boards that did not have "SPL too big" problem before this series.
--- drivers/ddr/marvell/a38x/mv_ddr_spd.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h index b4bfef3103..6043f11b28 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h @@ -40,7 +40,10 @@ */ union mv_ddr_spd_data { unsigned char all_bytes[MV_DDR_SPD_DATA_BLOCK0_SIZE + - MV_DDR_SPD_DATA_BLOCK1M_SIZE]; + MV_DDR_SPD_DATA_BLOCK1M_SIZE + + MV_DDR_SPD_DATA_BLOCK1H_SIZE + + MV_DDR_SPD_DATA_BLOCK2E_SIZE + + MV_DDR_SPD_DATA_BLOCK2M_SIZE]; struct { /* block 0 */ union { /* num of bytes used/num of bytes in spd device/crc coverage */ @@ -271,6 +274,9 @@ union mv_ddr_spd_data { } bit_fields; } byte_131; unsigned char bytes_132_191[60]; /* reserved; all 0s */ + unsigned char bytes_192_255[MV_DDR_SPD_DATA_BLOCK1H_SIZE]; + unsigned char bytes_256_319[MV_DDR_SPD_DATA_BLOCK2E_SIZE]; + unsigned char bytes_320_383[MV_DDR_SPD_DATA_BLOCK2M_SIZE]; } byte_fields; };
On 19.02.21 17:11, Marek Behún wrote:
Hi Stefan,
this is v2 of series that syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
I have tested how the SPL image increases for all a38x boards. Here are sizes of spl/u-boot-spl.bin before applying this series (in bytes, hexadecimal), by how much these files are increased after applying this series (in bytes, decimal).
before inc ------ --- clearfog 0x1f9c9 28controlcenterdc 0x2263c 108 db-88f6820-amc 0x241d0 108 SPL too big (before and after) db-88f6820-gp 0x23c14 108 helios4 0x1f68d 28 turris_omnia 0x1c932 36 x530 0x249ed 108 SPL too big (before and after)
As can be seen, these patches do not increase the size of SPL much, and the only boards where SPL is too big after the series have the same problem even before applying this series.
For these boards I recommend increasing in include/configs/*.h CONFIG_SPL_SIZE from (140 << 10) to (160 << 10) and in configs/*_defconfig CONFIG_SYS_SPI_U_BOOT_OFFS from 0x24000 to 0x29000
Changes from v1:
- original author names are now in the From headers
- added Chris' Tested-by
Marek
Alex Leibovich (2): ddr: marvell: a38x: add ddr32 support ddr: marvell: a38x: add ddr 32bit ECC support
Baruch Siach (1): ddr: marvell: a38x: allow board specific ODT configuration
Marek Behún (7): ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import code change from upstream ddr: marvell: a38x: bump version to 14.0.0 ddr: marvell: a38x: fix comment in conditional macro
Moti Buskila (7): ddr: marvell: a38x: fix write leveling suplementary algo ddr: marvell: a38x: fix 32bit ddr: marvell: a38x: fix memory size calculation using 32bit bus width ddr: marvell: a38x: add 16Gbit memory devices support ddr: marvell: a38x: add support for twin-die combined memory device ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit ddr: marvell: a38x: fix memory cs size function
heaterC (1): ddr: marvell: a38x: enum mv_ddr_twin_die: change order
board/CZ.NIC/turris_omnia/turris_omnia.c | 2 ++ board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 1 + board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 1 + board/alliedtelesis/x530/x530.c | 1 + board/gdsys/a38x/controlcenterdc.c | 1 + board/kobol/helios4/helios4.c | 1 + board/solidrun/clearfog/clearfog.c | 1 + drivers/ddr/marvell/a38x/ddr3_init.c | 5 ++++ drivers/ddr/marvell/a38x/ddr3_training.c | 5 +++- drivers/ddr/marvell/a38x/ddr3_training_db.c | 3 +++ .../ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++ .../marvell/a38x/ddr3_training_ip_engine.c | 5 +++- drivers/ddr/marvell/a38x/ddr_topology_def.h | 23 ++++++++++++++++++- .../ddr/marvell/a38x/mv_ddr_build_message.c | 2 +- drivers/ddr/marvell/a38x/mv_ddr_plat.c | 9 ++++++-- drivers/ddr/marvell/a38x/mv_ddr_topology.c | 14 ++++++++--- drivers/ddr/marvell/a38x/mv_ddr_topology.h | 2 ++ drivers/ddr/marvell/a38x/xor.c | 6 ++--- 18 files changed, 72 insertions(+), 12 deletions(-)
Applied to u-boot-marvell/master
Only this series for now. If we need some follow-up patches, please let me know after this is merged in master.
Thanks, Stefan
On Fri, 26 Feb 2021 12:13:14 +0100 Stefan Roese sr@denx.de wrote:
Applied to u-boot-marvell/master
Only this series for now. If we need some follow-up patches, please let me know after this is merged in master.
Very well.
participants (3)
-
Marek Behun -
Marek Behún
-
Stefan Roese