[U-Boot] [PATCH 01/12] riscv: cpu: Add nx25 to support RISC-V
From: Rick Chen rick@andestech.com
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch
Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok.
Detail verification message please see doc/README.ae250.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com Cc: Padmarao Begari Padmarao.Begari@microsemi.com --- arch/riscv/cpu/nx25/Makefile | 10 ++ arch/riscv/cpu/nx25/cpu.c | 33 +++++ arch/riscv/cpu/nx25/start.S | 291 ++++++++++++++++++++++++++++++++++++++++ arch/riscv/cpu/nx25/u-boot.lds | 69 ++++++++++ 4 files changed, 403 insertions(+), 0 deletions(-) create mode 100644 arch/riscv/cpu/nx25/Makefile create mode 100644 arch/riscv/cpu/nx25/cpu.c create mode 100644 arch/riscv/cpu/nx25/start.S create mode 100644 arch/riscv/cpu/nx25/u-boot.lds
diff --git a/arch/riscv/cpu/nx25/Makefile b/arch/riscv/cpu/nx25/Makefile new file mode 100644 index 0000000..5fcf100 --- /dev/null +++ b/arch/riscv/cpu/nx25/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen, Andes Technology Corporation rick@andestech.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y = start.o + +obj-y := cpu.o diff --git a/arch/riscv/cpu/nx25/cpu.c b/arch/riscv/cpu/nx25/cpu.c new file mode 100644 index 0000000..5478f4f --- /dev/null +++ b/arch/riscv/cpu/nx25/cpu.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* CPU specific code */ +#include <common.h> +#include <command.h> +#include <watchdog.h> +#include <asm/cache.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + /* turn off I/D-cache */ + + return 0; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + disable_interrupts(); + panic("nx25-ae250 wdt not support yet.\n"); +} diff --git a/arch/riscv/cpu/nx25/start.S b/arch/riscv/cpu/nx25/start.S new file mode 100644 index 0000000..6a07663 --- /dev/null +++ b/arch/riscv/cpu/nx25/start.S @@ -0,0 +1,291 @@ +/* + * Startup Code for RISC-V Core + * + * Copyright (c) 2017 Microsemi Corporation. + * Copyright (c) 2017 Padmarao Begari Padmarao.Begari@microsemi.com + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <common.h> +#include <elf.h> +#include <asm/encoding.h> + +#ifdef CONFIG_32BIT +#define LREG lw +#define SREG sw +#define REGBYTES 4 +#define RELOC_TYPE R_RISCV_32 +#define SYM_INDEX 0x8 +#define SYM_SIZE 0x10 +#else +#define LREG ld +#define SREG sd +#define REGBYTES 8 +#define RELOC_TYPE R_RISCV_64 +#define SYM_INDEX 0x20 +#define SYM_SIZE 0x18 +#endif + +.section .text +.globl _start +_start: + j handle_reset + +nmi_vector: + j nmi_vector + +trap_vector: + j trap_entry + +.global trap_entry +handle_reset: + la t0, trap_entry + csrw mtvec, t0 + csrwi mstatus, 0 + csrwi mie, 0 + +/* + * Do CPU critical regs init only at reboot, + * not when booting from ram + */ +#ifdef CONFIG_INIT_CRITICAL + jal cpu_init_crit /* Do CPU critical regs init */ +#endif + +/* + * Set stackpointer in internal/ex RAM to call board_init_f + */ +call_board_init_f: + li t0, -16 + li t1, CONFIG_SYS_INIT_SP_ADDR + and sp, t1, t0 /* force 16 byte alignment */ + +#ifdef CONFIG_DEBUG_UART + jal debug_uart_init +#endif + +call_board_init_f_0: + mv a0, sp + jal board_init_f_alloc_reserve + mv sp, a0 + jal board_init_f_init_reserve + + mv a0, zero /* a0 <-- boot_flags = 0 */ + la t5, board_init_f + jr t5 /* jump to board_init_f() */ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ +.globl relocate_code +relocate_code: + mv s2, a0 /* save addr_sp */ + mv s3, a1 /* save addr of gd */ + mv s4, a2 /* save addr of destination */ + +/* + *Set up the stack + */ +stack_setup: + mv sp, s2 + la t0, _start + sub t6, s4, t0 /* t6 <- relocation offset */ + beq t0, s4, clear_bss /* skip relocation */ + + mv t1, s4 /* t1 <- scratch for copy_loop */ + la t3, __bss_start + sub t3, t3, t0 /* t3 <- __bss_start_ofs */ + add t2, t0, t3 /* t2 <- source end address */ + +copy_loop: + LREG t5, 0(t0) + addi t0, t0, REGBYTES + SREG t5, 0(t1) + addi t1, t1, REGBYTES + blt t0, t2, copy_loop + +/* + * Update dynamic relocations after board_init_f + */ +fix_rela_dyn: + la t1, __rel_dyn_start + la t2, __rel_dyn_end + beq t1, t2, clear_bss + add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */ + add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */ + +/* + * skip first reserved entry: address, type, addend + */ + bne t1, t2, 7f + +6: + LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ + li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */ + bne t5, t3, 8f /* skip non-RISCV_RELOC entries */ + LREG t3, -(REGBYTES*3)(t1) + LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */ + add t5, t5, t6 /* t5 <-- location to fix up in RAM */ + add t3, t3, t6 /* t3 <-- location to fix up in RAM */ + SREG t5, 0(t3) +7: + addi t1, t1, (REGBYTES*3) + ble t1, t2, 6b + +8: + la t4, __dyn_sym_start + add t4, t4, t6 + +9: + LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ + srli t0, t5, SYM_INDEX /* t0 <--- sym table index */ + andi t5, t5, 0xFF /* t5 <--- relocation type */ + li t3, RELOC_TYPE + bne t5, t3, 10f /* skip non-addned entries */ + + LREG t3, -(REGBYTES*3)(t1) + li t5, SYM_SIZE + mul t0, t0, t5 + add s1, t4, t0 + LREG t5, REGBYTES(s1) + add t5, t5, t6 /* t5 <-- location to fix up in RAM */ + add t3, t3, t6 /* t3 <-- location to fix up in RAM */ + SREG t5, 0(t3) +10: + addi t1, t1, (REGBYTES*3) + ble t1, t2, 9b + +/* + * trap update +*/ + la t0, trap_entry + add t0, t0, t6 + csrw mtvec, t0 + +clear_bss: + la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ + add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ + la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ + add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ + li t2, 0x00000000 /* clear */ + beq t0, t1, call_board_init_r + +clbss_l: + SREG t2, 0(t0) /* clear loop... */ + addi t0, t0, REGBYTES + bne t0, t1, clbss_l + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +call_board_init_r: + la t0, board_init_r + mv t4, t0 /* offset of board_init_r() */ + add t4, t4, t6 /* real address of board_init_r() */ +/* + * setup parameters for board_init_r + */ + mv a0, s3 /* gd_t */ + mv a1, s4 /* dest_addr */ + +/* + * jump to it ... + */ + jr t4 /* jump to board_init_r() */ + +/* + * trap entry + */ +trap_entry: + addi sp, sp, -32*REGBYTES + SREG x1, 1*REGBYTES(sp) + SREG x2, 2*REGBYTES(sp) + SREG x3, 3*REGBYTES(sp) + SREG x4, 4*REGBYTES(sp) + SREG x5, 5*REGBYTES(sp) + SREG x6, 6*REGBYTES(sp) + SREG x7, 7*REGBYTES(sp) + SREG x8, 8*REGBYTES(sp) + SREG x9, 9*REGBYTES(sp) + SREG x10, 10*REGBYTES(sp) + SREG x11, 11*REGBYTES(sp) + SREG x12, 12*REGBYTES(sp) + SREG x13, 13*REGBYTES(sp) + SREG x14, 14*REGBYTES(sp) + SREG x15, 15*REGBYTES(sp) + SREG x16, 16*REGBYTES(sp) + SREG x17, 17*REGBYTES(sp) + SREG x18, 18*REGBYTES(sp) + SREG x19, 19*REGBYTES(sp) + SREG x20, 20*REGBYTES(sp) + SREG x21, 21*REGBYTES(sp) + SREG x22, 22*REGBYTES(sp) + SREG x23, 23*REGBYTES(sp) + SREG x24, 24*REGBYTES(sp) + SREG x25, 25*REGBYTES(sp) + SREG x26, 26*REGBYTES(sp) + SREG x27, 27*REGBYTES(sp) + SREG x28, 28*REGBYTES(sp) + SREG x29, 29*REGBYTES(sp) + SREG x30, 30*REGBYTES(sp) + SREG x31, 31*REGBYTES(sp) + csrr a0, mcause + csrr a1, mepc + mv a2, sp + jal handle_trap + csrw mepc, a0 + +/* + * Remain in M-mode after mret + */ + li t0, MSTATUS_MPP + csrs mstatus, t0 + LREG x1, 1*REGBYTES(sp) + LREG x2, 2*REGBYTES(sp) + LREG x3, 3*REGBYTES(sp) + LREG x4, 4*REGBYTES(sp) + LREG x5, 5*REGBYTES(sp) + LREG x6, 6*REGBYTES(sp) + LREG x7, 7*REGBYTES(sp) + LREG x8, 8*REGBYTES(sp) + LREG x9, 9*REGBYTES(sp) + LREG x10, 10*REGBYTES(sp) + LREG x11, 11*REGBYTES(sp) + LREG x12, 12*REGBYTES(sp) + LREG x13, 13*REGBYTES(sp) + LREG x14, 14*REGBYTES(sp) + LREG x15, 15*REGBYTES(sp) + LREG x16, 16*REGBYTES(sp) + LREG x17, 17*REGBYTES(sp) + LREG x18, 18*REGBYTES(sp) + LREG x19, 19*REGBYTES(sp) + LREG x20, 20*REGBYTES(sp) + LREG x21, 21*REGBYTES(sp) + LREG x22, 22*REGBYTES(sp) + LREG x23, 23*REGBYTES(sp) + LREG x24, 24*REGBYTES(sp) + LREG x25, 25*REGBYTES(sp) + LREG x26, 26*REGBYTES(sp) + LREG x27, 27*REGBYTES(sp) + LREG x28, 28*REGBYTES(sp) + LREG x29, 29*REGBYTES(sp) + LREG x30, 30*REGBYTES(sp) + LREG x31, 31*REGBYTES(sp) + addi sp, sp, 32*REGBYTES + mret + +#ifdef CONFIG_INIT_CRITICAL +cpu_init_crit: + ret +#endif diff --git a/arch/riscv/cpu/nx25/u-boot.lds b/arch/riscv/cpu/nx25/u-boot.lds new file mode 100644 index 0000000..936fd77 --- /dev/null +++ b/arch/riscv/cpu/nx25/u-boot.lds @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +OUTPUT_ARCH("riscv") +ENTRY(_start) + +SECTIONS +{ + . = ALIGN(4); + .text : + { + arch/riscv/cpu/nx25/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + __global_pointer$ = . + 0x800; + *(.data*) + } + . = ALIGN(4); + + .got : { + __got_start = .; + *(.got.plt) *(.got) + __got_end = .; + } + + . = ALIGN(4); + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + /DISCARD/ : { *(.rela.plt*) } + .rela.dyn : { + __rel_dyn_start = .; + *(.rela*) + __rel_dyn_end = .; + } + + . = ALIGN(4); + + .dynsym : { + __dyn_sym_start = .; + *(.dynsym) + __dyn_sym_end = .; + } + + . = ALIGN(4); + + _end = .; + + .bss : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end = .; + } + +}
From: Rick Chen rick@andestech.com
Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com Cc: Padmarao Begari Padmarao.Begari@microsemi.com --- arch/riscv/lib/Makefile | 14 +++ arch/riscv/lib/boot.c | 19 ++++ arch/riscv/lib/bootm.c | 248 +++++++++++++++++++++++++++++++++++++++++++ arch/riscv/lib/cache.c | 50 +++++++++ arch/riscv/lib/interrupts.c | 76 +++++++++++++ 5 files changed, 407 insertions(+), 0 deletions(-) create mode 100644 arch/riscv/lib/Makefile create mode 100644 arch/riscv/lib/boot.c create mode 100644 arch/riscv/lib/bootm.c create mode 100644 arch/riscv/lib/cache.c create mode 100644 arch/riscv/lib/interrupts.c
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile new file mode 100644 index 0000000..323cf3e --- /dev/null +++ b/arch/riscv/lib/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen, Andes Technology Corporation rick@andestech.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_GO) += boot.o +obj-y += cache.o +obj-y += interrupts.o diff --git a/arch/riscv/lib/boot.c b/arch/riscv/lib/boot.c new file mode 100644 index 0000000..39ba9b4 --- /dev/null +++ b/arch/riscv/lib/boot.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned long do_go_exec(ulong (*entry)(int, char * const []), + int argc, char * const argv[]) +{ + cleanup_before_linux(); + + return entry(argc, argv); +} diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c new file mode 100644 index 0000000..44ce38b --- /dev/null +++ b/arch/riscv/lib/bootm.c @@ -0,0 +1,248 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com + * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <image.h> +#include <u-boot/zlib.h> +#include <asm/byteorder.h> +#include <asm/bootm.h> + +DECLARE_GLOBAL_DATA_PTR; + +int arch_fixup_fdt(void *blob) +{ + return 0; +} + +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) +static void setup_start_tag(bd_t *bd); + +# ifdef CONFIG_SETUP_MEMORY_TAGS +static void setup_memory_tags(bd_t *bd); +# endif +static void setup_commandline_tag(bd_t *bd, char *commandline); + +# ifdef CONFIG_INITRD_TAG +static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end); +# endif +static void setup_end_tag(bd_t *bd); + +static struct tag *params; +#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ + +int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +{ + bd_t *bd = gd->bd; + char *s; + int machid = bd->bi_arch_number; + void (*theKernel)(int zero, int arch, uint params); + +#ifdef CONFIG_CMDLINE_TAG + char *commandline = env_get("bootargs"); +#endif + + /* + * allow the PREP bootm subcommand, it is required for bootm to work + */ + if (flag & BOOTM_STATE_OS_PREP) + return 0; + + if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) + return 1; + + theKernel = (void (*)(int, int, uint))images->ep; + + s = env_get("machid"); + if (s) { + machid = simple_strtoul(s, NULL, 16); + printf("Using machid 0x%x from environment\n", machid); + } + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + debug("## Transferring control to Linux (at address %08lx) ...\n", + (ulong)theKernel); + + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { +#ifdef CONFIG_OF_LIBFDT + debug("using: FDT\n"); + if (image_setup_linux(images)) { + printf("FDT creation failed! hanging..."); + hang(); + } +#endif + } else if (BOOTM_ENABLE_TAGS) { +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) + setup_start_tag(bd); +#ifdef CONFIG_SERIAL_TAG + setup_serial_tag(¶ms); +#endif +#ifdef CONFIG_REVISION_TAG + setup_revision_tag(¶ms); +#endif +#ifdef CONFIG_SETUP_MEMORY_TAGS + setup_memory_tags(bd); +#endif +#ifdef CONFIG_CMDLINE_TAG + setup_commandline_tag(bd, commandline); +#endif +#ifdef CONFIG_INITRD_TAG + if (images->rd_start && images->rd_end) + setup_initrd_tag(bd, images->rd_start, images->rd_end); +#endif + setup_end_tag(bd); +#endif + + /* we assume that the kernel is in place */ + printf("\nStarting kernel ...\n\n"); + +#ifdef CONFIG_USB_DEVICE + { + extern void udc_disconnect(void); + udc_disconnect(); + } +#endif + } + cleanup_before_linux(); + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) + theKernel(0, machid, (unsigned long)images->ft_addr); + else + theKernel(0, machid, bd->bi_boot_params); + /* does not return */ + + return 1; +} + +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) +static void setup_start_tag(bd_t *bd) +{ + params = (struct tag *)bd->bi_boot_params; + + params->hdr.tag = ATAG_CORE; + params->hdr.size = tag_size(tag_core); + + params->u.core.flags = 0; + params->u.core.pagesize = 0; + params->u.core.rootdev = 0; + + params = tag_next(params); +} + +#ifdef CONFIG_SETUP_MEMORY_TAGS +static void setup_memory_tags(bd_t *bd) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + params->hdr.tag = ATAG_MEM; + params->hdr.size = tag_size(tag_mem32); + + params->u.mem.start = bd->bi_dram[i].start; + params->u.mem.size = bd->bi_dram[i].size; + + params = tag_next(params); + } +} +#endif /* CONFIG_SETUP_MEMORY_TAGS */ + +static void setup_commandline_tag(bd_t *bd, char *commandline) +{ + char *p; + + if (!commandline) + return; + + /* eat leading white space */ + for (p = commandline; *p == ' '; p++) + ; + + /* skip non-existent command lines so the kernel will still + * use its default command line. + */ + if (*p == '\0') + return; + + params->hdr.tag = ATAG_CMDLINE; + params->hdr.size = + (sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2; + + strcpy(params->u.cmdline.cmdline, p) + ; + + params = tag_next(params); +} + +#ifdef CONFIG_INITRD_TAG +static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end) +{ + /* an ATAG_INITRD node tells the kernel where the compressed + * ramdisk can be found. ATAG_RDIMG is a better name, actually. + */ + params->hdr.tag = ATAG_INITRD2; + params->hdr.size = tag_size(tag_initrd); + + params->u.initrd.start = initrd_start; + params->u.initrd.size = initrd_end - initrd_start; + + params = tag_next(params); +} +#endif /* CONFIG_INITRD_TAG */ + +#ifdef CONFIG_SERIAL_TAG +void setup_serial_tag(struct tag **tmp) +{ + struct tag *params; + struct tag_serialnr serialnr; + void get_board_serial(struct tag_serialnr *serialnr); + + params = *tmp; + get_board_serial(&serialnr); + params->hdr.tag = ATAG_SERIAL; + params->hdr.size = tag_size(tag_serialnr); + params->u.serialnr.low = serialnr.low; + params->u.serialnr.high = serialnr.high; + params = tag_next(params); + *tmp = params; +} +#endif + +#ifdef CONFIG_REVISION_TAG +void setup_revision_tag(struct tag **in_params) +{ + u32 rev; + u32 get_board_rev(void); + + rev = get_board_rev(); + params->hdr.tag = ATAG_REVISION; + params->hdr.size = tag_size(tag_revision); + params->u.revision.rev = rev; + params = tag_next(params); +} +#endif /* CONFIG_REVISION_TAG */ + +static void setup_end_tag(bd_t *bd) +{ + params->hdr.tag = ATAG_NONE; + params->hdr.size = 0; +} + +#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c new file mode 100644 index 0000000..948656f --- /dev/null +++ b/arch/riscv/lib/cache.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +void flush_dcache_range(unsigned long start, unsigned long end) +{ +} + +void invalidate_icache_range(unsigned long start, unsigned long end) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ +} + +void flush_cache(unsigned long addr, unsigned long size) +{ +} + +void icache_enable(void) +{ +} + +void icache_disable(void) +{ +} + +int icache_status(void) +{ + return 0; +} + +void dcache_enable(void) +{ +} + +void dcache_disable(void) +{ +} + +int dcache_status(void) +{ + return 0; +} diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c new file mode 100644 index 0000000..075db8b --- /dev/null +++ b/arch/riscv/lib/interrupts.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2016-17 Microsemi Corporation. + * Padmarao Begari, Microsemi Corporation padmarao.begari@microsemi.com + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/ptrace.h> +#include <asm/system.h> +#include <asm/encoding.h> + +static void _exit_trap(int code, uint epc, struct pt_regs *regs); + +int interrupt_init(void) +{ + return 0; +} + +/* + * enable interrupts + */ +void enable_interrupts(void) +{ +} + +/* + * disable interrupts + */ +int disable_interrupts(void) +{ + return 0; +} + +uint handle_trap(uint mcause, uint epc, struct pt_regs *regs) +{ + uint is_int; + + is_int = (mcause & MCAUSE_INT); + if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) + external_interrupt(0); /* handle_m_ext_interrupt */ + else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) + timer_interrupt(0); /* handle_m_timer_interrupt */ + else + _exit_trap(mcause, epc, regs); + + return epc; +} + +/* + *Entry Point for PLIC Interrupt Handler + */ +__attribute__((weak)) void external_interrupt(struct pt_regs *regs) +{ +} + +__attribute__((weak)) void timer_interrupt(struct pt_regs *regs) +{ +} + +static void _exit_trap(int code, uint epc, struct pt_regs *regs) +{ + static const char *exception_code[] = { + "Instruction address misaligned", + "Instruction access fault", + "Illegal instruction", + "Breakpoint", + "Load address misaligned" + }; + + printf("exception code: %d , %s , epc %08x , ra %08lx\n", + code, exception_code[code], epc, regs->ra); +}
From: Rick Chen rick@andestech.com
AE250 is the Soc using NX25 cpu core base on RISC-V arch. Details please see the doc/README.ae250.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com --- arch/riscv/dts/Makefile | 14 +++++++ arch/riscv/dts/ae250.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 0 deletions(-) create mode 100644 arch/riscv/dts/Makefile create mode 100644 arch/riscv/dts/ae250.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile new file mode 100644 index 0000000..718b99f --- /dev/null +++ b/arch/riscv/dts/Makefile @@ -0,0 +1,14 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +dtb-$(CONFIG_TARGET_NX25_AE250) += ae250.dtb +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/riscv/dts/ae250.dts b/arch/riscv/dts/ae250.dts new file mode 100644 index 0000000..5dc4fb0 --- /dev/null +++ b/arch/riscv/dts/ae250.dts @@ -0,0 +1,96 @@ +/dts-v1/; +/ { + compatible = "riscv32 nx25"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + aliases { + uart0 = &serial0; + ethernet0 = &mac0; + spi0 = &spi; + } ; + + chosen { + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + tick-timer = &timer0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "andestech,n13"; + reg = <0>; + /* FIXME: to fill correct frqeuency */ + clock-frequency = <60000000>; + }; + }; + + intc: interrupt-controller { + compatible = "andestech,atnointc010"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <7 4>; + clock-frequency = <19660800>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2 4>; + clock-frequency = <40000000>; + }; + + mac0: mac@e0100000 { + compatible = "andestech,atmac100"; + reg = <0xe0100000 0x1000>; + interrupts = <25 4>; + }; + + mmc0: mmc@f0e00000 { + compatible = "andestech,atsdc010"; + max-frequency = <100000000>; + fifo-depth = <0x10>; + reg = <0xf0e00000 0x1000>; + interrupts = <17 4>; + }; + + spi: spi@f0b00000 { + compatible = "andestech,atcspi200"; + reg = <0xf0b00000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + clocks = <&spiclk>; + interrupts = <3 4>; + flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-cpol; + spi-cpha; + }; + }; + +};
From: Rick Chen rick@andestech.com
Add header files for RISC-V. Cache, ptregs, data type and other definitions are included.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com --- arch/riscv/include/asm/bitops.h | 172 ++++++++++++ arch/riscv/include/asm/bootm.h | 65 +++++ arch/riscv/include/asm/byteorder.h | 35 +++ arch/riscv/include/asm/cache.h | 22 ++ arch/riscv/include/asm/config.h | 13 + arch/riscv/include/asm/encoding.h | 188 +++++++++++++ arch/riscv/include/asm/global_data.h | 22 ++ arch/riscv/include/asm/io.h | 494 +++++++++++++++++++++++++++++++++ arch/riscv/include/asm/linkage.h | 12 + arch/riscv/include/asm/mach-types.h | 30 ++ arch/riscv/include/asm/posix_types.h | 89 ++++++ arch/riscv/include/asm/processor.h | 26 ++ arch/riscv/include/asm/ptrace.h | 106 +++++++ arch/riscv/include/asm/sections.h | 11 + arch/riscv/include/asm/setup.h | 191 +++++++++++++ arch/riscv/include/asm/string.h | 43 +++ arch/riscv/include/asm/system.h | 18 ++ arch/riscv/include/asm/types.h | 64 +++++ arch/riscv/include/asm/u-boot-riscv.h | 21 ++ arch/riscv/include/asm/u-boot.h | 46 +++ arch/riscv/include/asm/unaligned.h | 1 + 21 files changed, 1669 insertions(+), 0 deletions(-) create mode 100644 arch/riscv/include/asm/bitops.h create mode 100644 arch/riscv/include/asm/bootm.h create mode 100644 arch/riscv/include/asm/byteorder.h create mode 100644 arch/riscv/include/asm/cache.h create mode 100644 arch/riscv/include/asm/config.h create mode 100644 arch/riscv/include/asm/encoding.h create mode 100644 arch/riscv/include/asm/global_data.h create mode 100644 arch/riscv/include/asm/io.h create mode 100644 arch/riscv/include/asm/linkage.h create mode 100644 arch/riscv/include/asm/mach-types.h create mode 100644 arch/riscv/include/asm/posix_types.h create mode 100644 arch/riscv/include/asm/processor.h create mode 100644 arch/riscv/include/asm/ptrace.h create mode 100644 arch/riscv/include/asm/sections.h create mode 100644 arch/riscv/include/asm/setup.h create mode 100644 arch/riscv/include/asm/string.h create mode 100644 arch/riscv/include/asm/system.h create mode 100644 arch/riscv/include/asm/types.h create mode 100644 arch/riscv/include/asm/u-boot-riscv.h create mode 100644 arch/riscv/include/asm/u-boot.h create mode 100644 arch/riscv/include/asm/unaligned.h
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h new file mode 100644 index 0000000..55d420f --- /dev/null +++ b/arch/riscv/include/asm/bitops.h @@ -0,0 +1,172 @@ +/* + * Copyright 1995, Russell King. + * Various bits and pieces copyrights include: + * Linus Torvalds (test_bit). + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + * + * Please note that the code in this file should never be included + * from user space. Many of these are not implemented in assembler + * since they would be too costly. Also, they require priviledged + * instructions (which are not available from user mode) to ensure + * that they are atomic. + */ + +#ifndef __ASM_RISCV_BITOPS_H +#define __ASM_RISCV_BITOPS_H + +#ifdef __KERNEL__ + +#include <asm/system.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> + +#define smp_mb__before_clear_bit() do { } while (0) +#define smp_mb__after_clear_bit() do { } while (0) + +/* + * Function prototypes to keep gcc -Wall happy. + */ +static inline void __set_bit(int nr, void *addr) +{ + int *a = (int *)addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +static inline void __clear_bit(int nr, void *addr) +{ + int *a = (int *)addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a &= ~mask; +} + +static inline void __change_bit(int nr, void *addr) +{ + int mask; + unsigned long *ADDR = (unsigned long *)addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + *ADDR ^= mask; +} + +static inline int __test_and_set_bit(int nr, void *addr) +{ + int mask, retval; + unsigned int *a = (unsigned int *)addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + return retval; +} + +static inline int __test_and_clear_bit(int nr, void *addr) +{ + int mask, retval; + unsigned int *a = (unsigned int *)addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + return retval; +} + +static inline int __test_and_change_bit(int nr, void *addr) +{ + int mask, retval; + unsigned int *a = (unsigned int *)addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + return retval; +} + +/* + * This routine doesn't need to be atomic. + */ +static inline int test_bit(int nr, const void *addr) +{ + return ((unsigned char *)addr)[nr >> 3] & (1U << (nr & 7)); +} + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long word) +{ + int k; + + word = ~word; + k = 31; + if (word & 0x0000ffff) { + k -= 16; word <<= 16; + } + if (word & 0x00ff0000) { + k -= 8; word <<= 8; + } + if (word & 0x0f000000) { + k -= 4; word <<= 4; + } + if (word & 0x30000000) { + k -= 2; word <<= 2; + } + if (word & 0x40000000) + k -= 1; + + return k; +} + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +/* + * redefined in include/linux/bitops.h + * #define ffs(x) generic_ffs(x) + */ + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#define ext2_set_bit test_and_set_bit +#define ext2_clear_bit test_and_clear_bit +#define ext2_test_bit test_bit +#define ext2_find_first_zero_bit find_first_zero_bit +#define ext2_find_next_zero_bit find_next_zero_bit + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr, addr) test_and_set_bit(nr, addr) +#define minix_set_bit(nr, addr) set_bit(nr, addr) +#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr) +#define minix_test_bit(nr, addr) test_bit(nr, addr) +#define minix_find_first_zero_bit(addr, size) find_first_zero_bit(addr, size) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_RISCV_BITOPS_H */ diff --git a/arch/riscv/include/asm/bootm.h b/arch/riscv/include/asm/bootm.h new file mode 100644 index 0000000..0a644bb --- /dev/null +++ b/arch/riscv/include/asm/bootm.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013, Google Inc. + * + * Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz schwarz@corscience.de + * + * SPDX-License-Identifier: GPL-2.0+ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef NDS32_BOOTM_H +#define NDS32_BOOTM_H + +#include <asm/setup.h> + +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) +# define BOOTM_ENABLE_TAGS 1 +#else +# define BOOTM_ENABLE_TAGS 0 +#endif + +#ifdef CONFIG_SETUP_MEMORY_TAGS +# define BOOTM_ENABLE_MEMORY_TAGS 1 +#else +# define BOOTM_ENABLE_MEMORY_TAGS 0 +#endif + +#ifdef CONFIG_CMDLINE_TAG + #define BOOTM_ENABLE_CMDLINE_TAG 1 +#else + #define BOOTM_ENABLE_CMDLINE_TAG 0 +#endif + +#ifdef CONFIG_INITRD_TAG + #define BOOTM_ENABLE_INITRD_TAG 1 +#else + #define BOOTM_ENABLE_INITRD_TAG 0 +#endif + +#ifdef CONFIG_SERIAL_TAG + #define BOOTM_ENABLE_SERIAL_TAG 1 +void get_board_serial(struct tag_serialnr *serialnr); +#else + #define BOOTM_ENABLE_SERIAL_TAG 0 +static inline void get_board_serial(struct tag_serialnr *serialnr) +{ +} +#endif + +#ifdef CONFIG_REVISION_TAG + #define BOOTM_ENABLE_REVISION_TAG 1 +u32 get_board_rev(void); +#else + #define BOOTM_ENABLE_REVISION_TAG 0 +static inline u32 get_board_rev(void) +{ + return 0; +} +#endif + +#endif diff --git a/arch/riscv/include/asm/byteorder.h b/arch/riscv/include/asm/byteorder.h new file mode 100644 index 0000000..d26ac56 --- /dev/null +++ b/arch/riscv/include/asm/byteorder.h @@ -0,0 +1,35 @@ +/* + * linux/include/asm-arm/byteorder.h + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * ARM Endian-ness. In little endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + * + * When in big endian mode, byte accesses appear as: + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ + +#ifndef __ASM_RISCV_BYTEORDER_H +#define __ASM_RISCV_BYTEORDER_H + +#include <asm/types.h> + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __RISCVEB__ +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h new file mode 100644 index 0000000..facf072 --- /dev/null +++ b/arch/riscv/include/asm/cache.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_RISCV_CACHE_H +#define _ASM_RISCV_CACHE_H + +/* + * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. + * We use that value for aligning DMA buffers unless the board config has + * specified an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 32 +#endif + +#endif /* _ASM_RISCV_CACHE_H */ diff --git a/arch/riscv/include/asm/config.h b/arch/riscv/include/asm/config.h new file mode 100644 index 0000000..5f94eb0 --- /dev/null +++ b/arch/riscv/include/asm/config.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#define CONFIG_LMB + +#endif diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h new file mode 100644 index 0000000..5ff6d59 --- /dev/null +++ b/arch/riscv/include/asm/encoding.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2017 Microsemi Corporation. + * Padmarao Begari, Microsemi Corporation padmarao.begari@microsemi.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define MCAUSE32_CAUSE 0x7FFFFFFF +#define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF +#define MCAUSE32_INT 0x80000000 +#define MCAUSE64_INT 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define MIP_SSIP BIT(IRQ_S_SOFT) +#define MIP_HSIP BIT(IRQ_H_SOFT) +#define MIP_MSIP BIT(IRQ_M_SOFT) +#define MIP_STIP BIT(IRQ_S_TIMER) +#define MIP_HTIP BIT(IRQ_H_TIMER) +#define MIP_MTIP BIT(IRQ_M_TIMER) +#define MIP_SEIP BIT(IRQ_S_EXT) +#define MIP_HEIP BIT(IRQ_H_EXT) +#define MIP_MEIP BIT(IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_TYPE 0x01E // Type +#define PTE_R 0x020 // Referenced +#define PTE_D 0x040 // Dirty +#define PTE_SOFT 0x380 // Reserved for Software + +#define PTE_TYPE_TABLE 0x00 +#define PTE_TYPE_TABLE_GLOBAL 0x02 +#define PTE_TYPE_URX_SR 0x04 +#define PTE_TYPE_URWX_SRW 0x06 +#define PTE_TYPE_UR_SR 0x08 +#define PTE_TYPE_URW_SRW 0x0A +#define PTE_TYPE_URX_SRX 0x0C +#define PTE_TYPE_URWX_SRWX0x0E +#define PTE_TYPE_SR 0x10 +#define PTE_TYPE_SRW 0x12 +#define PTE_TYPE_SRX 0x14 +#define PTE_TYPE_SRWX 0x16 +#define PTE_TYPE_SR_GLOBAL 0x18 +#define PTE_TYPE_SRW_GLOBAL 0x1A +#define PTE_TYPE_SRX_GLOBAL 0x1C +#define PTE_TYPE_SRWX_GLOBAL 0x1E + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) +#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) +#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) +#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) +#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) +#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) +#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) + +#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \ + ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ + (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ + ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) + +#ifdef __riscv +#ifdef CONFIG_64BIT +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define MCAUSE_INT MCAUSE64_INT +# define MCAUSE_CAUSE MCAUSE64_CAUSE +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define MCAUSE_INT MCAUSE32_INT +# define MCAUSE_CAUSE MCAUSE32_CAUSE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE BIT(RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ +if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ +else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ +if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ +else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ +if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ +else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ +if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ +else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif +#endif +#endif +#endif diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h new file mode 100644 index 0000000..0cce98a --- /dev/null +++ b/arch/riscv/include/asm/global_data.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (c) 2017 Microsemi Corporation. + * Padmarao Begari, Microsemi Corporation padmarao.begari@microsemi.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H + +/* Architecture-specific global data */ +struct arch_global_data { +}; + +#include <asm-generic/global_data.h> + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("gp") + +#endif /* __ASM_GBL_DATA_H */ diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h new file mode 100644 index 0000000..e7f63ed --- /dev/null +++ b/arch/riscv/include/asm/io.h @@ -0,0 +1,494 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0 + * + */ +#ifndef __ASM_RISCV_IO_H +#define __ASM_RISCV_IO_H + +#ifdef __KERNEL__ + +#include <linux/types.h> +#include <asm/byteorder.h> + +static inline void sync(void) +{ +} + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +#ifdef CONFIG_ARCH_MAP_SYSMEM +static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) +{ + if (paddr < PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE) + paddr = paddr | 0x40000000; + return (void *)(uintptr_t)paddr; +} + +static inline void *unmap_sysmem(const void *vaddr) +{ + phys_addr_t paddr = (phys_addr_t)vaddr; + + paddr = paddr & ~0x40000000; + return (void *)(uintptr_t)paddr; +} + +static inline phys_addr_t map_to_sysmem(const void *ptr) +{ + return (phys_addr_t)(uintptr_t)ptr; +} +#endif + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ +} + +static inline phys_addr_t virt_to_phys(void *vaddr) +{ + return (phys_addr_t)(vaddr); +} + +/* + * Generic virtual read/write. Note that we don't support half-word + * read/writes. We define __arch_*[bl] here, and leave __arch_*w + * to the architecture specific code. + */ +#define __arch_getb(a) (*(unsigned char *)(a)) +#define __arch_getw(a) (*(unsigned short *)(a)) +#define __arch_getl(a) (*(unsigned int *)(a)) +#define __arch_getq(a) (*(unsigned long *)(a)) + +#define __arch_putb(v, a) (*(unsigned char *)(a) = (v)) +#define __arch_putw(v, a) (*(unsigned short *)(a) = (v)) +#define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) +#define __arch_putq(v, a) (*(unsigned long *)(a) = (v)) + +#define __raw_writeb(v, a) __arch_putb(v, a) +#define __raw_writew(v, a) __arch_putw(v, a) +#define __raw_writel(v, a) __arch_putl(v, a) +#define __raw_writeq(v, a) __arch_putq(v, a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) +#define __raw_readq(a) __arch_getq(a) + +/* + * TODO: The kernel offers some more advanced versions of barriers, it might + * have some advantages to use them instead of the simple one here. + */ +#define dmb() __asm__ __volatile__ ("" : : : "memory") +#define __iormb() dmb() +#define __iowmb() dmb() + +static inline void writeb(u8 val, volatile void __iomem *addr) +{ + __iowmb(); + __arch_putb(val, addr); +} + +static inline void writew(u16 val, volatile void __iomem *addr) +{ + __iowmb(); + __arch_putw(val, addr); +} + +static inline void writel(u32 val, volatile void __iomem *addr) +{ + __iowmb(); + __arch_putl(val, addr); +} + +static inline void writeq(u64 val, volatile void __iomem *addr) +{ + __iowmb(); + __arch_putq(val, addr); +} + +static inline u8 readb(const volatile void __iomem *addr) +{ + u8 val; + + val = __arch_getb(addr); + __iormb(); + return val; +} + +static inline u16 readw(const volatile void __iomem *addr) +{ + u16 val; + + val = __arch_getw(addr); + __iormb(); + return val; +} + +static inline u32 readl(const volatile void __iomem *addr) +{ + u32 val; + + val = __arch_getl(addr); + __iormb(); + return val; +} + +static inline u64 readq(const volatile void __iomem *addr) +{ + u32 val; + + val = __arch_getq(addr); + __iormb(); + return val; +} + +/* + * The compiler seems to be incapable of optimising constants + * properly. Spell it out to the compiler in some cases. + * These are only valid for small values of "off" (< 1<<12) + */ +#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off) +#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off) +#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off) + +#define __raw_base_readb(base, off) __arch_base_getb(base, off) +#define __raw_base_readw(base, off) __arch_base_getw(base, off) +#define __raw_base_readl(base, off) __arch_base_getl(base, off) + +#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) +#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le32(a, v) out_arch(l, le32, a, v) +#define out_le16(a, v) out_arch(w, le16, a, v) + +#define in_le32(a) in_arch(l, le32, a) +#define in_le16(a) in_arch(w, le16, a) + +#define out_be32(a, v) out_arch(l, be32, a, v) +#define out_be16(a, v) out_arch(w, be16, a, v) + +#define in_be32(a) in_arch(l, be32, a) +#define in_be16(a) in_arch(w, be16, a) + +#define out_8(a, v) __raw_writeb(v, a) +#define in_8(a) __raw_readb(a) + +/* + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + +/* + * Now, pick up the machine-defined IO definitions + * #include <asm/arch/io.h> + */ + +/* + * IO port access primitives + * ------------------------- + * + * The NDS32 doesn't have special IO access instructions just like ARM; + * all IO is memory mapped. + * Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * Note that for a big endian machine, this implies that the following + * big endian mode connectivity is in place, as described by numerious + * ARM documents: + * + * PCI: D0-D7 D8-D15 D16-D23 D24-D31 + * ARM: D24-D31 D16-D23 D8-D15 D0-D7 + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. + * + * Note that we prevent GCC re-ordering or caching values in expressions + * by introducing sequence points into the in*() definitions. Note that + * __raw_* do not guarantee this behaviour. + * + * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. + */ +#ifdef __io +#define outb(v, p) __raw_writeb(v, __io(p)) +#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p)) +#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) + +#define outsb(p, d, l) writesb(__io(p), d, l) +#define outsw(p, d, l) writesw(__io(p), d, l) +#define outsl(p, d, l) writesl(__io(p), d, l) + +#define insb(p, d, l) readsb(__io(p), d, l) +#define insw(p, d, l) readsw(__io(p), d, l) +#define insl(p, d, l) readsl(__io(p), d, l) + +static inline void readsb(unsigned int *addr, void *data, int bytelen) +{ + unsigned char *ptr; + unsigned char *ptr2; + + ptr = (unsigned char *)addr; + ptr2 = (unsigned char *)data; + + while (bytelen) { + *ptr2 = *ptr; + ptr2++; + bytelen--; + } +} + +static inline void readsw(unsigned int *addr, void *data, int wordlen) +{ + unsigned short *ptr; + unsigned short *ptr2; + + ptr = (unsigned short *)addr; + ptr2 = (unsigned short *)data; + + while (wordlen) { + *ptr2 = *ptr; + ptr2++; + wordlen--; + } +} + +static inline void readsl(unsigned int *addr, void *data, int longlen) +{ + unsigned int *ptr; + unsigned int *ptr2; + + ptr = (unsigned int *)addr; + ptr2 = (unsigned int *)data; + + while (longlen) { + *ptr2 = *ptr; + ptr2++; + longlen--; + } +} + +static inline void writesb(unsigned int *addr, const void *data, int bytelen) +{ + unsigned char *ptr; + unsigned char *ptr2; + + ptr = (unsigned char *)addr; + ptr2 = (unsigned char *)data; + + while (bytelen) { + *ptr = *ptr2; + ptr2++; + bytelen--; + } +} + +static inline void writesw(unsigned int *addr, const void *data, int wordlen) +{ + unsigned short *ptr; + unsigned short *ptr2; + + ptr = (unsigned short *)addr; + ptr2 = (unsigned short *)data; + + while (wordlen) { + *ptr = *ptr2; + ptr2++; + wordlen--; + } +} + +static inline void writesl(unsigned int *addr, const void *data, int longlen) +{ + unsigned int *ptr; + unsigned int *ptr2; + + ptr = (unsigned int *)addr; + ptr2 = (unsigned int *)data; + + while (longlen) { + *ptr = *ptr2; + ptr2++; + longlen--; + } +} +#endif + +#define outb_p(val, port) outb((val), (port)) +#define outw_p(val, port) outw((val), (port)) +#define outl_p(val, port) outl((val), (port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port, from, len) outsb(port, from, len) +#define outsw_p(port, from, len) outsw(port, from, len) +#define outsl_p(port, from, len) outsl(port, from, len) +#define insb_p(port, to, len) insb(port, to, len) +#define insw_p(port, to, len) insw(port, to, len) +#define insl_p(port, to, len) insl(port, to, len) + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ + +/* + * String version of IO memory access ops: + */ + +/* + * If this architecture has PCI memory IO, then define the read/write + * macros. These should only be used with the cookie passed from + * ioremap. + */ +#ifdef __mem_pci + +#define readb(c) ({ unsigned int __v = \ + __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = \ + le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = \ + le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) + +#define writeb(v, c) __raw_writeb(v, __mem_pci(c)) +#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c)) +#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c)) + +#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l)) +#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l)) +#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l)) + +#define eth_io_copy_and_sum(s, c, l, b) \ + eth_copy_and_sum((s), __mem_pci(c), (l), (b)) + +static inline int +check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} +#endif /* __mem_pci */ + +/* + * If this architecture has ISA IO, then define the isa_read/isa_write + * macros. + */ +#ifdef __mem_isa + +#define isa_readb(addr) __raw_readb(__mem_isa(addr)) +#define isa_readw(addr) __raw_readw(__mem_isa(addr)) +#define isa_readl(addr) __raw_readl(__mem_isa(addr)) +#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr)) +#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr)) +#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr)) +#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c)) +#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c)) +#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c)) + +#define isa_eth_io_copy_and_sum(a, b, c, d) \ + eth_copy_and_sum((a), __mem_isa(b), (c), (d)) + +static inline int +isa_check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + + do { + if (isa_readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#else /* __mem_isa */ + +#define isa_readb(addr) (__readwrite_bug("isa_readb"), 0) +#define isa_readw(addr) (__readwrite_bug("isa_readw"), 0) +#define isa_readl(addr) (__readwrite_bug("isa_readl"), 0) +#define isa_writeb(val, addr) __readwrite_bug("isa_writeb") +#define isa_writew(val, addr) __readwrite_bug("isa_writew") +#define isa_writel(val, addr) __readwrite_bug("isa_writel") +#define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io") +#define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio") +#define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio") + +#define isa_eth_io_copy_and_sum(a, b, c, d) \ + __readwrite_bug("isa_eth_io_copy_and_sum") + +#define isa_check_signature(io, sig, len) (0) + +#endif /* __mem_isa */ +#endif /* __KERNEL__ */ +#endif /* __ASM_RISCV_IO_H */ diff --git a/arch/riscv/include/asm/linkage.h b/arch/riscv/include/asm/linkage.h new file mode 100644 index 0000000..60d5317 --- /dev/null +++ b/arch/riscv/include/asm/linkage.h @@ -0,0 +1,12 @@ +/* + * U-Boot - linkage.h + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#endif diff --git a/arch/riscv/include/asm/mach-types.h b/arch/riscv/include/asm/mach-types.h new file mode 100644 index 0000000..f70b407 --- /dev/null +++ b/arch/riscv/include/asm/mach-types.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_RISCV_MACH_TYPE_H +#define __ASM_RISCV_MACH_TYPE_H + +#ifndef __ASSEMBLY__ +/* The type of machine we're running on */ +extern unsigned int __machine_arch_type; +#endif + +#define MACH_TYPE_AE250 1 + +#ifdef CONFIG_ARCH_AE250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AE250 +# endif +# define machine_is_ae250() (machine_arch_type == MACH_TYPE_AE250) +#else +# define machine_is_ae250() (1) +#endif + +#endif /* __ASM_RISCV_MACH_TYPE_H */ diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h new file mode 100644 index 0000000..6892b66 --- /dev/null +++ b/arch/riscv/include/asm/posix_types.h @@ -0,0 +1,89 @@ +/* + * linux/include/asm-arm/posix_types.h + * + * Copyright (C) 1996-1998 Russell King. + * + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * Copyright (C) 2017 Rick Chen (rick@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + * 25-10-2017 Modified for arch RISCV + */ +#ifndef __ARCH_RISCV_POSIX_TYPES_H +#define __ARCH_RISCV_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +#ifdef __GNUC__ +typedef __SIZE_TYPE__ __kernel_size_t; +#else +typedef unsigned int __kernel_size_t; +#endif +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char *__kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1 << (fd & 31))) + +#undef __FD_CLR +#define __FD_CLR(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1 << (fd & 31))) + +#undef __FD_ISSET +#define __FD_ISSET(fd, fdsetp) \ + ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1 << (fd & 31))) != 0) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ + (memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp))) + +#endif + +#endif /* __ARCH_RISCV_POSIX_TYPES_H */ diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h new file mode 100644 index 0000000..fe35752 --- /dev/null +++ b/arch/riscv/include/asm/processor.h @@ -0,0 +1,26 @@ +/* + * linux/include/asm-arm/processor.h + * + * Copyright (C) 1995-2002 Russell King + * + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * Copyright (C) 2017 Rick Chen (rick@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_RISCV_PROCESSOR_H +#define __ASM_RISCV_PROCESSOR_H + +/************************************************************** + * CAUTION: + * - do not implement for RISCV Arch yet. + * - so far some files include /asm/processor.h, but + * no one uses the macros defined in this head file. + **************************************************************/ + +#endif /* __ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h new file mode 100644 index 0000000..76d6869 --- /dev/null +++ b/arch/riscv/include/asm/ptrace.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2017 Microsemi Corporation. + * Copyright (c) 2017 Padmarao Begari Padmarao.Begari@microsemi.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_RISCV_PTRACE_H +#define __ASM_RISCV_PTRACE_H + +struct pt_regs { + unsigned long sepc; + unsigned long ra; + unsigned long sp; + unsigned long gp; + unsigned long tp; + unsigned long t0; + unsigned long t1; + unsigned long t2; + unsigned long s0; + unsigned long s1; + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; + unsigned long s2; + unsigned long s3; + unsigned long s4; + unsigned long s5; + unsigned long s6; + unsigned long s7; + unsigned long s8; + unsigned long s9; + unsigned long s10; + unsigned long s11; + unsigned long t3; + unsigned long t4; + unsigned long t5; + unsigned long t6; + /* Supervisor CSRs */ + unsigned long sstatus; + unsigned long sbadaddr; + unsigned long scause; +}; + +#ifdef CONFIG_64BIT +#define REG_FMT "%016lx" +#else +#define REG_FMT "%08lx" +#endif + +#define user_mode(regs) (((regs)->sstatus & SR_PS) == 0) + +/* Helpers for working with the instruction pointer */ +#define GET_IP(regs) ((regs)->sepc) +#define SET_IP(regs, val) (GET_IP(regs) = (val)) + +static inline unsigned long instruction_pointer(struct pt_regs *regs) +{ + return GET_IP(regs); +} + +static inline void instruction_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + SET_IP(regs, val); +} + +#define profile_pc(regs) instruction_pointer(regs) + +/* Helpers for working with the user stack pointer */ +#define GET_USP(regs) ((regs)->sp) +#define SET_USP(regs, val) (GET_USP(regs) = (val)) + +static inline unsigned long user_stack_pointer(struct pt_regs *regs) +{ + return GET_USP(regs); +} + +static inline void user_stack_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + SET_USP(regs, val); +} + +/* Helpers for working with the frame pointer */ +#define GET_FP(regs) ((regs)->s0) +#define SET_FP(regs, val) (GET_FP(regs) = (val)) + +static inline unsigned long frame_pointer(struct pt_regs *regs) +{ + return GET_FP(regs); +} + +static inline void frame_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + SET_FP(regs, val); +} + +#endif /* __ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/include/asm/sections.h b/arch/riscv/include/asm/sections.h new file mode 100644 index 0000000..9faa099 --- /dev/null +++ b/arch/riscv/include/asm/sections.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_RISCV_SECTIONS_H +#define __ASM_RISCV_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/riscv/include/asm/setup.h b/arch/riscv/include/asm/setup.h new file mode 100644 index 0000000..731b0d9 --- /dev/null +++ b/arch/riscv/include/asm/setup.h @@ -0,0 +1,191 @@ +/* + * linux/arch/nds32/include/asm/setup.h + * + * Copyright (C) 1997-1999 Russell King + * Copyright (C) 2008 Andes Technology Corporation + * Copyright (C) 2013 Ken Kuo (ken_kuo@andestech.com) + * Copyright (C) 2017 Rick Chen (rick@andestech.com) + * + * SPDX-License-Identifier: GPL-2.0 + * + * Structure passed to kernel to tell it about the + * hardware it's running on. See Documentation/arm/Setup + * for more info. + */ +#ifndef __RISCV_SETUP_H +#define __RISCV_SETUP_H + +#define COMMAND_LINE_SIZE 256 + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; /* bit 0 = read-only */ + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 + +struct tag_mem32 { + u32 size; + u32 start; /* physical start address */ +}; + +/* VGA text type displays */ +#define ATAG_VIDEOTEXT 0x54410003 + +struct tag_videotext { + u8 x; + u8 y; + u16 video_page; + u8 video_mode; + u8 video_cols; + u16 video_ega_bx; + u8 video_lines; + u8 video_isvga; + u16 video_points; +}; + +/* describes how the ramdisk will be used in kernel */ +#define ATAG_RAMDISK 0x54410004 + +struct tag_ramdisk { + u32 flags; /* bit 0 = load, bit 1 = prompt */ + u32 size; /* decompressed ramdisk size in _kilo_ bytes */ + u32 start; /* starting block of floppy-based RAM disk image */ +}; + +/* + * this one accidentally used virtual addresses - as such, + * it's deprecated. + * describes where the compressed ramdisk image lives (virtual address) + */ +#define ATAG_INITRD 0x54410005 + +/* describes where the compressed ramdisk image lives (physical address) */ +#define ATAG_INITRD2 0x54420005 + +struct tag_initrd { + u32 start; /* physical start address */ + u32 size; /* size of compressed ramdisk image in bytes */ +}; + +/* board serial number. "64 bits should be enough for everybody" */ +#define ATAG_SERIAL 0x54410006 + +struct tag_serialnr { + u32 low; + u32 high; +}; + +/* board revision */ +#define ATAG_REVISION 0x54410007 + +struct tag_revision { + u32 rev; +}; + +/* initial values for vesafb-type framebuffers. see struct screen_info + * in include/linux/tty.h + */ +#define ATAG_VIDEOLFB 0x54410008 + +struct tag_videolfb { + u16 lfb_width; + u16 lfb_height; + u16 lfb_depth; + u16 lfb_linelength; + u32 lfb_base; + u32 lfb_size; + u8 red_size; + u8 red_pos; + u8 green_size; + u8 green_pos; + u8 blue_size; + u8 blue_pos; + u8 rsvd_size; + u8 rsvd_pos; +}; + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410009 + +struct tag_cmdline { + char cmdline[COMMAND_LINE_SIZE]; +}; + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem32 mem; + struct tag_videotext videotext; + struct tag_ramdisk ramdisk; + struct tag_initrd initrd; + struct tag_serialnr serialnr; + struct tag_revision revision; + struct tag_videolfb videolfb; + struct tag_cmdline cmdline; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(const struct tag *); +}; + +#define tag_member_present(tag, member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t, base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +#ifdef __KERNEL__ + +#define __tag __used __attribute__((__section__(".taglist"))) +#define __tagtable(tag, fn) \ +static struct tagtable __tagtable_##fn __tag = { tag, fn } + +/* + * Memory map description + */ +#define NR_BANKS 8 + +struct meminfo { + int nr_banks; + struct { + unsigned long start; + unsigned long size; + int node; + } bank[NR_BANKS]; +}; + +/* + * Early command line parameters. + */ +struct early_params { + const char *arg; + void (*fn)(char **p); +}; + +#define __early_param(name, fn) \ +static struct early_params __early_##fn __used \ +__attribute__((__section__("__early_param"))) = { name, fn } + +#endif +#endif diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h new file mode 100644 index 0000000..038cdae --- /dev/null +++ b/arch/riscv/include/asm/string.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * Copyright (C) 2017 Rick Chen (rick@andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_RISCV_STRING_H +#define __ASM_RISCV_STRING_H + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#undef __HAVE_ARCH_STRRCHR +#undef __HAVE_ARCH_STRCHR +#undef __HAVE_ARCH_MEMCPY +#undef __HAVE_ARCH_MEMMOVE +#undef __HAVE_ARCH_MEMCHR +#undef __HAVE_ARCH_MEMZERO +#undef __HAVE_ARCH_MEMSET + +#ifdef CONFIG_MARCO_MEMSET +#define memset(p, v, n) \ + ({ \ + if ((n) != 0) { \ + if (__builtin_constant_p((v)) && (v) == 0) \ + __memzero((p), (n)); \ + else \ + memset((p), (v), (n)); \ + } \ + (p); \ + }) + +#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); }) +#endif + +#endif /* __ASM_RISCV_STRING_H */ diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h new file mode 100644 index 0000000..443a300 --- /dev/null +++ b/arch/riscv/include/asm/system.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_RISCV_SYSTEM_H +#define __ASM_RISCV_SYSTEM_H + +/* + * Interrupt configuring macros. + * + * TODO + * + */ + +#endif /* __ASM_RISCV_SYSTEM_H */ diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h new file mode 100644 index 0000000..9797206 --- /dev/null +++ b/arch/riscv/include/asm/types.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * Copyright (C) 2017 Rick Chen (rick@andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_RISCV_TYPES_H +#define __ASM_RISCV_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +#include <stddef.h> + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +#endif /* __KERNEL__ */ + +#endif diff --git a/arch/riscv/include/asm/u-boot-riscv.h b/arch/riscv/include/asm/u-boot-riscv.h new file mode 100644 index 0000000..18099cd --- /dev/null +++ b/arch/riscv/include/asm/u-boot-riscv.h @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _U_BOOT_RISCV_H_ +#define _U_BOOT_RISCV_H_ 1 + +/* cpu/.../cpu.c */ +int cleanup_before_linux(void); + +/* board/.../... */ +int board_init(void); + +#endif /* _U_BOOT_RISCV_H_ */ diff --git a/arch/riscv/include/asm/u-boot.h b/arch/riscv/include/asm/u-boot.h new file mode 100644 index 0000000..ddf7a63 --- /dev/null +++ b/arch/riscv/include/asm/u-boot.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +#include <asm/u-boot-riscv.h> + +#include <environment.h> + +typedef struct bd_info { + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned char bi_enetaddr[6]; + + struct /* RAM configuration */ + { + unsigned long start; + unsigned long size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; +} bd_t; + +/* For image.h:image_check_target_arch() */ +#define IH_ARCH_DEFAULT IH_ARCH_RISCV + +#endif /* _U_BOOT_H_ */ diff --git a/arch/riscv/include/asm/unaligned.h b/arch/riscv/include/asm/unaligned.h new file mode 100644 index 0000000..6cecbbb --- /dev/null +++ b/arch/riscv/include/asm/unaligned.h @@ -0,0 +1 @@ +#include <asm-generic/unaligned.h>
From: Rick Chen rick@andestech.com
Add Kconfig and makefile for RISC-V
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com Cc: Padmarao Begari Padmarao.Begari@microsemi.com --- arch/riscv/Kconfig | 42 ++++++++++++++++++++++++++++++++++++++++++ arch/riscv/Makefile | 11 +++++++++++ arch/riscv/config.mk | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+), 0 deletions(-) create mode 100644 arch/riscv/Kconfig create mode 100644 arch/riscv/Makefile create mode 100644 arch/riscv/config.mk
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig new file mode 100644 index 0000000..c50be37 --- /dev/null +++ b/arch/riscv/Kconfig @@ -0,0 +1,42 @@ +menu "RISCV architecture" + depends on RISCV + +config SYS_ARCH + default "riscv" + +choice + prompt "Target select" + optional + +config TARGET_NX25_AE250 + bool "Support nx25-ae250" + +endchoice + +source "board/AndesTech/nx25-ae250/Kconfig" + +choice + prompt "CPU selection" + default CPU_RISCV_32 + +config CPU_RISCV_32 + bool "RISCV 32 bit" + select 32BIT + help + Choose this option to build an U-Boot for RISCV32 architecture. + +config CPU_RISCV_64 + bool "RISCV 64 bit" + select 64BIT + help + Choose this option to build an U-Boot for RISCV64 architecture. + +endchoice + +config 32BIT + bool + +config 64BIT + bool + +endmenu diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile new file mode 100644 index 0000000..09d24db --- /dev/null +++ b/arch/riscv/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen, Andes Technology Corporation rick@andestech.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/riscv/cpu/$(CPU)/start.o + +libs-y += arch/riscv/cpu/$(CPU)/ +libs-y += arch/riscv/lib/ diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk new file mode 100644 index 0000000..6b681c4 --- /dev/null +++ b/arch/riscv/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (c) 2017 Microsemi Corporation. +# Padmarao Begari, Microsemi Corporation padmarao.begari@microsemi.com +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen, Andes Technology Corporation rick@andestech.com +# +# SPDX-License-Identifier: GPL-2.0+ + +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := riscv32-unknown-linux-gnu- +endif + +32bit-emul := elf32lriscv +64bit-emul := elf64lriscv + +ifdef CONFIG_32BIT +PLATFORM_LDFLAGS += -m $(32bit-emul) +endif + +ifdef CONFIG_64BIT +PLATFORM_LDFLAGS += -m $(64bit-emul) +endif + +CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \ + -T $(srctree)/examples/standalone/riscv.lds + +PLATFORM_CPPFLAGS += -ffixed-gp -fpic +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2 +LDFLAGS_u-boot += --gc-sections -static -pie
On Fri, Dec 22, 2017 at 03:44:22PM +0800, Andes wrote:
From: Rick Chen rick@andestech.com
Add Kconfig and makefile for RISC-V
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com Cc: Padmarao Begari Padmarao.Begari@microsemi.com
arch/riscv/Kconfig | 42 ++++++++++++++++++++++++++++++++++++++++++ arch/riscv/Makefile | 11 +++++++++++ arch/riscv/config.mk | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+), 0 deletions(-) create mode 100644 arch/riscv/Kconfig create mode 100644 arch/riscv/Makefile create mode 100644 arch/riscv/config.mk
This should also touch the top-level MAINTAINERS, thanks!
2017-12-22 23:30 GMT+08:00 Tom Rini trini@konsulko.com:
On Fri, Dec 22, 2017 at 03:44:22PM +0800, Andes wrote:
From: Rick Chen rick@andestech.com
Add Kconfig and makefile for RISC-V
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com Cc: Padmarao Begari Padmarao.Begari@microsemi.com
arch/riscv/Kconfig | 42 ++++++++++++++++++++++++++++++++++++++++++ arch/riscv/Makefile | 11 +++++++++++ arch/riscv/config.mk | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+), 0 deletions(-) create mode 100644 arch/riscv/Kconfig create mode 100644 arch/riscv/Makefile create mode 100644 arch/riscv/config.mk
This should also touch the top-level MAINTAINERS, thanks!
I will touch the top-level MAINTAINERS in the next version. Thanks for reviewing.
Rick
-- Tom
From: Rick Chen rick@andestech.com
Add nx25-ae250 board to do platform initializations.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com --- board/AndesTech/nx25-ae250/Kconfig | 24 ++++++++++ board/AndesTech/nx25-ae250/MAINTAINERS | 6 ++ board/AndesTech/nx25-ae250/Makefile | 8 +++ board/AndesTech/nx25-ae250/nx25-ae250.c | 77 +++++++++++++++++++++++++++++++ 4 files changed, 115 insertions(+), 0 deletions(-) create mode 100644 board/AndesTech/nx25-ae250/Kconfig create mode 100644 board/AndesTech/nx25-ae250/MAINTAINERS create mode 100644 board/AndesTech/nx25-ae250/Makefile create mode 100644 board/AndesTech/nx25-ae250/nx25-ae250.c
diff --git a/board/AndesTech/nx25-ae250/Kconfig b/board/AndesTech/nx25-ae250/Kconfig new file mode 100644 index 0000000..2fb3234 --- /dev/null +++ b/board/AndesTech/nx25-ae250/Kconfig @@ -0,0 +1,24 @@ +if TARGET_NX25_AE250 + +config SYS_CPU + default "nx25" + +config SYS_BOARD + default "nx25-ae250" + +config SYS_VENDOR + default "AndesTech" + +config SYS_SOC + default "ae250" + +config SYS_CONFIG_NAME + default "nx25-ae250" + +config ENV_SIZE + default 0x2000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x140000 if ENV_IS_IN_SPI_FLASH + +endif diff --git a/board/AndesTech/nx25-ae250/MAINTAINERS b/board/AndesTech/nx25-ae250/MAINTAINERS new file mode 100644 index 0000000..1bff127 --- /dev/null +++ b/board/AndesTech/nx25-ae250/MAINTAINERS @@ -0,0 +1,6 @@ +NX25-AE250 BOARD +M: Rick Chen rick@andestech.com +S: Maintained +F: board/AndesTech/nx25-ae250/ +F: include/configs/nx25-ae250.h +F: configs/nx25-ae250_defconfig diff --git a/board/AndesTech/nx25-ae250/Makefile b/board/AndesTech/nx25-ae250/Makefile new file mode 100644 index 0000000..66b6814 --- /dev/null +++ b/board/AndesTech/nx25-ae250/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen, Andes Technology Corporation rick@andestech.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := nx25-ae250.o diff --git a/board/AndesTech/nx25-ae250/nx25-ae250.c b/board/AndesTech/nx25-ae250/nx25-ae250.c new file mode 100644 index 0000000..12f2d35 --- /dev/null +++ b/board/AndesTech/nx25-ae250/nx25-ae250.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/mach-types.h> +#include <common.h> +#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) +#include <netdev.h> +#endif +#include <linux/io.h> +#include <faraday/ftsdc010.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_AE250; + gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; + + return 0; +} + +int dram_init(void) +{ + unsigned long sdram_base = PHYS_SDRAM_0; + unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; + unsigned long actual_size; + + actual_size = get_ram_size((void *)sdram_base, expected_size); + gd->ram_size = actual_size; + + if (expected_size != actual_size) { + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + } + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_0; + gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) +int board_eth_init(bd_t *bd) +{ + return ftmac100_initialize(bd); +} +#endif + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + return 0; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_DM_MMC +#ifdef CONFIG_FTSDC010 + ftsdc010_mmc_init(0); +#endif +#endif + return 0; +}
From: Rick Chen rick@andestech.com
Add nx25-ae250 board configuartion options for RISC-V
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com --- include/configs/nx25-ae250.h | 126 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 126 insertions(+), 0 deletions(-) create mode 100644 include/configs/nx25-ae250.h
diff --git a/include/configs/nx25-ae250.h b/include/configs/nx25-ae250.h new file mode 100644 index 0000000..b523797 --- /dev/null +++ b/include/configs/nx25-ae250.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * CPU and Board Configuration Options + */ +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_SERVERIP + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#ifdef CONFIG_OF_CONTROL +#undef CONFIG_OF_SEPARATE +#define CONFIG_OF_EMBED +#endif +#else +#define CONFIG_SYS_TEXT_BASE 0x80000000 +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* + * Print Buffer Size + */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * max number of command args + */ +#define CONFIG_SYS_MAXARGS 16 + +/* + * Boot Argument Buffer Size + */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * Size of malloc() pool + * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough + */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 \ + (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ +#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 + +/* + * Serial console configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#endif +#define CONFIG_SYS_NS16550_CLK 19660800 + +/* + * SD (MMC) controller + */ +#define CONFIG_FTSDC010_NUMBER 1 +#define CONFIG_FTSDC010_SDIO + +/* Init Stack Pointer */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Load address and memory test area should agree with + * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */ + +/* + * memtest works on 512 MB in DRAM + */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) + +/* environments */ +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OVERWRITE + +/* SPI FLASH */ +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + +/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +/* Increase max gunzip size */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +#endif /* __CONFIG_H */
From: Rick Chen rick@andestech.com
Add nx25-ae250 default configuration for RISC-V
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com --- configs/nx25-ae250_defconfig | 36 ++++++++++++++++++++++++++++++++++++ 1 files changed, 36 insertions(+), 0 deletions(-) create mode 100644 configs/nx25-ae250_defconfig
diff --git a/configs/nx25-ae250_defconfig b/configs/nx25-ae250_defconfig new file mode 100644 index 0000000..1f68b66 --- /dev/null +++ b/configs/nx25-ae250_defconfig @@ -0,0 +1,36 @@ +CONFIG_RISCV=y +CONFIG_TARGET_NX25_AE250=y +CONFIG_DEFAULT_DEVICE_TREE="ae250" +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_DM_MMC=y +CONFIG_MMC_NDS32=y +CONFIG_FTSDC010=y +CONFIG_DM_ETH=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_ATCSPI200_SPI=y +CONFIG_TIMER=y +CONFIG_ATCPIT100_TIMER=y
From: Rick Chen rick@andestech.com
Add prelink-riscv to arrange .rela.dyn and .rela.got in compile time.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com --- Makefile | 4 ++ tools/Makefile | 1 + tools/prelink-riscv.c | 91 ++++++++++++++++++++++++++++++++++++++++++ tools/prelink-riscv.inc | 101 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 197 insertions(+), 0 deletions(-) create mode 100644 tools/prelink-riscv.c create mode 100644 tools/prelink-riscv.inc
diff --git a/Makefile b/Makefile index c573ddb..bb6416f 100644 --- a/Makefile +++ b/Makefile @@ -1264,6 +1264,10 @@ ifeq ($(CONFIG_KALLSYMS),y) $(call cmd,u-boot__) common/system_map.o endif
+ifeq ($(CONFIG_RISCV),y) + @tools/prelink-riscv $@ 0 +endif + quiet_cmd_sym ?= SYM $@ cmd_sym ?= $(OBJDUMP) -t $< > $@ u-boot.sym: u-boot FORCE diff --git a/tools/Makefile b/tools/Makefile index 4d32fe5..571f571 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -185,6 +185,7 @@ hostprogs-$(CONFIG_KIRKWOOD) += kwboot hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot hostprogs-y += proftool hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela +hostprogs-$(CONFIG_RISCV) += prelink-riscv
hostprogs-y += fdtgrep fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o diff --git a/tools/prelink-riscv.c b/tools/prelink-riscv.c new file mode 100644 index 0000000..dd099a9 --- /dev/null +++ b/tools/prelink-riscv.c @@ -0,0 +1,91 @@ +#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__ +#error "Only little-endian host is supported" +#endif + +#include <errno.h> +#include <stdbool.h> +#include <stdint.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include <elf.h> +#include <fcntl.h> +#include <sys/mman.h> +#include <sys/stat.h> +#include <sys/types.h> +#include <unistd.h> + +#ifndef EM_RISCV +#define EM_RISCV 243 +#endif + +#ifndef R_RISCV_32 +#define R_RISCV_32 1 +#endif + +#ifndef R_RISCV_64 +#define R_RISCV_64 2 +#endif + +#ifndef R_RISCV_RELATIVE +#define R_RISCV_RELATIVE 3 +#endif + +const char *argv0; + +#define die(fmt, ...) \ + do { \ + fprintf(stderr, "%s: " fmt "\n", argv0, ## __VA_ARGS__); \ + exit(EXIT_FAILURE); \ + } while (0) + +#define PRELINK_INC_BITS 32 +#include "prelink-riscv.inc" +#undef PRELINK_INC_BITS + +#define PRELINK_INC_BITS 64 +#include "prelink-riscv.inc" +#undef PRELINK_INC_BITS + +int main(int argc, const char *const *argv) +{ + argv0 = argv[0]; + + if (argc < 2) { + fprintf(stderr, "Usage: %s <u-boot>\n", argv0); + exit(EXIT_FAILURE); + } + + int fd = open(argv[1], O_RDWR, 0); + + if (fd < 0) + die("Cannot open %s: %s", argv[1], strerror(errno)); + + struct stat st; + + if (fstat(fd, &st) < 0) + die("Cannot stat %s: %s", argv[1], strerror(errno)); + + void *data = + mmap(0, st.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + + if (data == MAP_FAILED) + die("Cannot mmap %s: %s", argv[1], strerror(errno)); + + close(fd); + + unsigned char *e_ident = (unsigned char *)data; + + if (memcmp(e_ident, ELFMAG, SELFMAG) != 0) + die("Invalid ELF file %s", argv[1]); + + bool is64 = e_ident[EI_CLASS] == ELFCLASS64; + + if (is64) + prelink64(data); + else + prelink32(data); + + return 0; +} diff --git a/tools/prelink-riscv.inc b/tools/prelink-riscv.inc new file mode 100644 index 0000000..f7f9596 --- /dev/null +++ b/tools/prelink-riscv.inc @@ -0,0 +1,101 @@ +#define CONCAT_IMPL(x, y) x##y +#define CONCAT(x, y) CONCAT_IMPL(x, y) +#define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z) + +#define prelink_nn CONCAT(prelink, PRELINK_INC_BITS) +#define uintnn_t CONCAT3(uint, PRELINK_INC_BITS, _t) +#define get_offset_nn CONCAT(get_offset_, PRELINK_INC_BITS) +#define Elf_Ehdr CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr) +#define Elf_Phdr CONCAT3(Elf, PRELINK_INC_BITS, _Phdr) +#define Elf_Rela CONCAT3(Elf, PRELINK_INC_BITS, _Rela) +#define Elf_Sym CONCAT3(Elf, PRELINK_INC_BITS, _Sym) +#define Elf_Dyn CONCAT3(Elf, PRELINK_INC_BITS, _Dyn) +#define Elf_Addr CONCAT3(Elf, PRELINK_INC_BITS, _Addr) +#define ELF_R_TYPE CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE) +#define ELF_R_SYM CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM) + +static void* get_offset_nn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr) +{ + Elf_Phdr *p; + + for (p = phdrs; p < phdrs + phnum; ++p) + if (p->p_vaddr <= addr && p->p_vaddr + p->p_memsz > addr) + return data + p->p_offset + (addr - p->p_vaddr); + + return NULL; +} + +static void prelink_nn(void *data) +{ + Elf_Ehdr *ehdr = data; + Elf_Phdr *p; + Elf_Dyn *dyn; + Elf_Rela *r; + + if (ehdr->e_machine != EM_RISCV) + die("Machine type is not RISC-V"); + + Elf_Phdr *phdrs = data + ehdr->e_phoff; + + Elf_Dyn *dyns = NULL; + for (p = phdrs; p < phdrs + ehdr->e_phnum; ++p) { + if (p->p_type == PT_DYNAMIC) { + dyns = data + p->p_offset; + break; + } + } + + if (dyns == NULL) + die("No dynamic section found"); + + Elf_Rela *rela_dyn = NULL; + size_t rela_count = 0; + Elf_Sym *dynsym = NULL; + for (dyn = dyns;; ++dyn) { + if (dyn->d_tag == DT_NULL) + break; + else if (dyn->d_tag == DT_RELA) + rela_dyn = get_offset_nn(data, phdrs, ehdr->e_phnum, + dyn->d_un.d_ptr); + else if (dyn->d_tag == DT_RELASZ) + rela_count = dyn->d_un.d_val / sizeof(Elf_Rela); + else if (dyn->d_tag == DT_SYMTAB) + dynsym = get_offset_nn(data, phdrs, ehdr->e_phnum, + dyn->d_un.d_ptr); + + } + + if (rela_dyn == NULL) + die("No .rela.dyn found"); + + if (dynsym == NULL) + die("No .dynsym found"); + + for (r = rela_dyn; r < rela_dyn + rela_count; ++r) { + void* buf = get_offset_nn(data, phdrs, ehdr->e_phnum, r->r_offset); + + if (buf == NULL) + continue; + + if (ELF_R_TYPE(r->r_info) == R_RISCV_RELATIVE) + *((uintnn_t*) buf) = r->r_addend; + else if (ELF_R_TYPE(r->r_info) == R_RISCV_32) + *((uint32_t*) buf) = dynsym[ELF_R_SYM(r->r_info)].st_value; + else if (ELF_R_TYPE(r->r_info) == R_RISCV_64) + *((uint64_t*) buf) = dynsym[ELF_R_SYM(r->r_info)].st_value; + } +} + +#undef prelink_nn +#undef uintnn_t +#undef get_offset_nn +#undef Elf_Ehdr +#undef Elf_Phdr +#undef Elf_Rela +#undef Elf_Sym +#undef Elf_Dyn +#undef Elf_Addr +#undef ELF_R_TYPE +#undef ELF_R_SYM + +#undef CONCAT_IMPL +#undef CONCAT +#undef CONCAT3
On Fri, Dec 22, 2017 at 03:44:26PM +0800, Andes wrote:
From: Rick Chen rick@andestech.com
Add prelink-riscv to arrange .rela.dyn and .rela.got in compile time.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com
Makefile | 4 ++ tools/Makefile | 1 + tools/prelink-riscv.c | 91 ++++++++++++++++++++++++++++++++++++++++++ tools/prelink-riscv.inc | 101 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 197 insertions(+), 0 deletions(-) create mode 100644 tools/prelink-riscv.c create mode 100644 tools/prelink-riscv.inc
diff --git a/Makefile b/Makefile index c573ddb..bb6416f 100644 --- a/Makefile +++ b/Makefile @@ -1264,6 +1264,10 @@ ifeq ($(CONFIG_KALLSYMS),y) $(call cmd,u-boot__) common/system_map.o endif
+ifeq ($(CONFIG_RISCV),y)
- @tools/prelink-riscv $@ 0
+endif
quiet_cmd_sym ?= SYM $@ cmd_sym ?= $(OBJDUMP) -t $< > $@ u-boot.sym: u-boot FORCE diff --git a/tools/Makefile b/tools/Makefile index 4d32fe5..571f571 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -185,6 +185,7 @@ hostprogs-$(CONFIG_KIRKWOOD) += kwboot hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot hostprogs-y += proftool hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela +hostprogs-$(CONFIG_RISCV) += prelink-riscv
hostprogs-y += fdtgrep fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o diff --git a/tools/prelink-riscv.c b/tools/prelink-riscv.c new file mode 100644 index 0000000..dd099a9 --- /dev/null +++ b/tools/prelink-riscv.c @@ -0,0 +1,91 @@ +#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__ +#error "Only little-endian host is supported" +#endif
[snip]
diff --git a/tools/prelink-riscv.inc b/tools/prelink-riscv.inc new file mode 100644 index 0000000..f7f9596 --- /dev/null +++ b/tools/prelink-riscv.inc
Needs license information, thanks!
2017-12-22 23:31 GMT+08:00 Tom Rini trini@konsulko.com:
On Fri, Dec 22, 2017 at 03:44:26PM +0800, Andes wrote:
From: Rick Chen rick@andestech.com
Add prelink-riscv to arrange .rela.dyn and .rela.got in compile time.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com
Makefile | 4 ++ tools/Makefile | 1 + tools/prelink-riscv.c | 91 ++++++++++++++++++++++++++++++++++++++++++ tools/prelink-riscv.inc | 101 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 197 insertions(+), 0 deletions(-) create mode 100644 tools/prelink-riscv.c create mode 100644 tools/prelink-riscv.inc
diff --git a/Makefile b/Makefile index c573ddb..bb6416f 100644 --- a/Makefile +++ b/Makefile @@ -1264,6 +1264,10 @@ ifeq ($(CONFIG_KALLSYMS),y) $(call cmd,u-boot__) common/system_map.o endif
+ifeq ($(CONFIG_RISCV),y)
@tools/prelink-riscv $@ 0+endif
quiet_cmd_sym ?= SYM $@ cmd_sym ?= $(OBJDUMP) -t $< > $@ u-boot.sym: u-boot FORCE diff --git a/tools/Makefile b/tools/Makefile index 4d32fe5..571f571 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -185,6 +185,7 @@ hostprogs-$(CONFIG_KIRKWOOD) += kwboot hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot hostprogs-y += proftool hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela +hostprogs-$(CONFIG_RISCV) += prelink-riscv
hostprogs-y += fdtgrep fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o diff --git a/tools/prelink-riscv.c b/tools/prelink-riscv.c new file mode 100644 index 0000000..dd099a9 --- /dev/null +++ b/tools/prelink-riscv.c @@ -0,0 +1,91 @@ +#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__ +#error "Only little-endian host is supported" +#endif
[snip]
diff --git a/tools/prelink-riscv.inc b/tools/prelink-riscv.inc new file mode 100644 index 0000000..f7f9596 --- /dev/null +++ b/tools/prelink-riscv.inc
Needs license information, thanks!
I will add license information in the next version. Thanks for reviewing.
Rick
-- Tom
From: Rick Chen rick@andestech.com
Run hello_world successfully.
U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800)
DRAM: 1 GiB MMC: mmc@f0e00000: 0 SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB In: serial@f0300000 Out: serial@f0300000 Err: serial@f0300000 Net: Warning: mac@e0100000 (eth0) using random MAC address - 0a:47:9b:f8:b4:f2 eth0: mac@e0100000 RISC-V # mmc rescan RISC-V # fatls mmc 0:1 318907 u-boot-ae250-64.bin 1252 hello_world_ae250_32.bin 328787 u-boot-ae250-32.bin
3 file(s), 0 dir(s)
RISC-V # fatload mmc 0:1 0x600000 hello_world_ae250_32.bin reading hello_world_ae250_32.bin 1252 bytes read in 23 ms (52.7 KiB/s) RISC-V # go 0x600000 Example expects ABI version 9 Actual U-Boot ABI version 9 Hello World argc = 1 argv[0] = "0x600000" argv[1] = "�#$B@" Hit any key to exit ...
RISC-V #
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com --- examples/standalone/riscv.lds | 41 +++++++++++++++++++++++++++++++++++++++++ examples/standalone/stubs.c | 12 ++++++++++++ 2 files changed, 53 insertions(+), 0 deletions(-) create mode 100644 examples/standalone/riscv.lds
diff --git a/examples/standalone/riscv.lds b/examples/standalone/riscv.lds new file mode 100644 index 0000000..7d8c482 --- /dev/null +++ b/examples/standalone/riscv.lds @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .data : { + __global_pointer$ = . + 0x800; + *(.data) + } + + . = ALIGN(4); + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + __bss_end = .; + + . = ALIGN(4); + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + + _end = .; +} diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 9c7a8c0..fadde66 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -172,6 +172,18 @@ gd_t *global_data; " lwi $r16, [$r16 + (%1)]\n" \ " jr $r16\n" \ : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16"); +#elif defined(CONFIG_RISCV) +/* + * t7 holds the pointer to the global_data. gp is call clobbered. + */ +#define EXPORT_FUNC(f, a, x, ...) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" lw x19, %0(gp)\n" \ +" lw x19, %1(x19)\n" \ +" jr x19\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "x19"); #elif defined(CONFIG_ARC) /* * r25 holds the pointer to the global_data. r10 is call clobbered.
From: Rick Chen rick@andestech.com
Support common commands bdinfo and image format, also modify common generic flow for RISC-V.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com --- arch/Kconfig | 5 +++++ cmd/bdinfo.c | 15 +++++++++++++++ common/board_f.c | 2 +- common/board_r.c | 4 ++-- include/elf.h | 5 +++++ include/image.h | 1 + 6 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig index 0b12ed9..762230c 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -54,6 +54,10 @@ config PPC select HAVE_PRIVATE_LIBGCC select SUPPORT_OF_CONTROL
+config RISCV + bool "riscv architecture" + select SUPPORT_OF_CONTROL + config SANDBOX bool "Sandbox" select BOARD_LATE_INIT @@ -194,3 +198,4 @@ source "arch/sandbox/Kconfig" source "arch/sh/Kconfig" source "arch/x86/Kconfig" source "arch/xtensa/Kconfig" +source "arch/riscv/Kconfig" diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 27ffcd5..c7ebad1 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -417,6 +417,21 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; }
+#elif defined(CONFIG_RISCV) + +int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + bd_t *bd = gd->bd; + + print_num("arch_number", bd->bi_arch_number); + print_bi_boot_params(bd); + print_bi_dram(bd); + print_eth_ip_addr(); + print_baudrate(); + + return 0; +} + #elif defined(CONFIG_ARC)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/common/board_f.c b/common/board_f.c index e46eced..0bdce64 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -218,7 +218,7 @@ static int setup_mon_len(void) gd->mon_len = (ulong)&_end - (ulong)_init; #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) gd->mon_len = CONFIG_SYS_MONITOR_LEN; -#elif defined(CONFIG_NDS32) || defined(CONFIG_SH) +#elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); #elif defined(CONFIG_SYS_MONITOR_BASE) /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ diff --git a/common/board_r.c b/common/board_r.c index 09167c1..2a9df6b 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -126,7 +126,7 @@ static int initr_reloc_global_data(void) { #ifdef __ARM__ monitor_flash_len = _end - __image_copy_start; -#elif defined(CONFIG_NDS32) +#elif defined(CONFIG_NDS32) || defined(CONFIG_RISCV) monitor_flash_len = (ulong)&_end - (ulong)&_start; #elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2) monitor_flash_len = (ulong)&__init_end - gd->relocaddr; @@ -704,7 +704,7 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_DM initr_dm, #endif -#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) +#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) board_init, /* Setup chipselects */ #endif /* diff --git a/include/elf.h b/include/elf.h index aaecac7..fe2128f 100644 --- a/include/elf.h +++ b/include/elf.h @@ -613,6 +613,11 @@ unsigned long elf_hash(const unsigned char *name); #define R_AARCH64_NONE 0 /* No relocation. */ #define R_AARCH64_RELATIVE 1027 /* Adjust by program base. */
+/* RISC-V relocations */ +#define R_RISCV_32 1 +#define R_RISCV_64 2 +#define R_RISCV_RELATIVE 3 + #ifndef __ASSEMBLER__ int valid_elf_image(unsigned long addr); #endif diff --git a/include/image.h b/include/image.h index a128a62..a41a836 100644 --- a/include/image.h +++ b/include/image.h @@ -190,6 +190,7 @@ enum { IH_ARCH_ARC, /* Synopsys DesignWare ARC */ IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ IH_ARCH_XTENSA, /* Xtensa */ + IH_ARCH_RISCV, /* RISC-V */
IH_ARCH_COUNT, };
On Fri, Dec 22, 2017 at 03:44:28PM +0800, Andes wrote:
From: Rick Chen rick@andestech.com
Support common commands bdinfo and image format, also modify common generic flow for RISC-V.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com
Reviewed-by: Tom Rini trini@konsulko.com
From: Rick Chen rick@andestech.com
Add documents to describe NX25 and AE250. Also update other documents for RISC-V.
Signed-off-by: Rick Chen rick@andestech.com Signed-off-by: Rick Chen rickchen36@gmail.com Signed-off-by: Greentime Hu green.hu@gmail.com --- README | 19 +++++++- doc/README.NX25 | 46 ++++++++++++++++ doc/README.ae250 | 137 +++++++++++++++++++++++++++++++++++++++++++++++++ doc/README.standalone | 1 + 4 files changed, 202 insertions(+), 1 deletions(-) create mode 100644 doc/README.NX25 create mode 100644 doc/README.ae250
diff --git a/README b/README index 93c7ea9..33bff88 100644 --- a/README +++ b/README @@ -143,6 +143,7 @@ Directory Hierarchy: /nios2 Files generic to Altera NIOS2 architecture /openrisc Files generic to OpenRISC architecture /powerpc Files generic to PowerPC architecture + /riscv Files generic to RISC-V architecture /sandbox Files generic to HW-independent "sandbox" /sh Files generic to SH architecture /x86 Files generic to x86 architecture @@ -3511,7 +3512,7 @@ Low Level (hardware related) configuration options: globally (CONFIG_CMD_MEMORY).
- CONFIG_SKIP_LOWLEVEL_INIT - [ARM, NDS32, MIPS only] If this variable is defined, then certain + [ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain low level initializations (like setting up the memory controller) are omitted and/or U-Boot does not relocate itself into RAM. @@ -4965,6 +4966,22 @@ On NDS32, the following registers are used: NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope, or current versions of GCC may "optimize" the code too much.
+On RISC-V, the following registers are used: + + x0: hard-wired zero (zero) + x1: return address (ra) + x2: stack pointer (sp) + x3: global pointer (gp) + x4: thread pointer (tp) + x5: link register (t0) + x8: frame pointer (fp) + x10-x11: arguments/return values (a0-1) + x12-x17: arguments (a2-7) + x28-31: temporaries (t3-6) + pc: program counter (pc) + + ==> U-Boot will use gp to hold a pointer to the global data + Memory Management: ------------------
diff --git a/doc/README.NX25 b/doc/README.NX25 new file mode 100644 index 0000000..9f054e5 --- /dev/null +++ b/doc/README.NX25 @@ -0,0 +1,46 @@ +NX25 is Andes CPU IP to adopt RISC-V architecture. + +Features +======== + +CPU Core + - 5-stage in-order execution pipeline + - Hardware Multiplier + - radix-2/radix-4/radix-16/radix-256/fast + - Hardware Divider + - Optional branch prediction + - Machine mode and optional user mode + - Optional performance monitoring + +ISA + - RV64I base integer instructions + - RVC for 16-bit compressed instructions + - RVM for multiplication and division instructions + +Memory subsystem + - I & D local memory + - Size: 4KB to 16MB + - Memory subsyetem soft-error protection + - Protection scheme: parity-checking or error-checking-and-correction (ECC) + - Automatic hardware error correction + +Bus + - Interface Protocol + - Synchronous AHB (32-bit/64-bit data-width), or + - Synchronous AXI4 (64-bit data-width) + +Power management + - Wait for interrupt (WFI) mode + +Debug + - Configurable number of breakpoints: 2/4/8 + - External Debug Module + - AHB slave port + - External JTAG debug transport module + +Platform Level Interrupt Controller (PLIC) + - AHB slave port + - Configurable number of interrupts: 1-1023 + - Configurable number of interrupt priorities: 3/7/15/63/127/255 + - Configurable number of targets: 1-16 + - Preempted interrupt priority stack diff --git a/doc/README.ae250 b/doc/README.ae250 new file mode 100644 index 0000000..a80bb39 --- /dev/null +++ b/doc/README.ae250 @@ -0,0 +1,137 @@ +Andes Technology SoC AE250 +=========================== + +AE250 is the mainline SoC produced by Andes Technology using NX25 CPU core +base on RISC-V architecture. + +AE250 has integrated both AHB and APB bus and many periphals for application +and product development. + +NX25-AE250 +========= + +NX25-AE250 is the SoC with AE250 hardcore CPU. + +Configurations +============== + +CONFIG_SKIP_LOWLEVEL_INIT: + If you want to boot this system from SPI ROM and bypass e-bios (the + other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT + in "include/configs/nx25-ae250.h". + +Build and boot steps +==================== + +build: +1. Prepare the toolchains and make sure the $PATH to toolchains is correct. +2. Use `make nx25-ae250_defconfig` in u-boot root to build the image. + +Verification +==================== + +Target +==================== +1. startup +2. relocation +3. timer driver +4. uart driver +5. mac driver +6. mmc driver +7. spi driver + +Steps +==================== +1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram. +2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom. +3. Ping a server by mac driver +4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver. +5. Burn this u-boot image to spi rom by spi driver +6. Re-boot u-boot from spi flash with power off and power on. + +Messages +==================== +U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800) + +DRAM: 1 GiB +MMC: mmc@f0e00000: 0 +SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB +In: serial@f0300000 +Out: serial@f0300000 +Err: serial@f0300000 +Net: +Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10 +eth0: mac@e0100000 + +RISC-V # version +U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800) + +riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0 +GNU ld (GNU Binutils) 2.29 + +RISC-V # setenv ipaddr 10.0.4.200 ; +RISC-V # setenv serverip 10.0.4.97 ; +RISC-V # ping 10.0.4.97 ; +Using mac@e0100000 device +host 10.0.4.97 is alive + +RISC-V # mmc rescan +RISC-V # fatls mmc 0:1 + 318907 u-boot-ae250-64.bin + 1252 hello_world_ae250_32.bin + 328787 u-boot-ae250-32.bin + +3 file(s), 0 dir(s) + +RISC-V # sf probe 0:0 50000000 0 +SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB + +RISC-V # sf test 0x100000 0x1000 +SPI flash test: +0 erase: 36 ticks, 111 KiB/s 0.888 Mbps +1 check: 29 ticks, 137 KiB/s 1.096 Mbps +2 write: 40 ticks, 100 KiB/s 0.800 Mbps +3 read: 20 ticks, 200 KiB/s 1.600 Mbps +Test passed +0 erase: 36 ticks, 111 KiB/s 0.888 Mbps +1 check: 29 ticks, 137 KiB/s 1.096 Mbps +2 write: 40 ticks, 100 KiB/s 0.800 Mbps +3 read: 20 ticks, 200 KiB/s 1.600 Mbps + +RISC-V # fatload mmc 0:1 0x600000 u-boot-ae250-32.bin +reading u-boot-ae250-32.bin +328787 bytes read in 324 ms (990.2 KiB/s) + +RISC-V # sf erase 0x0 0x51000 +SF: 331776 bytes @ 0x0 Erased: OK + +RISC-V # sf write 0x600000 0x0 0x50453 +device 0 offset 0x0, size 0x50453 +SF: 328787 bytes @ 0x0 Written: OK + +RISC-V # crc32 0x600000 0x50453 +crc32 for 00600000 ... 00650452 ==> 692dc44a + +RISC-V # crc32 0x80000000 0x50453 +crc32 for 80000000 ... 80050452 ==> 692dc44a +RISC-V # + +*** power-off and power-on, this U-Boot is booted from spi flash *** + +U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800) + +DRAM: 1 GiB +MMC: mmc@f0e00000: 0 +SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB +In: serial@f0300000 +Out: serial@f0300000 +Err: serial@f0300000 +Net: +Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5 +eth0: mac@e0100000 +RISC-V # + +TODO +==================== + +Boot bbl and riscv-linux diff --git a/doc/README.standalone b/doc/README.standalone index 659a12f..28ebde1 100644 --- a/doc/README.standalone +++ b/doc/README.standalone @@ -58,6 +58,7 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications: Blackfin 0x00001000 0x00001000 NDS32 0x00300000 0x00300000 Nios II 0x02000000 0x02000000 + RISC-V 0x00600000 0x00600000
For example, the "hello world" application may be loaded and executed on a PowerPC board with the following commands:
participants (3)
-
Andes -
Tom Rini -
陳建志