Here are the changes you requested, if there is anything else that needs to be changed don't hesitate to let me know.

Thanks, Matthew

Wolfgang Denk wrote:

Dear Matthew,

in message 3ED51F22.4010608@arlut.utexas.edu you wrote:

...

Here are some patches..

u-boot-startchg.patch: this patches changes what I was talking about in the message (whoops, it was an html message) I sent to the list earlier.

Please add an entry for the CHANGELOG file.

...

u-boot-utxchg.patch: these are changes for our board that brings u-boot upto date with what we have here

If you have any questions don't hesistate to ask.

I hesitate to apply a patch that throws out copyright notes:

...

+++ ./board/utx8245/flash.c 2003-05-28 14:38:13.002469000 -0500 @@ -2,11 +2,6 @@

• (C) Copyright 2001
• Wolfgang Denk, DENX Software Engineering, wd@denx.de.

• • (C) Copyright 2002
• • Gregory E. Allen, gallen@arlut.utexas.edu
• • Matthew E. Karger, karger@arlut.utexas.edu
• • Applied Research Laboratories, The University of Texas at Austin

• See file CREDITS for list of people who contributed to this
• project.

Can you please explain if this is really OK?

Also, the CHANGELOG entry is missing.

And please don't add trailing white space. Please clean up, and re-submit.

Best regards,

Wolfgang Denk

diff -purN ../u-boot/CHANGELOG ./CHANGELOG --- ../u-boot/CHANGELOG 2003-05-28 03:06:31.000000000 -0500 +++ ./CHANGELOG 2003-05-28 17:20:24.418516000 -0500 @@ -2,6 +2,10 @@ Changes since U-Boot 0.3.1: ======================================================================

+* Patch by Matthew McClintock, 28 May 2003 + cpu/mpc824x/start.S: no longer relocate code from sdram if we are in debug + mode. + * Fix data abort exception handling for arm920t CPU

* Fix alignment problems with flash driver for TRAB board diff -purN ../u-boot/cpu/mpc824x/start.S ./cpu/mpc824x/start.S --- ../u-boot/cpu/mpc824x/start.S 2003-05-22 17:53:09.000000000 -0500 +++ ./cpu/mpc824x/start.S 2003-05-28 17:17:52.089171000 -0500 @@ -542,7 +542,7 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */

mr r3, r5 /* Destination Address */ -#ifdef DEBUG +#ifdef CFG_BOOT_IMAGE_FROM_RAM lis r4, CFG_SDRAM_BASE@h /* Source Address */ ori r4, r4, CFG_SDRAM_BASE@l #else

diff -purN ../u-boot/board/utx8245/flash.c ./board/utx8245/flash.c --- ../u-boot/board/utx8245/flash.c 2002-11-02 18:47:04.000000000 -0600 +++ ./board/utx8245/flash.c 2003-05-28 17:02:39.023203000 -0500 @@ -45,25 +45,17 @@ # endif #endif

-#define FLASH_BANK_SIZE 0x200000 +#define FLASH_BANK_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ #define MAIN_SECT_SIZE 0x10000 #define SECT_SIZE_32KB 0x8000 #define SECT_SIZE_8KB 0x2000

flash_info_t flash_info[CFG_MAX_FLASH_BANKS];

-static int write_word (flash_info_t *info, ulong dest, ulong data); - -static __inline__ unsigned long get_msr(void) -{ unsigned long msr; - __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); -} +static int write_data (flash_info_t *info, ulong dest, ulong *data); +static void write_via_fpu(vu_long *addr, ulong *data); +static __inline__ unsigned long get_msr(void); +static __inline__ void set_msr(unsigned long msr);

/*flash command address offsets*/ #define ADDR0 (0x555) @@ -73,39 +65,87 @@ static __inline__ void set_msr(unsigned #define FLASH_WORD_SIZE unsigned char

/*---------------------------------------------------------------------*/ -/*#define DEBUG_FLASH 1 */ +//#define DEBUG_FLASH 1

/*---------------------------------------------------------------------*/

unsigned long flash_init(void) { - int i, j; - ulong size = 0; + int i; /* flash bank counter */ + int j; /* flash device sector counter */ + int k; /* flash size calculation loop counter */ + int N; /* pow(2,N) is flash size, but we don't have <math.h> */ + ulong total_size = 0, device_size = 1; unsigned char manuf_id, device_id;

- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { vu_char *addr = (vu_char *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);

- addr[0x555] = 0xAA; /* 3 cycles to read device info. See */ - addr[0x2AA] = 0x55; /* AM29LV116D datasheet for list of */ - addr[0x555] = 0x90; /* available commands. */ - - manuf_id = addr[0]; - device_id = addr[1]; - + addr[0x555] = 0xAA; /* get manuf/device info command */ + addr[0x2AA] = 0x55; /* 3-cycle command */ + addr[0x555] = 0x90; + + manuf_id = addr[0]; /* read back manuf/device info */ + device_id = addr[1]; + + addr[0x55] = 0x98; /* CFI command */ + N = addr[0x27]; /* read back device_size = pow(2,N) */ + + for (k = 0; k < N; k++) /* calculate device_size = pow(2,N) */ + device_size *= 2; + + flash_info[i].size = device_size; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + #if defined DEBUG_FLASH printf("manuf_id = %x, device_id = %x\n", manuf_id, device_id); -#endif - - if ( (manuf_id == (uchar)(AMD_MANUFACT)) && - ( device_id == AMD_ID_LV116DT)) +#endif + /* find out what kind of flash we are using */ + if ((manuf_id == (uchar)(AMD_MANUFACT)) + && (device_id == AMD_ID_LV033C)) + { + flash_info[i].flash_id = ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | + (FLASH_AM033C & FLASH_TYPEMASK); + + /* set individual sector start addresses */ + for (j = 0; j < flash_info[i].sector_count; j++) + { + flash_info[i].start[j] = (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE); + } + } + + else if ((manuf_id == (uchar)(AMD_MANUFACT)) && + (device_id == AMD_ID_LV116DT)) { flash_info[i].flash_id = ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | - (AMD_ID_LV116DT & FLASH_TYPEMASK); - } else { + (FLASH_AM160T & FLASH_TYPEMASK); + + /* set individual sector start addresses */ + for (j = 0; j < flash_info[i].sector_count; j++) + { + flash_info[i].start[j] = (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE); + + if (j < (CFG_MAX_FLASH_SECT - 3)) + flash_info[i].start[j] = (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE); + + else if (j == (CFG_MAX_FLASH_SECT - 3)) + flash_info[i].start[j] = (flash_info[i].start[j-1] + + SECT_SIZE_32KB); + + else + flash_info[i].start[j] = (flash_info[i].start[j-1] + + SECT_SIZE_8KB); + } + } + + else + { flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = (long)0xFFFFFFFF; + addr[0] = 0xFFFFFFFF; goto Done; }

@@ -113,32 +153,11 @@ unsigned long flash_init(void) printf ("flash_id = 0x%08lX\n", flash_info[i].flash_id); #endif

- addr[0] = (long)0xFFFFFFFF; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + addr[0] = 0xFFFFFFFF; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - - for (j = 0; j < flash_info[i].sector_count; j++) - { - - if (j < (CFG_MAX_FLASH_SECT - 3) ) - - flash_info[i].start[j] = CFG_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE; - - else if (j == (CFG_MAX_FLASH_SECT - 3) ) - - flash_info[i].start[j] = flash_info[i].start[j-1] + SECT_SIZE_32KB; - - - else - - flash_info[i].start[j] = flash_info[i].start[j-1] + SECT_SIZE_8KB; - - } - - size += flash_info[i].size; + + total_size += flash_info[i].size; }

/* Protect monitor and environment sectors @@ -149,12 +168,12 @@ unsigned long flash_init(void) #endif

#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) - flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); #endif

Done: - return size; + return total_size; }

/*----------------------------------------------------------------------- @@ -179,12 +198,13 @@ void flash_print_info(flash_info_t *info

switch(info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: type = "AM29F040B (512K * 8, uniform sector size)"; break; + case FLASH_AM033C: type = "AM29LV033C (32 Mbit, uniform sector size)"; break; + case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break; + case FLASH_AM040: type = "AM29F040B (512K * 8, uniform sector size)"; break; case FLASH_AM400B: type = "AM29LV400B (4 Mbit, bottom boot sect)"; break; case FLASH_AM400T: type = "AM29LV400T (4 Mbit, top boot sector)"; break; case FLASH_AM800B: type = "AM29LV800B (8 Mbit, bottom boot sect)"; break; case FLASH_AM800T: type = "AM29LV800T (8 Mbit, top boot sector)"; break; - case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break; case FLASH_AM320B: type = "AM29LV320B (32 Mbit, bottom boot sect)"; break; case FLASH_AM320T: type = "AM29LV320T (32 Mbit, top boot sector)"; break; case FLASH_STM800AB: type = "M29W800AB (8 Mbit, bottom boot sect)"; break; @@ -284,7 +304,7 @@ int flash_erase (flash_info_t *info, int sh8b = 3; else sh8b = 0; - + /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts();

@@ -295,9 +315,9 @@ int flash_erase (flash_info_t *info, int addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;

/* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) + for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) + if (info->protect[sect] == 0) { /* not protected */ addr = (FLASH_WORD_SIZE *)(info->start[0] + ( (info->start[sect] - info->start[0]) << sh8b)); @@ -312,10 +332,10 @@ int flash_erase (flash_info_t *info, int addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ udelay(30000); /* wait 30 ms */ } - + else addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - + l_sect = sect; } } @@ -489,3 +509,22 @@ static int write_word (flash_info_t *inf } /*----------------------------------------------------------------------- */ +static void write_via_fpu(vu_long *addr, ulong *data) +{ + __asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data)); + __asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr)); +} +/*----------------------------------------------------------------------- + */ +static __inline__ unsigned long get_msr(void) +{ + unsigned long msr; + + __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void set_msr(unsigned long msr) +{ + __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); +} diff -purN ../u-boot/board/utx8245/utx8245.c ./board/utx8245/utx8245.c --- ../u-boot/board/utx8245/utx8245.c 2003-02-14 05:22:40.000000000 -0600 +++ ./board/utx8245/utx8245.c 2003-05-28 17:01:45.413479000 -0500 @@ -30,6 +30,7 @@ #include <mpc824x.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/mmu.h> #include <pci.h>

#define SAVE_SZ 32 @@ -53,9 +54,15 @@ long int initdram(int board_type) volatile ulong *addr; ulong save[SAVE_SZ]; ulong val, ret = 0; - +/* + write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP), + ( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE)); + + write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP), + ( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE)); +*/ for (i=0; i<SAVE_SZ; i++) {save[i] = 0;} /* clear table */ - + for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { addr = (volatile ulong *)base + cnt; @@ -78,7 +85,7 @@ long int initdram(int board_type) addr = (volatile ulong *)base + cnt; val = *addr; *addr = save[--i]; - if (val != ~cnt) + if (val != ~cnt) { ulong new_bank0_end = cnt * sizeof(long) - 1; ulong mear1 = mpc824x_mpc107_getreg(MEAR1); @@ -110,16 +117,16 @@ Done: */

static struct pci_config_table pci_utx8245_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, +#ifndef CONFIG_PCI_PNP + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR, - PCI_FIREWIRE_MEMADDR, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR, + PCI_FIREWIRE_MEMADDR, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, -#endif /*CONFIG_PCI_PNP*/ +#endif /*CONFIG_PCI_PNP*/ { } };

@@ -129,12 +136,20 @@ static void pci_utx8245_fixup_irq(struct if (PCI_DEV(dev) == 11) /* assign serial interrupt line 9 (int25) to FireWire */ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25); - + else if (PCI_DEV(dev) == 12) /* assign serial interrupt line 8 (int24) to Ethernet */ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24); + + else if (PCI_DEV(dev) == 14) + /* assign serial interrupt line 0 (int16) to PMC slot 0 */ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16); + + else if (PCI_DEV(dev) == 15) + /* assign serial interrupt line 1 (int17) to PMC slot 1 */ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17); } - + static struct pci_controller utx8245_hose = { #ifndef CONFIG_PCI_PNP config_table: pci_utx8245_config_table, @@ -146,7 +161,7 @@ static struct pci_controller utx8245_hos void pci_init_board (void) { pci_mpc824x_init(&utx8245_hose); - + icache_enable(); }

diff -purN ../u-boot/CHANGELOG ./CHANGELOG --- ../u-boot/CHANGELOG 2003-05-28 03:06:31.000000000 -0500 +++ ./CHANGELOG 2003-05-28 17:10:19.951060000 -0500 @@ -2,6 +2,9 @@ Changes since U-Boot 0.3.1: ======================================================================

+* Patch by Matthew McClintock, 28 May 2003 + minor patches for utx8245 + * Fix data abort exception handling for arm920t CPU

* Fix alignment problems with flash driver for TRAB board diff -purN ../u-boot/include/configs/utx8245.h ./include/configs/utx8245.h --- ../u-boot/include/configs/utx8245.h 2002-11-02 18:34:34.000000000 -0600 +++ ./include/configs/utx8245.h 2003-05-28 17:01:45.433479000 -0500 @@ -51,16 +51,39 @@ #define CONFIG_UTX8245 1 #define DEBUG 1

+#define CONFIG_IDENT_STRING " [UTX5] " + #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 57600 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }

-#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTDELAY 2 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" -#define CONFIG_BOOTCOMMAND "bootm FF920000 FF800000" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */ -#define CONFIG_ETHADDR 41:52:4c:61:00:01 /* MAC address */ -#define CONFIG_SERVERIP 10.8.17.105 +#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */ +#define CONFIG_SERVERIP 10.8.17.105 /* Spree */ +#define CFG_TFTP_LOADADDR 10000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=FFA00000\0" \ + "ramdisk_addr=FF800000\0" \ + "ppcboot_startaddr=FFB00000\0" \ + "ppcboot_endaddr=FFB2FFFF\0" \ + "nfsargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/nfs rw \ +nfsroot=$(nfsrootip):$(rootpath) ip=dhcp\0" \ + "ramargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/ram0\0" \ + "smargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/mtdblock1 ro\0" \ + "fwargs=setenv bootargs console=ttyS0,$(baudrate) root=/dev/sda2 ro\0" \ + "nfsboot=run nfsargs;bootm $(kernel_addr)\0" \ + "ramboot=run ramargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "smboot=run smargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "fwboot=run fwargs;bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "update_ppcboot=tftp $(loadaddr) /bdi2000/./ppcboot.bin;protect off \ +$(ppcboot_startaddr) $(ppcboot_endaddr);era $(ppcboot_startaddr) \ +$(ppcboot_endaddr);cp.b $(loadaddr) $(ppcboot_startaddr) $(filesize);\ +protect on $(ppcboot_startaddr) $(ppcboot_endaddr)" + #define CONFIG_ENV_OVERWRITE

#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \ @@ -70,7 +93,8 @@ | CFG_CMD_IMI | CFG_CMD_CACHE \ | CFG_CMD_RUN | CFG_CMD_ECHO \ | CFG_CMD_REGINFO | CFG_CMD_NET\ - | CFG_CMD_DHCP) + | CFG_CMD_DHCP | CFG_CMD_I2C \ + | CFG_CMD_DATE)

/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -80,9 +104,9 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */

/* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) @@ -101,12 +125,20 @@ #define CONFIG_PCI_SCAN_SHOW #define CONFIG_NET_MULTI #define CONFIG_EEPRO100 +#define CONFIG_EEPRO100_SROM_WRITE + +#define PCI_ENET0_IOADDR 0xF0000000 +#define PCI_ENET0_MEMADDR 0xF0000000

-#define PCI_ENET0_IOADDR 0x80000000 +#define PCI_FIREWIRE_IOADDR 0xF1000000 +#define PCI_FIREWIRE_MEMADDR 0xF1000000 +/* +#define PCI_ENET0_IOADDR 0xFE000000 #define PCI_ENET0_MEMADDR 0x80000000 + #define PCI_FIREWIRE_IOADDR 0x81000000 #define PCI_FIREWIRE_MEMADDR 0x81000000 - +*/

/*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -114,12 +146,13 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 /* amount of SDRAM */ +#define CFG_MAX_RAM_SIZE 0x10000000 /* 256MB */ +//#define CFG_VERY_BIG_RAM 1

- -/* even though FLASHP_BASE is FF800000, with 2MB on RCS0, the - * reset vector is actually located at FF800100, but the 8245 - * takes care of us. +/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector + * is actually located at FFF00100. Therefore, PPCBoot is + * physically located at 0xFFB0_0000, but is also mirrored at + * 0xFFF0_0000. */ #define CFG_RESET_ADDRESS 0xFFF00100

@@ -130,33 +163,41 @@ #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */

-/*#define CFG_DRAM_TEST 1 */ +//#define CFG_DRAM_TEST 1 #define CFG_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */ -#define CFG_MEMTEST_END 0x0ff8ffa8 /* in SDRAM, skips exception */ - /* vectors and U-Boot */ +#define CFG_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */ + /* vectors and PPCBoot */

/*-------------------------------------------------------------------- * Definitions for initial stack pointer and data area *------------------------------------------------------------------*/ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for */ +#define CFG_INIT_DATA_SIZE 128 /* Size in bytes reserved for */ /* initial data */ #define CFG_INIT_RAM_ADDR 0x40000000 #define CFG_INIT_RAM_END 0x1000 +#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) +#define CFG_GBL_DATA_SIZE 128 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*-------------------------------------------------------------------- * NS16550 Configuration *------------------------------------------------------------------*/ -#define CFG_NS16550 +#define CFG_NS16550 #define CFG_NS16550_SERIAL

#define CFG_NS16550_REG_SIZE 1

-#define CFG_NS16550_CLK get_bus_freq(0) +#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2) +# define CFG_NS16550_CLK get_bus_freq(0) +#else +# define CFG_NS16550_CLK 33000000 +#endif

#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) #define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) +#define CFG_NS16550_COM3 0xFF000000 +#define CFG_NS16550_COM4 0xFF000008

/*-------------------------------------------------------------------- * Low Level Configuration Settings @@ -168,60 +209,83 @@ #define CONFIG_SYS_CLK_FREQ 33000000 #define CFG_HZ 1000

-#define CFG_ETH_DEV_FN 0x7800 -#define CFG_ETH_IOBASE 0x00104000 +//#define CFG_ETH_DEV_FN 0x7800 +//#define CFG_ETH_IOBASE 0x00104000 + +/*-------------------------------------------------------------------- + * I2C Configuration + *------------------------------------------------------------------*/ +#if 1 +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#endif

+#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */ + /* Philips PCF8563 RTC */ +#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */

/*-------------------------------------------------------------------- * Memory Control Configuration Register values * - see sec. 4.12 of MPC8245 UM *------------------------------------------------------------------*/

-/* MCCR1 */ +/**** MCCR1 ****/ #define CFG_ROMNAL 0 -#define CFG_ROMFAL 2 /* (tacc=70ns)*mem_freq - 2 */ -#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */ -#define CFG_BANK1_ROW 2 /* bit count */ -#define CFG_BANK2_ROW 0 -#define CFG_BANK3_ROW 0 -#define CFG_BANK4_ROW 0 +#define CFG_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2, + mem_freq = 100MHz */ + +#define CFG_BANK7_ROW 0 /* SDRAM bank 7-0 row address */ +#define CFG_BANK6_ROW 0 /* bit count */ #define CFG_BANK5_ROW 0 -#define CFG_BANK6_ROW 0 -#define CFG_BANK7_ROW 0 +#define CFG_BANK4_ROW 0 +#define CFG_BANK3_ROW 0 +#define CFG_BANK2_ROW 0 +#define CFG_BANK1_ROW 2 +#define CFG_BANK0_ROW 2

-/* MCCR2, refresh interval clock cycles */ +/**** MCCR2, refresh interval clock cycles ****/ #define CFG_REFINT 480 /* 33 MHz SDRAM clock was 480 */

-/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4 */ +/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ #define CFG_BSTOPRE 1023 /* burst to precharge[0..9], */ /* sets open page interval */ - -/* MCCR3 */ -#define CFG_REFREC 5 /* Refresh to activate interval, trc */ - -/* MCCR4 */ + +/**** MCCR3 ****/ +#define CFG_REFREC 7 /* Refresh to activate interval, trc */ + +/**** MCCR4 ****/ #define CFG_PRETOACT 2 /* trp */ -#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + tdrl */ +#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */ #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */ #define CFG_ACTORW 2 /* trcd min */ #define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ #define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 +#define CFG_EXTROM 0 /* we don't need extended ROM space */ #define CFG_REGDIMM 0

/* calculate according to formula in sec. 6-22 of 8245 UM */ #define CFG_PGMAX 50 /* how long the 8245 retains the */ /* currently accessed page in memory */ /* was 45 */ - + #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */ - /* bottom 3 bits MUST be 0 */ + /* bits 7,6, and 3-0 MUST be 0 */

+#if 0 #define CFG_DLL_MAX_DELAY 0x04 +#else +#define CFG_DLL_MAX_DELAY 0 +#endif +#if 0 /* need for 33MHz SDRAM */ #define CFG_DLL_EXTEND 0x80 +#else +#define CFG_DLL_EXTEND 0 +#endif #define CFG_PCI_HOLD_DEL 0x20 - +

/* Memory bank settings. * Only bits 20-29 are actually used from these values to set the @@ -255,29 +319,34 @@ #define CFG_BANK7_END 0x3fffffff #define CFG_BANK7_ENABLE 0

-/*-------------------------------------------------------------------- - * 4.4 - Output Driver Control Register - *------------------------------------------------------------------*/ +//-------------------------------------------------------------------- +// 4.4 - Output Driver Control Register +//-------------------------------------------------------------------- #define CFG_ODCR 0xe5

-/*-------------------------------------------------------------------- - * 4.8 - Error Handling Registers - *------------------------------------------------------------------*/ -#define CFG_ERRENR1 0x11 /* enable SDRAM refresh overflow error */ +//-------------------------------------------------------------------- +// 4.8 - Error Handling Registers +//-------------------------------CFG_SDMODE_BURSTLEN------------------------------------- +#define CFG_ERRENR1 0x11 // enable SDRAM refresh overflow error

/* SDRAM 0-256 MB */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +//#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in dcache */ #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

+ +#define CFG_IBAT2L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT2U (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP) + /* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) +//#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +//#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

-/* Flash, config addrs, etc. */ +/*Flash, config addrs, etc. */ #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

@@ -298,26 +367,30 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */

/*----------------------------------------------------------------------- - * FLASH organization (AMD AM29LV116D) - */ + * FLASH organization + *----------------------------------------------------------------------*/ #define CFG_FLASH_BASE 0xFF800000 +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */

-#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - /* Warning: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ +/* NOTE: environment is not EMBEDDED in the ppcboot code. + It's stored in flash in its own separate sector. */ #define CFG_ENV_IS_IN_FLASH 1

+#if 1 /* AMD AM29LV033C */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ +#define CFG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */ +#define CFG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */ +#else /* AMD AM29LV116D */ +#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */ #define CFG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */ -#define CFG_ENV_SIZE 0x2000 /* Size of the Environment */ +#define CFG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */ +#endif /* #if */ + +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Size of the Environment */ #define CFG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CFG_ENV_SECT_SIZE 0x2000 /* Size of the Environment Sector */

+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */

#if CFG_MONITOR_BASE >= CFG_FLASH_BASE #undef CFG_RAMBOOT