[U-Boot] [PATCH 3/5] jz4740 nand spl files
From: Xiangfu Liu xiangfu@sharism.cc
Signed-off-by: Xiangfu Liu xiangfu@openmobilefree.net --- nand_spl/board/xburst/nanonote/Makefile | 96 +++++++ nand_spl/board/xburst/nanonote/u-boot.lds | 63 +++++ nand_spl/nand_boot_jz4740.c | 395 +++++++++++++++++++++++++++++ 3 files changed, 554 insertions(+), 0 deletions(-) create mode 100644 nand_spl/board/xburst/nanonote/Makefile create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds create mode 100644 nand_spl/nand_boot_jz4740.c
diff --git a/nand_spl/board/xburst/nanonote/Makefile b/nand_spl/board/xburst/nanonote/Makefile new file mode 100644 index 0000000..f5d1eb5 --- /dev/null +++ b/nand_spl/board/xburst/nanonote/Makefile @@ -0,0 +1,96 @@ +# +# (C) Copyright 2006 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +TEXT_BASE = 0x80000000 + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL -O2 + +SOBJS = start.o usbboot.o +COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin + dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1 + cat $< $(nandobj)junk1 > $(nandobj)junk2 + dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3 + cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4 + dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5 + cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6 + dd bs=1024 count=256 if=$(nandobj)junk6 of=$@ + rm -f $(nandobj)junk* + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files +$(obj)start.S: + @rm -f $(obj)start.S + ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S + +$(obj)usbboot.S: + @rm -f $(obj)usbboot.S + ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $(obj)usbboot.S + +$(obj)cpu.c: + @rm -f $(obj)cpu.c + ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $(obj)cpu.c + +$(obj)jz4740.c: + @rm -f $(obj)jz4740.c + ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $(obj)jz4740.c + +$(obj)jz_serial.c: + @rm -f $(obj)jz_serial.c + ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c + +$(obj)nand_boot_jz4740.c: + @rm -f $(obj)nand_boot_jz4740.c + ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/nand_spl/board/xburst/nanonote/u-boot.lds b/nand_spl/board/xburst/nanonote/u-boot.lds new file mode 100644 index 0000000..7042388 --- /dev/null +++ b/nand_spl/board/xburst/nanonote/u-boot.lds @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2005 + * Ingenic Semiconductor, jlwei@ingenic.cn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") + +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/nand_spl/nand_boot_jz4740.c b/nand_spl/nand_boot_jz4740.c new file mode 100644 index 0000000..44fe95d --- /dev/null +++ b/nand_spl/nand_boot_jz4740.c @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2007 Ingenic Semiconductor Inc. + * Author: Peter jlwei@ingenic.cn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> + +#include <asm/jz4740.h> + +#define KEY_U_OUT (32 * 2 + 16) +#define KEY_U_IN (32 * 3 + 19) + +/* + * NAND flash definitions + */ +#define NAND_DATAPORT 0xb8000000 +#define NAND_ADDRPORT 0xb8010000 +#define NAND_COMMPORT 0xb8008000 + +#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1) +#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1)) +#define __nand_ecc_rs_encoding() \ + (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING) +#define __nand_ecc_rs_decoding() \ + (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING) +#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE) +#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF)) +#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF)) +#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n)) +#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n)) +#define __nand_data8() REG8(NAND_DATAPORT) +#define __nand_data16() REG16(NAND_DATAPORT) + +#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) + #define NAND_BUS_WIDTH 8 + #define NAND_ROW_CYCLE 3 +#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2) + #define NAND_BUS_WIDTH 8 + #define NAND_ROW_CYCLE 2 +#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) + #define NAND_BUS_WIDTH 16 + #define NAND_ROW_CYCLE 3 +#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2) + #define NAND_BUS_WIDTH 16 + #define NAND_ROW_CYCLE 2 +#endif + +static inline void __nand_dev_ready(void) +{ + unsigned int timeout = 10000; + while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--); + while (!(REG_GPIO_PXPIN(2) & 0x40000000)); +} + +/* + * NAND flash parameters + */ +static int page_size = 2048; +static int oob_size = 64; +static int ecc_count = 4; +static int page_per_block = 64; +static int bad_block_pos = 0; +static int block_size = 131072; +static unsigned char oob_buf[128] = {0}; + +/* + * External routines + */ +extern void flush_cache_all(void); +extern int serial_init(void); +extern void serial_puts(const char *s); +extern void sdram_init(void); +extern void pll_init(void); +extern void usb_boot(); + +/* + * NAND flash routines + */ +#if NAND_BUS_WIDTH == 16 +static inline void nand_read_buf16(void *buf, int count) +{ + int i; + u16 *p = (u16 *)buf; + + for (i = 0; i < count; i += 2) + *p++ = __nand_data16(); +} +#define nand_read_buf nand_read_buf16 + +#elif NAND_BUS_WIDTH == 8 +static inline void nand_read_buf8(void *buf, int count) +{ + int i; + u8 *p = (u8 *)buf; + + for (i = 0; i < count; i++) + *p++ = __nand_data8(); +} +#define nand_read_buf nand_read_buf8 + +#endif + +/* Correct 1~9-bit errors in 512-bytes data */ +static void rs_correct(unsigned char *dat, int idx, int mask) +{ + int i; + + idx--; + + i = idx + (idx >> 3); + if (i >= 512) + return; + + mask <<= (idx & 0x7); + + dat[i] ^= mask & 0xff; + if (i < 511) + dat[i+1] ^= (mask >> 8) & 0xff; +} + +static int nand_read_oob(int page_addr, uchar *buf, int size) +{ + int col_addr; + if (page_size != 512) + col_addr = page_size; + else { + col_addr = 0; + __nand_dev_ready(); + } + + if (page_size != 512) + /* Send READ0 command */ + __nand_cmd(NAND_CMD_READ0); + else + /* Send READOOB command */ + __nand_cmd(NAND_CMD_READOOB); + + /* Send column address */ + __nand_addr(col_addr & 0xff); + if (page_size != 512) + __nand_addr((col_addr >> 8) & 0xff); + + /* Send page address */ + __nand_addr(page_addr & 0xff); + __nand_addr((page_addr >> 8) & 0xff); + #if defined NAND_ROW_CYCLE && NAND_ROW_CYCLE == 3 + __nand_addr((page_addr >> 16) & 0xff); + #endif + + /* Send READSTART command for 2048 or 4096 ps NAND */ + if (page_size != 512) + __nand_cmd(NAND_CMD_READSTART); + + /* Wait for device ready */ + __nand_dev_ready(); + + /* Read oob data */ + nand_read_buf(buf, size); + if (page_size == 512) + __nand_dev_ready(); + return 0; +} + +static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf) +{ + uchar *databuf = dst, *tmpbuf; + int i, j; + + /* + * Read oob data + */ + nand_read_oob(page_addr, oobbuf, oob_size); + + /* + * Read page data + */ + /* Send READ0 command */ + __nand_cmd(NAND_CMD_READ0); + + /* Send column address */ + __nand_addr(0); + if (page_size != 512) + __nand_addr(0); + + /* Send page address */ + __nand_addr(page_addr & 0xff); + __nand_addr((page_addr >> 8) & 0xff); + #if defined NAND_ROW_CYCLE && NAND_ROW_CYCLE == 3 + __nand_addr((page_addr >> 16) & 0xff); + #endif + + /* Send READSTART command for 2048 or 4096 ps NAND */ + if (page_size != 512) + __nand_cmd(NAND_CMD_READSTART); + + /* Wait for device ready */ + __nand_dev_ready(); + + /* Read page data */ + tmpbuf = databuf; + + for (i = 0; i < ecc_count; i++) { + volatile unsigned char *paraddr = (volatile unsigned char *)EMC_NFPAR0; + unsigned int stat; + + /* Enable RS decoding */ + REG_EMC_NFINTS = 0x0; + __nand_ecc_rs_decoding(); + + /* Read data */ + nand_read_buf((void *)tmpbuf, CONFIG_SYS_NAND_ECCSIZE); + + /* Set PAR values */ + for (j = 0; j < CONFIG_SYS_NAND_ECCBYTES; j++) + *paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*CONFIG_SYS_NAND_ECCBYTES + j]; + + /* Set PRDY */ + REG_EMC_NFECR |= EMC_NFECR_PRDY; + + /* Wait for completion */ + __nand_ecc_decode_sync(); + + /* Disable decoding */ + __nand_ecc_disable(); + + /* Check result of decoding */ + stat = REG_EMC_NFINTS; + if (stat & EMC_NFINTS_ERR) { + /* Error occurred */ + /* serial_puts("Error occurred\n"); */ + if (stat & EMC_NFINTS_UNCOR) { + /* Uncorrectable error occurred */ + /* serial_puts("Uncorrectable error occurred\n"); */ + } else { + unsigned int errcnt, index, mask; + + errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT; + switch (errcnt) { + case 4: + index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT; + mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT; + rs_correct(tmpbuf, index, mask); + /* FALL-THROUGH */ + case 3: + index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT; + mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT; + rs_correct(tmpbuf, index, mask); + /* FALL-THROUGH */ + case 2: + index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT; + mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT; + rs_correct(tmpbuf, index, mask); + /* FALL-THROUGH */ + case 1: + index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT; + mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT; + rs_correct(tmpbuf, index, mask); + break; + default: + break; + } + } + } + tmpbuf += CONFIG_SYS_NAND_ECCSIZE; + } + + return 0; +} + +#ifndef CONFIG_SYS_NAND_BADBLOCK_PAGE +#define CONFIG_SYS_NAND_BADBLOCK_PAGE 0 /* NAND bad block was marked at this page in a block, starting from 0 */ +#endif + +static void nand_load(int offs, int uboot_size, uchar *dst) +{ + int page; + int pagecopy_count; + + __nand_enable(); + + page = offs / page_size; + pagecopy_count = 0; + while (pagecopy_count < (uboot_size / page_size)) { + if (page % page_per_block == 0) { + nand_read_oob(page + CONFIG_SYS_NAND_BADBLOCK_PAGE, oob_buf, oob_size); + if (oob_buf[bad_block_pos] != 0xff) { + page += page_per_block; + /* Skip bad block */ + continue; + } + } + /* Load this page to dst, do the ECC */ + nand_read_page(page, dst, oob_buf); + + dst += page_size; + page++; + pagecopy_count++; + } + + __nand_disable(); +} + +static void jz_nand_init(void) { + /* Optimize the timing of nand */ + REG_EMC_SMCR1 = 0x094c4400; +} + +static void gpio_init(void) +{ + /* + * Initialize SDRAM pins + */ + __gpio_as_sdram_16bit_4720(); + + /* + * Initialize UART0 pins + */ + __gpio_as_uart0(); + __gpio_jtag_to_uart0(); +} + +static int is_usb_boot() +{ + __gpio_as_input(KEY_U_IN); + __gpio_enable_pull(KEY_U_IN); + __gpio_as_output(KEY_U_OUT); + __gpio_clear_pin(KEY_U_OUT); + + if (__gpio_get_pin(KEY_U_IN) == 0) + return 1; + + return 0; +} + +void nand_boot(void) +{ + void (*uboot)(void); + + /* + * Init hardware + */ + gpio_init(); + pll_init(); + + serial_init(); + sdram_init(); + jz_nand_init(); + + serial_puts("\nNAND Boot\n"); + +#if defined(CONFIG_NANONOTE) + if(is_usb_boot()) { + serial_puts("[U] pressed, goto USBBOOT mode\n"); + usb_boot(); + } +#endif + page_size = CONFIG_SYS_NAND_PAGE_SIZE; + block_size = CONFIG_SYS_NAND_BLOCK_SIZE; + page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE; + bad_block_pos = (page_size == 512) ? 5 : 0; + oob_size = page_size / 32; + ecc_count = page_size / CONFIG_SYS_NAND_ECCSIZE; + + /* + * Load U-Boot image from NAND into RAM + */ + nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); + + uboot = (void (*)(void))CONFIG_SYS_NAND_U_BOOT_START; + + serial_puts("Starting U-Boot ...\n"); + + /* Flush caches */ + flush_cache_all(); + + /* Jump to U-Boot image */ + (*uboot)(); +}
From: Xiangfu Liu xiangfu@sharism.cc
Signed-off-by: Xiangfu Liu xiangfu@openmobilefree.net --- drivers/mtd/nand/jz4740_nand.c | 250 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 250 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/jz4740_nand.c
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c new file mode 100644 index 0000000..f661b36 --- /dev/null +++ b/drivers/mtd/nand/jz4740_nand.c @@ -0,0 +1,250 @@ +/* + * Platform independend driver for JZ4740. + * + * Copyright (c) 2007 Ingenic Semiconductor Inc. + * Author: jlwei@ingenic.cn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ +#include <common.h> + +#if defined(CONFIG_CMD_NAND) +#include <nand.h> +#include <asm/io.h> +#include <asm/jz4740.h> + +#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST ) +#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE) + +#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000) +#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000) +#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000) + +#define BIT(x) (1 << (x)) +#define JZ_NAND_ECC_CTRL_ENCODING BIT(3) +#define JZ_NAND_ECC_CTRL_RS BIT(2) +#define JZ_NAND_ECC_CTRL_RESET BIT(1) +#define JZ_NAND_ECC_CTRL_ENABLE BIT(0) + +static struct nand_ecclayout qi_lb60_ecclayout_2gb = { + .eccbytes = 72, + .eccpos = { + 12, 13, 14, 15, 16, 17, 18, 19, + 20, 21, 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32, 33, 34, 35, + 36, 37, 38, 39, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 49, 50, 51, + 52, 53, 54, 55, 56, 57, 58, 59, + 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, + 76, 77, 78, 79, 80, 81, 82, 83}, + .oobfree = { + {.offset = 2, + .length = 10}, + {.offset = 84, + .length = 44}} +}; + +static int is_reading; + +static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_ALE) + this->IO_ADDR_W = JZ_NAND_ADDR_ADDR; + else if (ctrl & NAND_CLE) + this->IO_ADDR_W = JZ_NAND_CMD_ADDR; + else + this->IO_ADDR_W = JZ_NAND_DATA_ADDR; + + if (ctrl & NAND_NCE) + REG_EMC_NFCSR |= EMC_NFCSR_NFCE1; + else + REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int jz_nand_device_ready(struct mtd_info *mtd) +{ + udelay(20); + return (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0; +} + +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + /* + * Don't use "chip" to address the NAND device, + * generate the cs from the address where it is encoded. + */ +} + +static int jz_nand_rs_calculate_ecc(struct mtd_info* mtd, const u_char* dat, + u_char* ecc_code) +{ + uint32_t reg, status; + int i; + volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0; + + if(is_reading) + return 0; + + do { + status = REG_EMC_NFINTS; + } while(!(status & EMC_NFINTS_ENCF)); + + __nand_ecc_disable(); + + for(i = 0; i < 9; i++) + ecc_code[i] = *(paraddr + i); + + return 0; +} + +static void jz_nand_hwctl(struct mtd_info* mtd, int mode) +{ + uint32_t reg; + REG_EMC_NFINTS = 0; + reg = REG_EMC_NFECR; + reg |= JZ_NAND_ECC_CTRL_RESET; + reg |= JZ_NAND_ECC_CTRL_ENABLE; + reg |= JZ_NAND_ECC_CTRL_RS; + + switch(mode) { + case NAND_ECC_READ: + reg &= ~JZ_NAND_ECC_CTRL_ENCODING; + is_reading = 1; + break; + case NAND_ECC_WRITE: + reg |= JZ_NAND_ECC_CTRL_ENCODING; + is_reading = 0; + break; + default: + break; + } + + REG_EMC_NFECR = reg; +} + +/* Correct 1~9-bit errors in 512-bytes data */ +static void jz_rs_correct(unsigned char *dat, int idx, int mask) +{ + int i; + + idx--; + + i = idx + (idx >> 3); + if (i >= 512) + return; + + mask <<= (idx & 0x7); + + dat[i] ^= mask & 0xff; + if (i < 511) + dat[i+1] ^= (mask >> 8) & 0xff; +} + +static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + int k; + uint32_t reg, status; + volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0; + + /* Set PAR values */ + static uint8_t all_ff_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f}; + if (read_ecc[0] == 0xff && + read_ecc[1] == 0xff && + read_ecc[2] == 0xff && + read_ecc[3] == 0xff && + read_ecc[4] == 0xff && + read_ecc[5] == 0xff && + read_ecc[6] == 0xff && + read_ecc[7] == 0xff && + read_ecc[8] == 0xff) { + for (k = 0; k < 9; k++) + *(paraddr + k) = all_ff_ecc[k]; + } else { + + for (k = 0; k < 9; k++) + *(paraddr + k) = read_ecc[k]; + } + /* Set PRDY */ + REG_EMC_NFECR |= EMC_NFECR_PRDY; + + /* Wait for completion */ + do { + status = REG_EMC_NFINTS; + } while (!(status & EMC_NFINTS_DECF)); + + __nand_ecc_disable(); + + /* Check decoding */ + if (status & EMC_NFINTS_ERR) { + if (status & EMC_NFINTS_UNCOR) { + printk("uncorrectable ecc\n"); + while(1); + return -1; + } + + uint32_t errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT; + switch (errcnt) { + case 4: + jz_rs_correct(dat, + (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, + (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); + case 3: + jz_rs_correct(dat, + (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, + (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); + case 2: + jz_rs_correct(dat, + (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, + (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); + case 1: + jz_rs_correct(dat, + (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, + (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); + return errcnt; + default: + break; + } + } + + return 0; +} + +/* + * Main initialization routine + */ +int board_nand_init(struct nand_chip *nand) +{ + /* EMC setup, Set NFE bit */ + REG_EMC_NFCSR |= EMC_NFCSR_NFE1; + REG_EMC_SMCR1 = 0x094c4400; + /* REG_EMC_SMCR3 = 0x04444400; */ + + nand->IO_ADDR_R = JZ_NAND_DATA_ADDR; + nand->IO_ADDR_W = JZ_NAND_DATA_ADDR; + nand->cmd_ctrl = jz_nand_cmd_ctrl; + nand->dev_ready = jz_nand_device_ready; + + nand->ecc.hwctl = jz_nand_hwctl; + nand->ecc.correct = jz_nand_rs_correct_data; + nand->ecc.calculate = jz_nand_rs_calculate_ecc; + nand->ecc.mode = NAND_ECC_HW_OOB_FIRST; + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + nand->ecc.layout = &qi_lb60_ecclayout_2gb; + nand->chip_delay = 50; + + return 0; +} +#endif /* (CONFIG_CMD_NAND) */
From: Xiangfu Liu xiangfu@sharism.cc
Signed-off-by: Xiangfu Liu xiangfu@openmobilefree.net --- board/xburst/nanonote/Makefile | 45 ++++++++ board/xburst/nanonote/config.mk | 31 ++++++ board/xburst/nanonote/nanonote.c | 124 ++++++++++++++++++++++ board/xburst/nanonote/u-boot-nand.lds | 63 +++++++++++ include/configs/nanonote.h | 188 +++++++++++++++++++++++++++++++++ include/configs/qi_lb60.h | 28 +++++ 6 files changed, 479 insertions(+), 0 deletions(-) create mode 100644 board/xburst/nanonote/Makefile create mode 100644 board/xburst/nanonote/config.mk create mode 100644 board/xburst/nanonote/nanonote.c create mode 100644 board/xburst/nanonote/u-boot-nand.lds create mode 100644 include/configs/nanonote.h create mode 100644 include/configs/qi_lb60.h
diff --git a/board/xburst/nanonote/Makefile b/board/xburst/nanonote/Makefile new file mode 100644 index 0000000..a4f6bd0 --- /dev/null +++ b/board/xburst/nanonote/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2006 +# Ingenic Semiconductor, jlwei@ingenic.cn +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xburst/nanonote/config.mk b/board/xburst/nanonote/config.mk new file mode 100644 index 0000000..858e6a2 --- /dev/null +++ b/board/xburst/nanonote/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2006 Qi Hardware, Inc. +# Author: Xiangfu Liu xiangfu.z@gmail.com +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Qi Hardware, Inc. Ben NanoNote (QI_LB60) +# + +ifndef TEXT_BASE +# ROM version +# TEXT_BASE = 0x88000000 + +# RAM version +TEXT_BASE = 0x80100000 +endif diff --git a/board/xburst/nanonote/nanonote.c b/board/xburst/nanonote/nanonote.c new file mode 100644 index 0000000..ef9552a --- /dev/null +++ b/board/xburst/nanonote/nanonote.c @@ -0,0 +1,124 @@ +/* + * Authors: Xiangfu Liu xiangfu.z@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 3 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <command.h> +#include <asm/mipsregs.h> +#include <asm/jz4740.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void gpio_init(void) +{ + /* + * Initialize NAND Flash Pins + */ + __gpio_as_nand(); + + /* + * Initialize SDRAM pins + */ + __gpio_as_sdram_16bit_4720(); + + /* + * Initialize LCD pins + */ + __gpio_as_lcd_18bit(); + + /* + * Initialize MSC pins + */ + __gpio_as_msc(); + + /* + * Initialize Other pins + */ + unsigned int i; + for (i = 0; i < 7; i++){ + __gpio_as_input(GPIO_KEYIN_BASE + i); + __gpio_enable_pull(GPIO_KEYIN_BASE + i); + } + + for (i = 0; i < 8; i++) { + __gpio_as_output(GPIO_KEYOUT_BASE + i); + __gpio_clear_pin(GPIO_KEYOUT_BASE + i); + } + + /* enable the TP4, TP5 as UART0 */ + __gpio_jtag_to_uart0(); + + /* + * Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the + * same gpio, init the gpio as uart0 cause a keyboard bug. so for + * end user we disable the uart0 + */ + if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){ + /* if pressed [S] */ + printf("[S] pressed, enable UART0\n"); + gd->boot_option |= BOOT_WITH_ENABLE_UART; + __gpio_as_uart0(); + } else { + __gpio_as_input(GPIO_KEYIN_8); + __gpio_enable_pull(GPIO_KEYIN_8); + } + + __gpio_as_output(GPIO_AUDIO_POP); + __gpio_set_pin(GPIO_AUDIO_POP); + + __gpio_as_output(GPIO_LCD_CS); + __gpio_clear_pin(GPIO_LCD_CS); + + __gpio_as_output(GPIO_AMP_EN); + __gpio_clear_pin(GPIO_AMP_EN); + + __gpio_as_output(GPIO_SDPW_EN); + __gpio_disable_pull(GPIO_SDPW_EN); + __gpio_clear_pin(GPIO_SDPW_EN); + + __gpio_as_input(GPIO_SD_DETECT); + __gpio_disable_pull(GPIO_SD_DETECT); + + __gpio_as_input(GPIO_USB_DETECT); + __gpio_enable_pull(GPIO_USB_DETECT); + + if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) { + printf("[M] pressed, boot from sd card\n"); + gd->boot_option |= BOOT_FROM_SDCARD; + } +} + +static void cpm_init(void) +{ + __cpm_stop_ipu(); + __cpm_stop_cim(); + __cpm_stop_i2c(); + __cpm_stop_ssi(); + __cpm_stop_uart1(); + __cpm_stop_sadc(); + __cpm_stop_uhc(); + __cpm_stop_udc(); + __cpm_stop_aic1(); +/* __cpm_stop_aic2();*/ +} + +void board_early_init(void) +{ + gpio_init(); + cpm_init(); +} + +/* U-Boot common routines */ + +int checkboard (void) +{ + printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %d MHz)\n", + gd->cpu_clk / 1000000); + + return 0; /* success */ +} diff --git a/board/xburst/nanonote/u-boot-nand.lds b/board/xburst/nanonote/u-boot-nand.lds new file mode 100644 index 0000000..a15a96e --- /dev/null +++ b/board/xburst/nanonote/u-boot-nand.lds @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2006 + * Ingenic Semiconductor, jlwei@ingenic.cn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") + +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/include/configs/nanonote.h b/include/configs/nanonote.h new file mode 100644 index 0000000..648202e --- /dev/null +++ b/include/configs/nanonote.h @@ -0,0 +1,188 @@ +/* + * Authors: Xiangfu Liu xiangfu.z@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 3 of the License, or (at your option) any later version. + */ + +/* + * This file contains the configuration parameters for the NanoNote. + */ +#ifndef __CONFIG_NANONOTE_H +#define __CONFIG_NANONOTE_H + +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_JZSOC 1 /* Jz SoC */ +#define CONFIG_JZ4740 1 /* Jz4740 SoC */ +#define CONFIG_NAND_JZ4740 +#define CONFIG_NANONOTE + +#define BOOT_FROM_SDCARD 1 +#define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */ + +#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ +#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ +#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ +#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED + +#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */ +#define CONFIG_BAUDRATE 57600 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */ +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL) +#define CONFIG_BOOTDELAY 0 +/* + * Command line configuration. + */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ + +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SAVEENV /* saveenv */ +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ +#define CONFIG_CMD_SOURCE /* "source" command support */ +#define CONFIG_CMD_NAND + +/* + * Serial download configuration + */ +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "NanoNote# " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ + +#define CONFIG_SYS_MALLOC_LEN 896 * 1024 +#define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80800000 + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ + +/* + * NAND FLASH configuration + */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +/* NAND Boot config code */ +#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 + +#define NANONOTE_NAND_SIZE 2 /* if board nand flash is 1GB, set to 1 + * if board nand flash is 2GB, set to 2 + * for change the PAGE_SIZE and BLOCK_SIZE + * will delete when there is no 1GB flash + */ + +#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE) +/* nand chip block size */ +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10) +/* nand bad block was marked at this page in a block, start from 0 */ +#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127 +/* ECC offset position in oob area, default value is 6 if it isn't defined */ +#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE) +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 9 + +#define CONFIG_SYS_NAND_BASE 0xB8000000 +#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/ + +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 8k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 8kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + */ +#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */ +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +/* Start NUB from this addr*/ + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */ +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ + +#define CONFIG_ENV_SIZE (4 << 10) +#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE) + +/* in board/nanonote/config.mk TEXT_BAS = 0x88000000 */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE + +/* + * SDRAM Info. + */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* + * Cache Configuration + */ +#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * GPIO definition + */ +#define GPIO_LCD_CS (2 * 32 + 21) +#define GPIO_AMP_EN (3 * 32 + 4) + +#define GPIO_SDPW_EN (3 * 32 + 2) +#define GPIO_SD_DETECT (3 * 32 + 0) + +#define GPIO_BUZZ_PWM (3 * 32 + 27) +#define GPIO_USB_DETECT (3 * 32 + 28) + +#define GPIO_AUDIO_POP (1 * 32 + 29) +#define GPIO_COB_TEST (1 * 32 + 30) + +#define GPIO_KEYOUT_BASE (2 * 32 + 10) +#define GPIO_KEYIN_BASE (3 * 32 + 18) +#define GPIO_KEYIN_8 (3 * 32 + 26) + +#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */ +#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */ + +#define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */ +#define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */ +#define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */ +#endif /* __CONFIG_NANONOTE_H */ diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h new file mode 100644 index 0000000..29ec805 --- /dev/null +++ b/include/configs/qi_lb60.h @@ -0,0 +1,28 @@ +#ifndef __CONFIG_QI_LB60_H +#define __CONFIG_QI_LB60_H + +#include <configs/nanonote.h> + +#define CONFIG_QI_LB60 1 + +//#define DEBUG +#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" +#define CONFIG_BOOTARGSFROMSD "mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait" +#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" +#define CONFIG_BOOTCOMMANDFROMSD "mmc init; ext2load mmc 0 0x80600000 /boot/uImage; bootm" + +/* SDRAM paramters */ +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ +#define SDRAM_ROW 13 /* Row address: 11 to 13 */ +#define SDRAM_COL 9 /* Column address: 8 to 12 */ +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ + +/* SDRAM Timings, unit: ns */ +#define SDRAM_TRAS 45 /* RAS# Active Time */ +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ +#define SDRAM_TPC 20 /* RAS# Precharge Time */ +#define SDRAM_TRWL 7 /* Write Latency Time */ +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ + +#endif
Dear Xiangfu Liu,
In message 1289446657-12499-6-git-send-email-xiangfu@openmobilefree.net you wrote:
From: Xiangfu Liu xiangfu@sharism.cc
Signed-off-by: Xiangfu Liu xiangfu@openmobilefree.net
board/xburst/nanonote/Makefile | 45 ++++++++ board/xburst/nanonote/config.mk | 31 ++++++ board/xburst/nanonote/nanonote.c | 124 ++++++++++++++++++++++ board/xburst/nanonote/u-boot-nand.lds | 63 +++++++++++ include/configs/nanonote.h | 188 +++++++++++++++++++++++++++++++++ include/configs/qi_lb60.h | 28 +++++ 6 files changed, 479 insertions(+), 0 deletions(-) create mode 100644 board/xburst/nanonote/Makefile create mode 100644 board/xburst/nanonote/config.mk create mode 100644 board/xburst/nanonote/nanonote.c create mode 100644 board/xburst/nanonote/u-boot-nand.lds create mode 100644 include/configs/nanonote.h create mode 100644 include/configs/qi_lb60.h
Entry to MAINTAINERS mssing.
Entry to boards.cfg missing.
Best regards,
Wolfgang Denk
On Thu, 11 Nov 2010 11:37:36 +0800 Xiangfu Liu xiangfu@openmobilefree.net wrote:
From: Xiangfu Liu xiangfu@sharism.cc
Signed-off-by: Xiangfu Liu xiangfu@openmobilefree.net
drivers/mtd/nand/jz4740_nand.c | 250 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 250 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/jz4740_nand.c
Same comments as on nand_spl.
Also, this looks like the type of controller that could work with the standard nand_boot.c -- is there something preventing that?
-Scott
Dear Xiangfu Liu,
In message 1289446657-12499-4-git-send-email-xiangfu@openmobilefree.net you wrote:
From: Xiangfu Liu xiangfu@sharism.cc
Signed-off-by: Xiangfu Liu xiangfu@openmobilefree.net
nand_spl/board/xburst/nanonote/Makefile | 96 +++++++ nand_spl/board/xburst/nanonote/u-boot.lds | 63 +++++ nand_spl/nand_boot_jz4740.c | 395 +++++++++++++++++++++++++++++ 3 files changed, 554 insertions(+), 0 deletions(-) create mode 100644 nand_spl/board/xburst/nanonote/Makefile create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds create mode 100644 nand_spl/nand_boot_jz4740.c
You need to rework the splitting of your code into commits - as is, these patches make no sense to me. Please re-read http://www.denx.de/wiki/view/U-Boot/Patches#General_Patch_Submission_Rules
diff --git a/nand_spl/nand_boot_jz4740.c b/nand_spl/nand_boot_jz4740.c new file mode 100644
...
+#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1) +#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1)) +#define __nand_ecc_rs_encoding() \
- (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
+#define __nand_ecc_rs_decoding() \
- (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING)
+#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE) +#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF)) +#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF)) +#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n)) +#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n)) +#define __nand_data8() REG8(NAND_DATAPORT) +#define __nand_data16() REG16(NAND_DATAPORT)
You seem to have a tendency to use "__" a lot in front of indentifiers. The C standard says:
-- All identifiers that begin with an underscore and either an uppercase letter or another underscore are always reserved for any use.
-- All identifiers that begin with an underscore are always reserved for use as identifiers with file scope in both the ordinary and tag name spaces.
Please recheck your identifier names with this in mind.
As mentioned before, this code needs to be converted to use I/O accessors instead of these REG*() volatile pointer accesses.
Both comments apply globally.
...
/* Check result of decoding */stat = REG_EMC_NFINTS;if (stat & EMC_NFINTS_ERR) {/* Error occurred *//* serial_puts("Error occurred\n"); */if (stat & EMC_NFINTS_UNCOR) {/* Uncorrectable error occurred *//* serial_puts("Uncorrectable error occurred\n"); */} else {unsigned int errcnt, index, mask;errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;switch (errcnt) {case 4:index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;rs_correct(tmpbuf, index, mask);/* FALL-THROUGH */case 3:index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;rs_correct(tmpbuf, index, mask);/* FALL-THROUGH */case 2:index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;rs_correct(tmpbuf, index, mask);/* FALL-THROUGH */case 1:index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;rs_correct(tmpbuf, index, mask);break;
Lines too long.
I stop reviewing here.
Please fix the code, and resubmit.
Thanks.
Best regards,
Wolfgang Denk
On Thu, 11 Nov 2010 11:37:35 +0800 Xiangfu Liu xiangfu@openmobilefree.net wrote:
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
- dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
- cat $< $(nandobj)junk1 > $(nandobj)junk2
- dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
- cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
- dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
- cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
- dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
- rm -f $(nandobj)junk*
Why do you need all this?
+#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1) +#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1)) +#define __nand_ecc_rs_encoding() \
- (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
+#define __nand_ecc_rs_decoding() \
- (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING)
+#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE) +#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF)) +#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF)) +#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n)) +#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n)) +#define __nand_data8() REG8(NAND_DATAPORT) +#define __nand_data16() REG16(NAND_DATAPORT)
Drop the leading underscores.
Use I/O accessors.
Consider making some of these inline functions -- or just open-coding for the really simple ones.
+#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3)
- #define NAND_BUS_WIDTH 8
- #define NAND_ROW_CYCLE 3
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
- #define NAND_BUS_WIDTH 8
- #define NAND_ROW_CYCLE 2
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3)
- #define NAND_BUS_WIDTH 16
- #define NAND_ROW_CYCLE 3
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
- #define NAND_BUS_WIDTH 16
- #define NAND_ROW_CYCLE 2
+#endif
+static inline void __nand_dev_ready(void) +{
- unsigned int timeout = 10000;
- while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
- while (!(REG_GPIO_PXPIN(2) & 0x40000000));
+}
Hmm, why a timeout here and not on any of the other spin loops?
+/*
- NAND flash parameters
- */
+static int page_size = 2048; +static int oob_size = 64; +static int ecc_count = 4; +static int page_per_block = 64; +static int bad_block_pos = 0; +static int block_size = 131072;
You initialize these here, and then you set them to other constant values in nand_boot(). And then you test them for specific values later.
What's going on? If you're not dynamically detecting these, then have them be constants (either #defines or "static const int"). It will allow the compiler to generate smaller code.
+static unsigned char oob_buf[128] = {0};
Be careful, this may still go into the BSS even with the assignment. Is the BSS getting cleared in the SPL boot code on this platform? Do you actually rely on it being zero initially?
Either way, the assignment doesn't do much.
+/*
- External routines
- */
+extern void flush_cache_all(void); +extern int serial_init(void); +extern void serial_puts(const char *s); +extern void sdram_init(void); +extern void pll_init(void); +extern void usb_boot();
Get these from the appropriate header file.
/* Error occurred *//* serial_puts("Error occurred\n"); */if (stat & EMC_NFINTS_UNCOR) {/* Uncorrectable error occurred *//* serial_puts("Uncorrectable error occurred\n"); */
Why is this commented out?
If it's for space concerns, the strings could be shrunk and still get a message out.
} else {unsigned int errcnt, index, mask;errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;switch (errcnt) {case 4:index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;rs_correct(tmpbuf, index, mask);/* FALL-THROUGH */case 3:index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;rs_correct(tmpbuf, index, mask);/* FALL-THROUGH */case 2:index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;rs_correct(tmpbuf, index, mask);/* FALL-THROUGH */case 1:index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;rs_correct(tmpbuf, index, mask);break;default:break;}
Please keep lines under 80 columns. Consider factoring this chunk out to its own function.
}}tmpbuf += CONFIG_SYS_NAND_ECCSIZE;- }
- return 0;
+}
+#ifndef CONFIG_SYS_NAND_BADBLOCK_PAGE +#define CONFIG_SYS_NAND_BADBLOCK_PAGE 0 /* NAND bad block was marked at this page in a block, starting from 0 */ +#endif
This isn't really an aspect of the controller, but of the flash chip. Many flash chips can have bad block markers in the first or second page of a block.
+static void nand_load(int offs, int uboot_size, uchar *dst) +{
- int page;
- int pagecopy_count;
- __nand_enable();
- page = offs / page_size;
- pagecopy_count = 0;
- while (pagecopy_count < (uboot_size / page_size)) {
Round up if uboot_size is not aligned? Any reason not to take the basic loop logic from nand_boot.c?
if (page % page_per_block == 0) {nand_read_oob(page + CONFIG_SYS_NAND_BADBLOCK_PAGE, oob_buf, oob_size);if (oob_buf[bad_block_pos] != 0xff) {page += page_per_block;/* Skip bad block */continue;}
On 16-bit NAND isn't the bad-block marker 16-bit?
}/* Load this page to dst, do the ECC */nand_read_page(page, dst, oob_buf);dst += page_size;page++;pagecopy_count++;- }
- __nand_disable();
+}
+static void jz_nand_init(void) {
Brace on its own line.
- /* Optimize the timing of nand */
- REG_EMC_SMCR1 = 0x094c4400;
+}
+static void gpio_init(void) +{
- /*
* Initialize SDRAM pins*/- __gpio_as_sdram_16bit_4720();
- /*
* Initialize UART0 pins*/- __gpio_as_uart0();
- __gpio_jtag_to_uart0();
+}
+static int is_usb_boot() +{
- __gpio_as_input(KEY_U_IN);
- __gpio_enable_pull(KEY_U_IN);
- __gpio_as_output(KEY_U_OUT);
- __gpio_clear_pin(KEY_U_OUT);
- if (__gpio_get_pin(KEY_U_IN) == 0)
return 1;- return 0;
+}
+void nand_boot(void) +{
- void (*uboot)(void);
- /*
* Init hardware*/- gpio_init();
- pll_init();
- serial_init();
- sdram_init();
- jz_nand_init();
- serial_puts("\nNAND Boot\n");
+#if defined(CONFIG_NANONOTE)
- if(is_usb_boot()) {
Space after "if".
serial_puts("[U] pressed, goto USBBOOT mode\n");usb_boot();- }
+#endif
I wonder how much of the above stuff belongs in nand_boot(), versus a board file. This file should focus on the NAND controller.
- page_size = CONFIG_SYS_NAND_PAGE_SIZE;
- block_size = CONFIG_SYS_NAND_BLOCK_SIZE;
- page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
- bad_block_pos = (page_size == 512) ? 5 : 0;
- oob_size = page_size / 32;
- ecc_count = page_size / CONFIG_SYS_NAND_ECCSIZE;
- /*
* Load U-Boot image from NAND into RAM*/- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
Consider adding support for CONFIG_NAND_ENV_DST.
-Scott
participants (3)
-
Scott Wood -
Wolfgang Denk -
Xiangfu Liu