[U-Boot-Users] [PATCH] Fix MPC8544DS PCIe3 scsi.
From: Ed Swarthout ed.swarthout@freescale.com
Increase PCIe 3 Memory region to 8M to fix scsi invalid port number:
SCSI: scanning bus for devices... Invaild port number 1 Invaild port number 2 Invaild port number 3
Signed-off-by: Ed Swarthout ed.swarthout@freescale.com ---
d64ee908 reduced PCIe 3 region by too much. With this fix I get 0xb010c000 assigned to bar5.
board/freescale/mpc8544ds/init.S | 2 +- include/configs/MPC8544DS.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index 900c368..ca1b5d5 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -237,6 +237,6 @@ law_entry:
/* contains both PCIE3 MEM & IO space */ .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M) + .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M) 4: entry_end diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 746f360..ba5aa00 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -308,9 +308,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* controller 3, direct to uli, tgtid 3, Base address b000 */ #define CFG_PCIE3_MEM_BASE 0xb0000000 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE -#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */ +#define CFG_PCIE3_MEM_SIZE 0x00800000 /* 8M of 16M LAW */ #define CFG_PCIE3_IO_BASE 0x00000000 -#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ +#define CFG_PCIE3_IO_PHYS 0xb0800000 /* reuse mem LAW */ #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
On Aug 20, 2007, at 3:03 AM, Ed Swarthout wrote:
From: Ed Swarthout ed.swarthout@freescale.com
Increase PCIe 3 Memory region to 8M to fix scsi invalid port number:
SCSI: scanning bus for devices... Invaild port number 1 Invaild port number 2 Invaild port number 3
Signed-off-by: Ed Swarthout ed.swarthout@freescale.com
d64ee908 reduced PCIe 3 region by too much. With this fix I get 0xb010c000 assigned to bar5.
board/freescale/mpc8544ds/init.S | 2 +- include/configs/MPC8544DS.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)
I don't understand why this is needed. It seems like something more fundamental in the u-boot allocator if it can't handle all the devices in 1M of memory space. No devices memory space requirement is greater than 4k and there are only 5 or 6 of them.
- k
On Mon, 20 Aug 2007, Kumar Gala wrote:
I don't understand why this is needed. It seems like something more fundamental in the u-boot allocator if it can't handle all the devices in 1M of memory space. No devices memory space requirement is greater than 4k and there are only 5 or 6 of them.
This 'hack' seems to workaround the issue in slightly better way. Not sure if we can do anything better.
The problem is pciauto_setup_device() getting called from fsl_pci_init.c is allocating memory space it doesn't need.
- k
diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1084dc6..193343b 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -54,6 +54,7 @@ fsl_pci_init(struct pci_controller *hose) u8 temp8; int r; int bridge; + unsigned long bus_lower_temp; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; pci_dev_t dev = PCI_BDF(busno,0,0);
@@ -131,8 +132,11 @@ fsl_pci_init(struct pci_controller *hose) }
/* Call setup to allocate PCSRBAR window */ + bus_lower_temp = hose->pci_mem->bus_lower; pciauto_setup_device(hose, dev, 1, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + hose->pci_mem->bus_lower = bus_lower_temp; + #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c
From: Ed Swarthout Ed.Swarthout@freescale.com
CPU physical address space was being wasted by allocating a PCSRBAR PCI inbound region to it's memory space.
As a rule, PCSRBAR should be left alone since it does not affect transactions from self and other masters may have changed it.
Signed-off-by: Ed Swarthout ed.swarthout@freescale.com ---
Was: {PATCH] Fix MPC8544DS PCIe3 scsi.
This fixes the MPC8544DS scsi error:
SCSI: scanning bus for devices... Invaild port number 1 Invaild port number 2 Invaild port number 3
when not enough PCIe3 memory space is available for allocation.
This replaces k's temp hack.
drivers/fsl_pci_init.c | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1084dc6..3a13eea 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -130,9 +130,14 @@ fsl_pci_init(struct pci_controller *hose)
}
- /* Call setup to allocate PCSRBAR window */ - pciauto_setup_device(hose, dev, 1, hose->pci_mem, + /* Use generic setup_device to initialize standard pci regs, + * but do not allocate any windows since any BAR found (such + * as PCSRBAR) is not in this cpu's memory space. + */ + + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + #ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
On Aug 20, 2007, at 11:55 PM, Ed Swarthout wrote:
From: Ed Swarthout Ed.Swarthout@freescale.com
CPU physical address space was being wasted by allocating a PCSRBAR PCI inbound region to it's memory space.
As a rule, PCSRBAR should be left alone since it does not affect transactions from self and other masters may have changed it.
Signed-off-by: Ed Swarthout ed.swarthout@freescale.com
Acked-off-by: Kumar Gala galak@kernel.crashing.org
- k
In message 11876721332262-git-send-email-ed.swarthout@hwdebug.com you wrote:
From: Ed Swarthout Ed.Swarthout@freescale.com
CPU physical address space was being wasted by allocating a PCSRBAR PCI inbound region to it's memory space.
As a rule, PCSRBAR should be left alone since it does not affect transactions from self and other masters may have changed it.
Signed-off-by: Ed Swarthout ed.swarthout@freescale.com
Applied, thanks.
Best regards,
Wolfgang Denk
In message Pine.LNX.4.64.0708200942240.25897@blarg.am.freescale.net you wrote:
On Mon, 20 Aug 2007, Kumar Gala wrote:
I don't understand why this is needed. It seems like something more fundamental in the u-boot allocator if it can't handle all the devices in 1M of memory space. No devices memory space requirement is greater than 4k and there are only 5 or 6 of them.
This 'hack' seems to workaround the issue in slightly better way. Not sure if we can do anything better.
The problem is pciauto_setup_device() getting called from fsl_pci_init.c is allocating memory space it doesn't need.
- k
diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1084dc6..193343b 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c
...
What's the state of this? Will it go into the MPC85xx custodian tree?
Best regards,
Wolfgang Denk
On 8/28/07, Wolfgang Denk wd@denx.de wrote:
In message Pine.LNX.4.64.0708200942240.25897@blarg.am.freescale.net
diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1084dc6..193343b 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c
...
What's the state of this? Will it go into the MPC85xx custodian tree?
Yes, I will send you a pull request tonight, assuming all goes well.
Andy
On Tuesday 28 August 2007 19:07, Wolfgang Denk wrote:
diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1084dc6..193343b 100644
...
What's the state of this? Will it go into the MPC85xx custodian tree?
No, please discard. It is superseeded with:
Re: [U-Boot-Users] [PATCH] fsl_pci_init - Remove self PCSRBAR allocation
which you have just applied.
Thanks, -EdS
On Aug 28, 2007, at 7:07 PM, Wolfgang Denk wrote:
In message <Pine.LNX. 4.64.0708200942240.25897@blarg.am.freescale.net> you wrote:
On Mon, 20 Aug 2007, Kumar Gala wrote:
I don't understand why this is needed. It seems like something more fundamental in the u-boot allocator if it can't handle all the devices in 1M of memory space. No devices memory space requirement is greater than 4k and there are only 5 or 6 of them.
This 'hack' seems to workaround the issue in slightly better way. Not sure if we can do anything better.
The problem is pciauto_setup_device() getting called from fsl_pci_init.c is allocating memory space it doesn't need.
- k
diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index 1084dc6..193343b 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c
...
What's the state of this? Will it go into the MPC85xx custodian tree?
This was a hack, Ed's version "fsl_pci_init - Remove self PCSRBAR allocation" is cleaner and show replace this version that happened to go in via the MPC85xx custodian tree.
- k
This reverts commit 9468e680. Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient.
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com --- drivers/fsl_pci_init.c | 4 +--- 1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c index a4ce458..3a13eea 100644 --- a/drivers/fsl_pci_init.c +++ b/drivers/fsl_pci_init.c @@ -54,7 +54,6 @@ fsl_pci_init(struct pci_controller *hose) u8 temp8; int r; int bridge; - unsigned long bus_lower_temp; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; pci_dev_t dev = PCI_BDF(busno,0,0);
@@ -135,10 +134,9 @@ fsl_pci_init(struct pci_controller *hose) * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. */ - bus_lower_temp = hose->pci_mem->bus_lower; + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); - hose->pci_mem->bus_lower = bus_lower_temp;
#ifndef CONFIG_PCI_NOSCAN printf (" Scanning PCI bus %02x\n", hose->current_busno);
In message 11884587771354-git-send-email-Ed.Swarthout@freescale.com you wrote:
This reverts commit 9468e680. Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient.
Signed-off-by: Ed Swarthout Ed.Swarthout@freescale.com
Applied, thanks.
Best regards,
Wolfgang Denk
Dear Andy,
in message 11875970313708-git-send-email-ed.swarthout@hwdebug.com Ed Swarthout wrote:
From: Ed Swarthout ed.swarthout@freescale.com
Increase PCIe 3 Memory region to 8M to fix scsi invalid port number:
SCSI: scanning bus for devices... Invaild port number 1 Invaild port number 2 Invaild port number 3
Signed-off-by: Ed Swarthout ed.swarthout@freescale.com
What about this one? Will you send me a pull request for the MPC85xx tree soon, or should I pick this up direclty, or should I ignore it?
Best regards,
Wolfgang Denk
participants (6)
-
Andy Fleming -
Ed Swarthout -
Ed Swarthout -
Ed Swarthout -
Kumar Gala -
Wolfgang Denk