[U-Boot] [PATCH 1/3] video: mb862xx: fix coding style and remove dead code
Signed-off-by: Anatolij Gustschin agust@denx.de --- drivers/video/mb862xx.c | 217 +++++++++++++++++++++++++---------------------- 1 files changed, 114 insertions(+), 103 deletions(-)
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index 01eda55..7bc3c9b 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -37,6 +37,7 @@ #if defined(CONFIG_POST) #include <post.h> #endif + /* * Graphic Device */ @@ -65,74 +66,73 @@ unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; #define rd_io in32r #define wr_io out32r #else -#define rd_io(addr) in_be32((volatile unsigned*)(addr)) -#define wr_io(addr,val) out_be32((volatile unsigned*)(addr), (val)) +#define rd_io(addr) in_be32((volatile unsigned *)(addr)) +#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val)) #endif
-#define HOST_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fc0000 + (off))) -#define HOST_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fc0000 + (off)), (val)) -#define DISP_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fd0000 + (off))) -#define DISP_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fd0000 + (off)), (val)) -#define DE_RD_REG(off) rd_io((pGD->dprBase + (off))) -#define DE_WR_REG(off, val) wr_io((pGD->dprBase + (off)), (val)) +#define HOST_RD_REG(off) rd_io((dev->frameAdrs + 0x01fc0000 + (off))) +#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + 0x01fc0000 + (off)), \ + (val)) +#define DISP_RD_REG(off) rd_io((dev->frameAdrs + 0x01fd0000 + (off))) +#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + 0x01fd0000 + (off)), \ + (val)) +#define DE_RD_REG(off) rd_io((dev->dprBase + (off))) +#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
#if defined(CONFIG_VIDEO_CORALP) -#define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x8400)), (val)) +#define DE_WR_FIFO(val) wr_io((dev->dprBase + (0x8400)), (val)) #else -#define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x04a0)), (val)) +#define DE_WR_FIFO(val) wr_io((dev->dprBase + (0x04a0)), (val)) #endif
-#define L0PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2))) -#define L0PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)), (val)) -#define L1PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2))) -#define L1PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)), (val)) -#define L2PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2))) -#define L2PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)), (val)) -#define L3PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2))) -#define L3PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)), (val)) +#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + 0x01fd0400 + \ + ((idx) << 2)), (val))
-static void gdc_sw_reset(void) +static void gdc_sw_reset (void) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + GraphicDevice *dev = &mb862xx; + HOST_WR_REG (0x002c, 0x00000001); udelay (500); video_hw_init (); }
-static void de_wait(void) +static void de_wait (void) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + GraphicDevice *dev = &mb862xx; int lc = 0x10000;
- /* Sync with software writes to framebuffer, - try to reset if engine locked */ + /* + * Sync with software writes to framebuffer, + * try to reset if engine locked + */ while (DE_RD_REG (0x0400) & 0x00000131) if (lc-- < 0) { gdc_sw_reset (); - printf ("gdc reset done after drawing engine lock...\n"); + printf ("gdc reset done after drawing engine lock.\n"); break; } }
-static void de_wait_slots(int slots) +static void de_wait_slots (int slots) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + GraphicDevice *dev = &mb862xx; int lc = 0x10000;
/* Wait for free fifo slots */ while (DE_RD_REG (0x0408) < slots) if (lc-- < 0) { gdc_sw_reset (); - printf ("gdc reset done after drawing engine lock...\n"); + printf ("gdc reset done after drawing engine lock.\n"); break; } }
#if !defined(CONFIG_VIDEO_CORALP) -static void board_disp_init(void) +static void board_disp_init (void) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + GraphicDevice *dev = &mb862xx; const gdc_regs *regs = board_get_regs ();
while (regs->index) { @@ -147,69 +147,69 @@ static void board_disp_init(void) */ static void de_init (void) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; - int cf = (pGD->gdfBytesPP == 1) ? 0x0000 : 0x8000; + GraphicDevice *dev = &mb862xx; + int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
- pGD->dprBase = pGD->frameAdrs + 0x01ff0000; + dev->dprBase = dev->frameAdrs + 0x01ff0000;
/* Setup mode and fbbase, xres, fg, bg */ de_wait_slots (2); DE_WR_FIFO (0xf1010108); DE_WR_FIFO (cf | 0x0300); DE_WR_REG (0x0440, 0x0000); - DE_WR_REG (0x0444, pGD->winSizeX); + DE_WR_REG (0x0444, dev->winSizeX); DE_WR_REG (0x0480, 0x0000); DE_WR_REG (0x0484, 0x0000); /* Reset clipping */ DE_WR_REG (0x0454, 0x0000); - DE_WR_REG (0x0458, pGD->winSizeX); + DE_WR_REG (0x0458, dev->winSizeX); DE_WR_REG (0x045c, 0x0000); - DE_WR_REG (0x0460, pGD->winSizeY); + DE_WR_REG (0x0460, dev->winSizeY);
/* Clear framebuffer using drawing engine */ de_wait_slots (3); DE_WR_FIFO (0x09410000); DE_WR_FIFO (0x00000000); - DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX); + DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX); /* sync with SW access to framebuffer */ de_wait (); }
#if defined(CONFIG_VIDEO_CORALP) -unsigned int pci_video_init(void) +unsigned int pci_video_init (void) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + GraphicDevice *dev = &mb862xx; pci_dev_t devbusfn;
- if ((devbusfn = pci_find_devices(supported, 0)) < 0) - { + if ((devbusfn = pci_find_devices (supported, 0)) < 0) { printf ("PCI video controller not found!\n"); return 0; }
/* PCI setup */ - pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs); - pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs); + pci_write_config_dword (devbusfn, PCI_COMMAND, + (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs); + dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
- if (pGD->frameAdrs == 0) { + if (dev->frameAdrs == 0) { printf ("PCI config: failed to get base address\n"); return 0; }
- pGD->pciBase = pGD->frameAdrs; + dev->pciBase = dev->frameAdrs;
/* Setup clocks and memory mode for Coral-P Eval. Board */ HOST_WR_REG (0x0038, 0x00090000); udelay (200); HOST_WR_REG (0xfffc, 0x11d7fa13); udelay (100); - return pGD->frameAdrs; + return dev->frameAdrs; }
unsigned int card_init (void) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + GraphicDevice *dev = &mb862xx; unsigned int cf, videomode, div = 0; unsigned long t1, hsync, vsync; char *penv; @@ -217,11 +217,10 @@ unsigned int card_init (void) struct ctfb_res_modes *res_mode; struct ctfb_res_modes var_mode;
- memset (pGD, 0, sizeof (GraphicDevice)); + memset (dev, 0, sizeof (GraphicDevice));
- if (!pci_video_init ()) { + if (!pci_video_init ()) return 0; - }
printf ("CoralP\n");
@@ -229,7 +228,7 @@ unsigned int card_init (void) videomode = 0x310; /* get video mode via environment */ if ((penv = getenv ("videomode")) != NULL) { - /* deceide if it is a string */ + /* decide if it is a string */ if (penv[0] <= '9') { videomode = (int) simple_strtoul (penv, NULL, 16); tmp = 1; @@ -237,28 +236,28 @@ unsigned int card_init (void) } else { tmp = 1; } + if (tmp) { - /* parameter are vesa modes */ - /* search params */ + /* parameter are vesa modes, search params */ for (i = 0; i < VESA_MODES_COUNT; i++) { if (vesa_modes[i].vesanr == videomode) break; } if (i == VESA_MODES_COUNT) { - printf ("\tno VESA Mode found, switching to mode 0x%x \n", videomode); + printf ("\tno VESA Mode found, fallback to mode 0x%x\n", + videomode); i = 0; } - res_mode = - (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; + res_mode = (struct ctfb_res_modes *) + &res_mode_init[vesa_modes[i].resindex]; if (vesa_modes[i].resindex > 2) { - printf ("\tUnsupported resolution, switching to default\n"); + printf ("\tUnsupported resolution, using default\n"); bpp = vesa_modes[1].bits_per_pixel; div = fr_div[1]; } bpp = vesa_modes[i].bits_per_pixel; div = fr_div[vesa_modes[i].resindex]; } else { - res_mode = (struct ctfb_res_modes *) &var_mode; bpp = video_get_params (res_mode, penv); } @@ -276,85 +275,94 @@ unsigned int card_init (void) vsync = 1000000000L / t1;
/* fill in Graphic device struct */ - sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, res_mode->yres, bpp, (hsync / 1000), (vsync / 1000)); - printf ("\t%s\n", pGD->modeIdent); - pGD->winSizeX = res_mode->xres; - pGD->winSizeY = res_mode->yres; - pGD->memSize = VIDEO_MEM_SIZE; + printf ("\t%s\n", dev->modeIdent); + dev->winSizeX = res_mode->xres; + dev->winSizeY = res_mode->yres; + dev->memSize = VIDEO_MEM_SIZE;
switch (bpp) { case 8: - pGD->gdfIndex = GDF__8BIT_INDEX; - pGD->gdfBytesPP = 1; + dev->gdfIndex = GDF__8BIT_INDEX; + dev->gdfBytesPP = 1; break; case 15: case 16: - pGD->gdfIndex = GDF_15BIT_555RGB; - pGD->gdfBytesPP = 2; + dev->gdfIndex = GDF_15BIT_555RGB; + dev->gdfBytesPP = 2; break; default: - printf ("\t%d bpp configured, but only 8,15 and 16 supported.\n", bpp); + printf ("\t%d bpp configured, but only 8,15 and 16 supported\n", + bpp); printf ("\tSwitching back to 15bpp\n"); - pGD->gdfIndex = GDF_15BIT_555RGB; - pGD->gdfBytesPP = 2; + dev->gdfIndex = GDF_15BIT_555RGB; + dev->gdfBytesPP = 2; }
/* Setup dot clock (internal pll, division rate) */ DISP_WR_REG (0x0100, div); /* L0 init */ - cf = (pGD->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; - DISP_WR_REG (0x0020, ((pGD->winSizeX * pGD->gdfBytesPP)/64)<<16 | - (pGD->winSizeY-1) | - cf); + cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; + DISP_WR_REG (0x0020, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 | + (dev->winSizeY - 1) | cf); DISP_WR_REG (0x0024, 0x00000000); DISP_WR_REG (0x0028, 0x00000000); DISP_WR_REG (0x002c, 0x00000000); DISP_WR_REG (0x0110, 0x00000000); DISP_WR_REG (0x0114, 0x00000000); - DISP_WR_REG (0x0118, (pGD->winSizeY-1)<<16 | pGD->winSizeX); + DISP_WR_REG (0x0118, (dev->winSizeY - 1) << 16 | dev->winSizeX);
/* Display timing init */ - DISP_WR_REG (0x0004, (pGD->winSizeX+res_mode->left_margin+res_mode->right_margin+res_mode->hsync_len-1)<<16); - DISP_WR_REG (0x0008, (pGD->winSizeX-1) << 16 | (pGD->winSizeX-1)); - DISP_WR_REG (0x000c, (res_mode->vsync_len-1)<<24|(res_mode->hsync_len-1)<<16|(pGD->winSizeX+res_mode->right_margin-1)); - DISP_WR_REG (0x0010, (pGD->winSizeY+res_mode->lower_margin+res_mode->upper_margin+res_mode->vsync_len-1)<<16); - DISP_WR_REG (0x0014, (pGD->winSizeY-1) << 16 | (pGD->winSizeY+res_mode->lower_margin-1)); + DISP_WR_REG (0x0004, (dev->winSizeX + + res_mode->left_margin + + res_mode->right_margin + + res_mode->hsync_len - 1) << 16); + DISP_WR_REG (0x0008, (dev->winSizeX - 1) << 16 | (dev->winSizeX - 1)); + DISP_WR_REG (0x000c, (res_mode->vsync_len - 1) << 24 | + (res_mode->hsync_len - 1) << 16 | + (dev->winSizeX + res_mode->right_margin - 1)); + DISP_WR_REG (0x0010, (dev->winSizeY + res_mode->lower_margin + + res_mode->upper_margin + + res_mode->vsync_len - 1) << 16); + DISP_WR_REG (0x0014, (dev->winSizeY-1) << 16 | + (dev->winSizeY + res_mode->lower_margin - 1)); DISP_WR_REG (0x0018, 0x00000000); - DISP_WR_REG (0x001c, pGD->winSizeY << 16 | pGD->winSizeX); + DISP_WR_REG (0x001c, dev->winSizeY << 16 | dev->winSizeX); /* Display enable, L0 layer */ DISP_WR_REG (0x0100, 0x80010000 | div);
- return pGD->frameAdrs; + return dev->frameAdrs; } #endif
void *video_hw_init (void) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + GraphicDevice *dev = &mb862xx;
printf ("Video: Fujitsu ");
- memset (pGD, 0, sizeof (GraphicDevice)); + memset (dev, 0, sizeof (GraphicDevice));
#if defined(CONFIG_VIDEO_CORALP) - if (card_init () == 0) { - return (NULL); - } + if (card_init () == 0) + return NULL; #else - /* Preliminary init of the onboard graphic controller, - retrieve base address */ - if ((pGD->frameAdrs = board_video_init ()) == 0) { + /* + * Preliminary init of the onboard graphic controller, + * retrieve base address + */ + if ((dev->frameAdrs = board_video_init ()) == 0) { printf ("Controller not found!\n"); - return (NULL); + return NULL; } else - printf("Lime\n"); + printf ("Lime\n"); #endif
de_init ();
#if !defined(CONFIG_VIDEO_CORALP) - board_disp_init(); + board_disp_init (); #endif
#if (defined(CONFIG_LWMON5) || \ @@ -363,15 +371,16 @@ void *video_hw_init (void) board_backlight_switch (1); #endif
- return pGD; + return dev; }
/* * Set a RGB color in the LUT */ -void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b) +void video_set_lut (unsigned int index, unsigned char r, + unsigned char g, unsigned char b) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + GraphicDevice *dev = &mb862xx;
L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); } @@ -379,10 +388,11 @@ void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsign /* * Drawing engine Fill and BitBlt screen region */ -void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, unsigned int dst_y, - unsigned int dim_x, unsigned int dim_y, unsigned int color) +void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, + unsigned int dst_y, unsigned int dim_x, + unsigned int dim_y, unsigned int color) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + GraphicDevice *dev = &mb862xx;
de_wait_slots (3); DE_WR_REG (0x0480, color); @@ -392,11 +402,12 @@ void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, unsigned int dst_y de_wait (); }
-void video_hw_bitblt (unsigned int bpp, unsigned int src_x, unsigned int src_y, - unsigned int dst_x, unsigned int dst_y, unsigned int width, +void video_hw_bitblt (unsigned int bpp, unsigned int src_x, + unsigned int src_y, unsigned int dst_x, + unsigned int dst_y, unsigned int width, unsigned int height) { - GraphicDevice *pGD = (GraphicDevice *)&mb862xx; + GraphicDevice *dev = &mb862xx; unsigned int ctrl = 0x0d000000L;
if (src_x >= dst_x && src_y >= dst_y)
Signed-off-by: Anatolij Gustschin agust@denx.de --- drivers/video/mb862xx.c | 96 ++++++++++++++++++++++++---------------------- include/mb862xx.h | 69 +++++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+), 46 deletions(-)
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index 7bc3c9b..57b8667 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -70,29 +70,30 @@ unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; #define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val)) #endif
-#define HOST_RD_REG(off) rd_io((dev->frameAdrs + 0x01fc0000 + (off))) -#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + 0x01fc0000 + (off)), \ +#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off))) +#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \ (val)) -#define DISP_RD_REG(off) rd_io((dev->frameAdrs + 0x01fd0000 + (off))) -#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + 0x01fd0000 + (off)), \ +#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off))) +#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \ (val)) #define DE_RD_REG(off) rd_io((dev->dprBase + (off))) #define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
#if defined(CONFIG_VIDEO_CORALP) -#define DE_WR_FIFO(val) wr_io((dev->dprBase + (0x8400)), (val)) +#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val)) #else -#define DE_WR_FIFO(val) wr_io((dev->dprBase + (0x04a0)), (val)) +#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val)) #endif
-#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + 0x01fd0400 + \ +#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \ + (GC_DISP_BASE | GC_L0PAL0) + \ ((idx) << 2)), (val))
static void gdc_sw_reset (void) { GraphicDevice *dev = &mb862xx;
- HOST_WR_REG (0x002c, 0x00000001); + HOST_WR_REG (GC_SRST, 0x1); udelay (500); video_hw_init (); } @@ -107,7 +108,7 @@ static void de_wait (void) * Sync with software writes to framebuffer, * try to reset if engine locked */ - while (DE_RD_REG (0x0400) & 0x00000131) + while (DE_RD_REG (GC_CTR) & 0x00000131) if (lc-- < 0) { gdc_sw_reset (); printf ("gdc reset done after drawing engine lock.\n"); @@ -121,7 +122,7 @@ static void de_wait_slots (int slots) int lc = 0x10000;
/* Wait for free fifo slots */ - while (DE_RD_REG (0x0408) < slots) + while (DE_RD_REG (GC_IFCNT) < slots) if (lc-- < 0) { gdc_sw_reset (); printf ("gdc reset done after drawing engine lock.\n"); @@ -150,21 +151,21 @@ static void de_init (void) GraphicDevice *dev = &mb862xx; int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
- dev->dprBase = dev->frameAdrs + 0x01ff0000; + dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
/* Setup mode and fbbase, xres, fg, bg */ de_wait_slots (2); DE_WR_FIFO (0xf1010108); DE_WR_FIFO (cf | 0x0300); - DE_WR_REG (0x0440, 0x0000); - DE_WR_REG (0x0444, dev->winSizeX); - DE_WR_REG (0x0480, 0x0000); - DE_WR_REG (0x0484, 0x0000); + DE_WR_REG (GC_FBR, 0x0); + DE_WR_REG (GC_XRES, dev->winSizeX); + DE_WR_REG (GC_FC, 0x0); + DE_WR_REG (GC_BC, 0x0); /* Reset clipping */ - DE_WR_REG (0x0454, 0x0000); - DE_WR_REG (0x0458, dev->winSizeX); - DE_WR_REG (0x045c, 0x0000); - DE_WR_REG (0x0460, dev->winSizeY); + DE_WR_REG (GC_CXMIN, 0x0); + DE_WR_REG (GC_CXMAX, dev->winSizeX); + DE_WR_REG (GC_CYMIN, 0x0); + DE_WR_REG (GC_CYMAX, dev->winSizeY);
/* Clear framebuffer using drawing engine */ de_wait_slots (3); @@ -200,9 +201,9 @@ unsigned int pci_video_init (void) dev->pciBase = dev->frameAdrs;
/* Setup clocks and memory mode for Coral-P Eval. Board */ - HOST_WR_REG (0x0038, 0x00090000); + HOST_WR_REG (GC_CCF, 0x00090000); udelay (200); - HOST_WR_REG (0xfffc, 0x11d7fa13); + HOST_WR_REG (GC_MMR, 0x11d7fa13); udelay (100); return dev->frameAdrs; } @@ -301,36 +302,39 @@ unsigned int card_init (void) }
/* Setup dot clock (internal pll, division rate) */ - DISP_WR_REG (0x0100, div); + DISP_WR_REG (GC_DCM1, div); /* L0 init */ cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; - DISP_WR_REG (0x0020, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 | + DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 | (dev->winSizeY - 1) | cf); - DISP_WR_REG (0x0024, 0x00000000); - DISP_WR_REG (0x0028, 0x00000000); - DISP_WR_REG (0x002c, 0x00000000); - DISP_WR_REG (0x0110, 0x00000000); - DISP_WR_REG (0x0114, 0x00000000); - DISP_WR_REG (0x0118, (dev->winSizeY - 1) << 16 | dev->winSizeX); + DISP_WR_REG (GC_L0OA0, 0x0); + DISP_WR_REG (GC_L0DA0, 0x0); + DISP_WR_REG (GC_L0DY_L0DX, 0x0); + DISP_WR_REG (GC_L0EM, 0x0); + DISP_WR_REG (GC_L0WY_L0WX, 0x0); + DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
/* Display timing init */ - DISP_WR_REG (0x0004, (dev->winSizeX + - res_mode->left_margin + - res_mode->right_margin + - res_mode->hsync_len - 1) << 16); - DISP_WR_REG (0x0008, (dev->winSizeX - 1) << 16 | (dev->winSizeX - 1)); - DISP_WR_REG (0x000c, (res_mode->vsync_len - 1) << 24 | - (res_mode->hsync_len - 1) << 16 | - (dev->winSizeX + res_mode->right_margin - 1)); - DISP_WR_REG (0x0010, (dev->winSizeY + res_mode->lower_margin + - res_mode->upper_margin + - res_mode->vsync_len - 1) << 16); - DISP_WR_REG (0x0014, (dev->winSizeY-1) << 16 | - (dev->winSizeY + res_mode->lower_margin - 1)); - DISP_WR_REG (0x0018, 0x00000000); - DISP_WR_REG (0x001c, dev->winSizeY << 16 | dev->winSizeX); + DISP_WR_REG (GC_HTP_A, (dev->winSizeX + + res_mode->left_margin + + res_mode->right_margin + + res_mode->hsync_len - 1) << 16); + DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 | + (dev->winSizeX - 1)); + DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 | + (res_mode->hsync_len - 1) << 16 | + (dev->winSizeX + + res_mode->right_margin - 1)); + DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin + + res_mode->upper_margin + + res_mode->vsync_len - 1) << 16); + DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 | + (dev->winSizeY + + res_mode->lower_margin - 1)); + DISP_WR_REG (GC_WY_WX, 0x0); + DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX); /* Display enable, L0 layer */ - DISP_WR_REG (0x0100, 0x80010000 | div); + DISP_WR_REG (GC_DCM1, 0x80010000 | div);
return dev->frameAdrs; } @@ -395,7 +399,7 @@ void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, GraphicDevice *dev = &mb862xx;
de_wait_slots (3); - DE_WR_REG (0x0480, color); + DE_WR_REG (GC_FC, color); DE_WR_FIFO (0x09410000); DE_WR_FIFO ((dst_y << 16) | dst_x); DE_WR_FIFO ((dim_y << 16) | dim_x); diff --git a/include/mb862xx.h b/include/mb862xx.h index 164305f..43f01e7 100644 --- a/include/mb862xx.h +++ b/include/mb862xx.h @@ -32,6 +32,75 @@ #define PCI_DEVICE_ID_CORAL_P 0x2019 #define PCI_DEVICE_ID_CORAL_PA 0x201E
+#define GC_HOST_BASE 0x01fc0000 +#define GC_DISP_BASE 0x01fd0000 +#define GC_DRAW_BASE 0x01ff0000 + +/* Host interface registers */ +#define GC_SRST 0x0000002c +#define GC_CCF 0x00000038 +#define GC_MMR 0x0000fffc + +/* + * Display Controller registers + * _A means the offset is aligned, we use these for boards + * with 8-/16-bit GDC access not working or buggy. + */ +#define GC_DCM0 0x00000000 +#define GC_HTP_A 0x00000004 +#define GC_HTP 0x00000006 +#define GC_HDB_HDP_A 0x00000008 +#define GC_HDP 0x00000008 +#define GC_HDB 0x0000000a +#define GC_VSW_HSW_HSP_A 0x0000000c +#define GC_HSP 0x0000000c +#define GC_HSW 0x0000000e +#define GC_VSW 0x0000000f +#define GC_VTR_A 0x00000010 +#define GC_VTR 0x00000012 +#define GC_VDP_VSP_A 0x00000014 +#define GC_VSP 0x00000014 +#define GC_VDP 0x00000016 +#define GC_WY_WX 0x00000018 +#define GC_WH_WW 0x0000001c +#define GC_L0M 0x00000020 +#define GC_L0OA0 0x00000024 +#define GC_L0DA0 0x00000028 +#define GC_L0DY_L0DX 0x0000002c +#define GC_L2M 0x00000040 +#define GC_L2OA0 0x00000044 +#define GC_L2DA0 0x00000048 +#define GC_L2OA1 0x0000004c +#define GC_L2DA1 0x00000050 +#define GC_L2DX 0x00000054 +#define GC_L2DY 0x00000056 +#define GC_DCM1 0x00000100 +#define GC_DCM2 0x00000104 +#define GC_DCM3 0x00000108 +#define GC_L0EM 0x00000110 +#define GC_L0WY_L0WX 0x00000114 +#define GC_L0WH_L0WW 0x00000118 +#define GC_L2EM 0x00000130 +#define GC_L2WX 0x00000134 +#define GC_L2WY 0x00000136 +#define GC_L2WW 0x00000138 +#define GC_L2WH 0x0000013a +#define GC_L0PAL0 0x00000400 + +/* Drawing registers */ +#define GC_CTR 0x00000400 +#define GC_IFCNT 0x00000408 +#define GC_FBR 0x00000440 +#define GC_XRES 0x00000444 +#define GC_CXMIN 0x00000454 +#define GC_CXMAX 0x00000458 +#define GC_CYMIN 0x0000045c +#define GC_CYMAX 0x00000460 +#define GC_FC 0x00000480 +#define GC_BC 0x00000484 +#define GC_FIFO 0x000004a0 +#define GC_GEO_FIFO 0x00008400 + typedef struct { unsigned int index; unsigned int value;
Signed-off-by: Anatolij Gustschin agust@denx.de --- drivers/video/mb862xx.c | 20 ++++++++++---------- 1 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index 57b8667..a8676cc 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -111,7 +111,7 @@ static void de_wait (void) while (DE_RD_REG (GC_CTR) & 0x00000131) if (lc-- < 0) { gdc_sw_reset (); - printf ("gdc reset done after drawing engine lock.\n"); + puts ("gdc reset done after drawing engine lock.\n"); break; } } @@ -125,7 +125,7 @@ static void de_wait_slots (int slots) while (DE_RD_REG (GC_IFCNT) < slots) if (lc-- < 0) { gdc_sw_reset (); - printf ("gdc reset done after drawing engine lock.\n"); + puts ("gdc reset done after drawing engine lock.\n"); break; } } @@ -183,7 +183,7 @@ unsigned int pci_video_init (void) pci_dev_t devbusfn;
if ((devbusfn = pci_find_devices (supported, 0)) < 0) { - printf ("PCI video controller not found!\n"); + puts ("PCI video controller not found!\n"); return 0; }
@@ -194,7 +194,7 @@ unsigned int pci_video_init (void) dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
if (dev->frameAdrs == 0) { - printf ("PCI config: failed to get base address\n"); + puts ("PCI config: failed to get base address\n"); return 0; }
@@ -223,7 +223,7 @@ unsigned int card_init (void) if (!pci_video_init ()) return 0;
- printf ("CoralP\n"); + puts ("CoralP\n");
tmp = 0; videomode = 0x310; @@ -252,7 +252,7 @@ unsigned int card_init (void) res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; if (vesa_modes[i].resindex > 2) { - printf ("\tUnsupported resolution, using default\n"); + puts ("\tUnsupported resolution, using default\n"); bpp = vesa_modes[1].bits_per_pixel; div = fr_div[1]; } @@ -296,7 +296,7 @@ unsigned int card_init (void) default: printf ("\t%d bpp configured, but only 8,15 and 16 supported\n", bpp); - printf ("\tSwitching back to 15bpp\n"); + puts ("\tfallback to 15bpp\n"); dev->gdfIndex = GDF_15BIT_555RGB; dev->gdfBytesPP = 2; } @@ -344,7 +344,7 @@ void *video_hw_init (void) { GraphicDevice *dev = &mb862xx;
- printf ("Video: Fujitsu "); + puts ("Video: Fujitsu ");
memset (dev, 0, sizeof (GraphicDevice));
@@ -357,10 +357,10 @@ void *video_hw_init (void) * retrieve base address */ if ((dev->frameAdrs = board_video_init ()) == 0) { - printf ("Controller not found!\n"); + puts ("Controller not found!\n"); return NULL; } else - printf ("Lime\n"); + puts ("Lime\n"); #endif
de_init ();
On Tue, 7 Jul 2009 13:45:34 +0200 Anatolij Gustschin agust@denx.de wrote:
Signed-off-by: Anatolij Gustschin agust@denx.de
drivers/video/mb862xx.c | 20 ++++++++++---------- 1 files changed, 10 insertions(+), 10 deletions(-)
applied
On Tue, 7 Jul 2009 13:45:33 +0200 Anatolij Gustschin agust@denx.de wrote:
Signed-off-by: Anatolij Gustschin agust@denx.de
drivers/video/mb862xx.c | 96 ++++++++++++++++++++++++---------------------- include/mb862xx.h | 69 +++++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+), 46 deletions(-)
applied
On Tue, 7 Jul 2009 13:45:32 +0200 Anatolij Gustschin agust@denx.de wrote:
Signed-off-by: Anatolij Gustschin agust@denx.de
drivers/video/mb862xx.c | 217 +++++++++++++++++++++++++---------------------- 1 files changed, 114 insertions(+), 103 deletions(-)
applied
participants (1)
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Anatolij Gustschin