[U-Boot] [PATCH 0/6] ARM:OMAP3:SDP3430 initial support
Hi, This series of patch provides minimal support for OMAP3430 based OMAP3 platform
Ref: http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&...
David Brownell (1): ARM:OMAP3:SDP3430: initial support
Nishanth Menon (5): OMAP3: Fix SDRC init OMAP3: export enable_gpmc_cs_config to board files OMAP3: make gpmc_config as const OMAP3: fix warnings when NAND/ONENAND is not used DLMALLOC:!X86: add av_ initialization
MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/ti/sdp3430/Makefile | 49 ++++ board/ti/sdp3430/config.mk | 33 +++ board/ti/sdp3430/sdp.c | 194 ++++++++++++++++ board/ti/sdp3430/sdp.h | 376 ++++++++++++++++++++++++++++++++ board/ti/sdp3430/u-boot.lds | 63 ++++++ common/dlmalloc.c | 5 + cpu/arm_cortexa8/omap3/mem.c | 15 +- include/asm-arm/arch-omap3/cpu.h | 1 + include/asm-arm/arch-omap3/mem.h | 8 +- include/asm-arm/arch-omap3/sys_proto.h | 2 + include/configs/omap3_sdp.h | 367 +++++++++++++++++++++++++++++++ 14 files changed, 1109 insertions(+), 9 deletions(-) create mode 100644 board/ti/sdp3430/Makefile create mode 100644 board/ti/sdp3430/config.mk create mode 100644 board/ti/sdp3430/sdp.c create mode 100644 board/ti/sdp3430/sdp.h create mode 100644 board/ti/sdp3430/u-boot.lds create mode 100644 include/configs/omap3_sdp.h
Regards, Nishanth Menon
Defaults are for infenion DDR timings. Since none of the supported boards currently do XIP boot, these seem to be faulty. fix the values as per the calculations(ACTIMA,B), conf the sdrc power with pwdnen and wakeupproc bits
Signed-off-by: Nishanth Menon nm@ti.com --- cpu/arm_cortexa8/omap3/mem.c | 3 ++- include/asm-arm/arch-omap3/cpu.h | 1 + include/asm-arm/arch-omap3/mem.h | 8 ++++---- 3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 079c848..8731c9d 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early) writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
/* Disable Power Down of CKE cuz of 1 CKE on combo part */ - writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power); + writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH, + &sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index 8ab2e39..e51c4f3 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -222,6 +222,7 @@ struct sdrc {
#define PAGEPOLICY_HIGH (0x1 << 0) #define SRFRONRESET (0x1 << 7) +#define PWDNEN (0x1 << 2) #define WAKEUPPROC (0x1 << 26)
#define DDR_SDRAM (0x1 << 0) diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h index 5b9ac75..31cbdef 100644 --- a/include/asm-arm/arch-omap3/mem.h +++ b/include/asm-arm/arch-omap3/mem.h @@ -78,16 +78,16 @@ enum { #define TRP_165 3 #define TRAS_165 7 #define TRC_165 10 -#define TRFC_165 21 +#define TRFC_165 12 #define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \ (TRAS_165 << 18) | (TRP_165 << 15) | \ (TRCD_165 << 12) | (TRRD_165 << 9) | \ (TDPL_165 << 6) | (TDAL_165))
#define TWTR_165 1 -#define TCKE_165 1 -#define TXP_165 5 -#define XSR_165 23 +#define TCKE_165 2 +#define TXP_165 2 +#define XSR_165 20 #define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \ (TXP_165 << 8) | (TWTR_165 << 16))
Export enable_gpmc_cs_config into common header to prevent warning: warning: implicit declaration of function 'enable_gpmc_cs_config'
Signed-off-by: Nishanth Menon nm@ti.com --- include/asm-arm/arch-omap3/sys_proto.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index 2246f80..e59021e 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -34,6 +34,8 @@ void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); void gpmc_init(void); +void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size);
void watchdog_init(void); void set_muxconf_regs(void);
gpmc_config should not be a variant as it is board specific hence make it a const parameter
Signed-off-by: Nishanth Menon nm@ti.com --- cpu/arm_cortexa8/omap3/mem.c | 6 +++--- include/asm-arm/arch-omap3/sys_proto.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 8731c9d..8d64478 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -44,7 +44,7 @@ volatile unsigned int boot_flash_env_addr; struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND) -static u32 gpmc_m_nand[GPMC_MAX_REG] = { +static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, M_NAND_GPMC_CONFIG2, M_NAND_GPMC_CONFIG3, @@ -62,7 +62,7 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = { #endif
#if defined(CONFIG_CMD_ONENAND) -static u32 gpmc_onenand[GPMC_MAX_REG] = { +static const u32 gpmc_onenand[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, ONENAND_GPMC_CONFIG2, ONENAND_GPMC_CONFIG3, @@ -193,7 +193,7 @@ void do_sdrc_init(u32 cs, u32 early) writel(0, &sdrc_base->cs[cs].mcfg); }
-void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base, +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size) { writel(0, &cs->config7); diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index e59021e..34bd515 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -34,7 +34,7 @@ void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); void gpmc_init(void); -void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base, +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size);
void watchdog_init(void);
Fix build warnings by putting specific used variables under required #ifdefs for removing: mem.c:227: warning: unused variable 'f_sec' mem.c:226: warning: unused variable 'f_off' mem.c:225: warning: unused variable 'size' mem.c:224: warning: unused variable 'base' mem.c:222: warning: unused variable 'gpmc_config'
Signed-off-by: Nishanth Menon nm@ti.com --- cpu/arm_cortexa8/omap3/mem.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 8d64478..e93343c 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -219,12 +219,16 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ - u32 *gpmc_config = NULL; gpmc_cfg = (struct gpmc *)GPMC_BASE; +#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND) + u32 *gpmc_config = NULL; u32 base = 0; u32 size = 0; +#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND) u32 f_off = CONFIG_SYS_MONITOR_LEN; u32 f_sec = 0; +#endif +#endif u32 config = 0;
/* global settings */
This is questionable if this is really required as the av_ static initalized values should have been loaded to sdram as part of the boot process and initialization should have been done.
Signed-off-by: Nishanth Menon nm@ti.com --- common/dlmalloc.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 241db8c..bd509db 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1527,6 +1527,11 @@ void *sbrk(ptrdiff_t increment) */ void mem_malloc_init(ulong start, ulong size) { + u8 i; + av_[0] = av_[1] = 0; + for (i = 0; i < 128; i++) + av_[2 + i * 2] = av_[2 + i * 2 + 1] = bin_at(i); + mem_malloc_start = start; mem_malloc_end = start + size; mem_malloc_brk = start;
From: David Brownell david-b@pacbell.net
Start of SDP3430 support in "mainline" u-boot mainline code
Original Patch written by David Brownell
Support default jumpering and: - UART1/ttyS0 console(legacy sdp3430 u-boot) - UART3/ttyS2 console (matching other boards, and SDP HW docs) - Ethernet - mmc0 - NOR boot
TODO: - mmc1 - NAND (boot or 128M storage) - OneNAND (boot or 256M storage) - Fix NOR env variable load - Review SDRC timing configuration/DPLL configuration - Dynamically read FPGA dip switch settings and map NOR/NAND/ONENAND devices to right chipselects
Currently the UART1 is enabled by default. for compatibility with other OMAP3 u-boot platforms, enable the #define of CONSOLE_J9.
Ref: SDP3430: http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&...
Signed-off-by: David Brownell david-b@pacbell.net Signed-off-by: Nishanth Menon nm@ti.com --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/ti/sdp3430/Makefile | 49 ++++++ board/ti/sdp3430/config.mk | 33 ++++ board/ti/sdp3430/sdp.c | 194 ++++++++++++++++++++++ board/ti/sdp3430/sdp.h | 376 +++++++++++++++++++++++++++++++++++++++++++ board/ti/sdp3430/u-boot.lds | 63 +++++++ include/configs/omap3_sdp.h | 367 +++++++++++++++++++++++++++++++++++++++++ 9 files changed, 1087 insertions(+), 0 deletions(-) create mode 100644 board/ti/sdp3430/Makefile create mode 100644 board/ti/sdp3430/config.mk create mode 100644 board/ti/sdp3430/sdp.c create mode 100644 board/ti/sdp3430/sdp.h create mode 100644 board/ti/sdp3430/u-boot.lds create mode 100644 include/configs/omap3_sdp.h
diff --git a/MAINTAINERS b/MAINTAINERS index e9db278..adc8a63 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -619,6 +619,7 @@ Guennadi Liakhovetski g.liakhovetski@gmx.de Nishanth Menon nm@ti.com
omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC) + omap3_sdp ARM CORTEX-A8 (OMAP3xx SoC)
David Müller d.mueller@elsoft.ch
diff --git a/MAKEALL b/MAKEALL index f0ed8ea..53620eb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -588,6 +588,7 @@ LIST_ARM_CORTEX_A8=" \ omap3_pandora \ omap3_zoom1 \ omap3_zoom2 \ + omap3_sdp \ "
######################################################################### diff --git a/Makefile b/Makefile index 5a4a109..2626147 100644 --- a/Makefile +++ b/Makefile @@ -3172,6 +3172,9 @@ omap3_zoom1_config : unconfig omap3_zoom2_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
+omap3_sdp_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3 + ######################################################################### ## XScale Systems ######################################################################### diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile new file mode 100644 index 0000000..2554c7b --- /dev/null +++ b/board/ti/sdp3430/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := sdp.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/sdp3430/config.mk b/board/ti/sdp3430/config.mk new file mode 100644 index 0000000..3726634 --- /dev/null +++ b/board/ti/sdp3430/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2006-2009 +# Texas Instruments, <www.ti.com> +# +# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c new file mode 100644 index 0000000..39116a0 --- /dev/null +++ b/board/ti/sdp3430/sdp.c @@ -0,0 +1,194 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, <www.ti.com> + * Richard Woodruff r-woodruff2@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include "sdp.h" + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "OMAP3 SDP3430 board", +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "OneNAND", +#elif defined(CONFIG_ENV_IS_IN_NAND) + "NAND", +#else + "NOR", +#endif +}; + +static const u32 gpmc_sdp_nor[] = { + 0x00001200, /*CONF1 */ + 0x001F1F00, /*CONF2 */ + 0x00080802, /*CONF3 */ + 0x1C091C09, /*CONF4 */ + 0x01131F1F, /*CONF5 */ + 0x1F0F03C2, /*CONF6 */ + /*CONF7- computed as params */ +}; +static const u32 gpmc_sdp_debug[] = { + 0x00611200, /*CONF1 FPGA needs WAIT1 line-active Low to function now.. */ + 0x001F1F01, /*CONF2 */ + 0x00080803, /*CONF3 */ + 0x1D091D09, /*CONF4 */ + 0x041D1F1F, /*CONF5 */ + 0x1D0904C4, /*CONF6 */ + /*CONF7- computed as params */ +}; +static const u32 gpmc_sdp_onenand[] = { + 0x00001200, /*CONF1 */ + 0x000F0F01, /*CONF2 */ + 0x00030301, /*CONF3 */ + 0x0F040F04, /*CONF4 */ + 0x010F1010, /*CONF5 */ + 0x1F060000, /*CONF6 */ + /*CONF7- computed as params */ +}; + +static const u32 gpmc_sdp_nand[] = { + 0x00000800, /*CONF1 */ + 0x00141400, /*CONF2 */ + 0x00141400, /*CONF3 */ + 0x0F010F01, /*CONF4 */ + 0x010C1414, /*CONF5 */ + 0x1F040A80, /*CONF6 */ + /*CONF7- computed as params */ +}; + +/* gpmc_cfg is initialized by gpmc_init and we use it here */ +extern struct gpmc *gpmc_cfg; + +/****************************************************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* TODO: Dynamically pop out CS mapping and program accordingly */ + /* Configure devices for default ON ON ON settings */ + enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0], + CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M); + enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000, + GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000, + GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE, + GPMC_SIZE_16M); + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c) +#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b) + +static void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int rc = 0; + int cnt = 20; + + writew(0x0, LAN_RESET_REGISTER); + do { + writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto reset_err_out; + --cnt; + } while (readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto reset_err_out; + --cnt; + } while (readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG); + udelay(1000); +reset_err_out: + return; + +#endif +} + + +/****************************************************************************** + * Routine: misc_init_r + * Description: Configure SDP board specific configurations + *****************************************************************************/ +int misc_init_r(void) +{ + /* partial setup: + * VAUX3 - 2.8V for DVI + * VPLL1 - 1.8V + * VDAC - 1.8V + * and turns on LEDA/LEDB (not needed ... NOP?) + */ + twl4030_power_init(); + + /* FIXME finish setup: + * VAUX1 - 2.8V for mainboard I/O + * VAUX2 - 2.8V for camera + * VAUX4 - 1.8V for OMAP3 CSI + * VMMC1 - 3.15V (init, variable) for MMC1 + * VMMC2 - 1.85V for MMC2 + * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM + * VPLL2 - 1.8V + */ + ether_init(); + + return 0; +} + +/****************************************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + *****************************************************************************/ +void set_muxconf_regs(void) +{ + /* platform specific muxes */ + MUX_SDP3430(); +} diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h new file mode 100644 index 0000000..5ad2920 --- /dev/null +++ b/board/ti/sdp3430/sdp.h @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments + * Richard Woodruff r-woodruff2@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _BOARD_SDP_H_ +#define _BOARD_SDP_H_ + +#define OFF_IN_PD 0 +#define OFF_OUT_PD 0 + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_SDP3430()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*NCS0*/\ + MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*NCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*NCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*NCS3*/\ + MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\ + MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) /*G56-T_EN*/\ + MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\ + MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G58-WLNIQ*/\ + MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*NADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_NOE*/\ + MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_NWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*NBE0_CLE*/\ + MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\ + MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_NWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0)) /*WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0)) /*WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA10*/\ + MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA11*/\ + MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA12*/\ + MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA13*/\ + MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA14*/\ + MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA15*/\ + MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA16*/\ + MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA17*/\ + MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA18*/\ + MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA19*/\ + MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA20*/\ + MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA21*/\ + MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA22*/\ + MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*DSSDATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))/*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\ + MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D2 */\ + MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D3 */\ + MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D4 */\ + MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D5 */\ + MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D6 */\ + MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D7 */\ + MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D8 */\ + MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D9 */\ + MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*CAM_STRB*/\ + MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio InterfACe */\ + MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCBP2_FSX*/\ + MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCBP2CLKX*/\ + MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCBSP2_DR*/\ + MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*MCBSP2_DX*/\ + /*Expansion Card */\ + MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1DAT7*/\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))/*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))/*MMC2DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))/*MMC2DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))/*MMC2DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))/*MMC2DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*MMC2DRD0*/\ + MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*MMC2DRD1*/\ + MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*MMC2DCMD*/\ + MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*MMC2CLKIN*/\ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*MCBSP3_DX*/\ + MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCBSP3_DR*/\ + MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCBP3CLKX*/\ + MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCBSP3FSX*/\ + MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))/*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))/*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))/*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))/*UART1_RX*/\ + MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DATRX*/\ + MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\ + MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\ + MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\ + MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MBSP1CLKR*/\ + MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157-BTWP*/\ + MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*MCBSP1_DX*/\ + MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCBSP1_DR*/\ + MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))/*MCBSPCLKS*/\ + MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCBSP1FSX*/\ + MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCBSPCLKX*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))/*UART3CTS*/\ + MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*UART3RTS*/\ + MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*UART3RX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*UART3TX*/\ + MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))/*HSUSB0STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0D0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0D1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0D2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0D3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0D4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0D5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0D6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB0D7*/\ + /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */ \ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))/*HDQ_SIO*/\ + MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCSPI1CLK*/\ + MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCSPI1SIO*/\ + MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCSPI1SOI*/\ + MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))/*MCSPI1CS0*/\ + MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))/*MCSPI1CS1*/\ + MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176NORDD*/\ + MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))/*MCSPI1CS3*/\ + MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCSPI2CLK*/\ + MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCSPI2SIO*/\ + MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))/*MCSPI2SOI*/\ + MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))/*MCSPI2CS0*/\ + MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))/*MCSPI2CS1*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))/*SYS_NIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2-PENIRQ*/\ + MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4-MMC1WP*/\ + MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5-LCDENV*/\ + MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6-LANINT*/\ + MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7-MMC2WP*/\ + MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8-ENBKL*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1 */\ + MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))/*JTAG_EMU0*/\ + MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))/*JTAG_EMU1*/\ + MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))/*HSUSB1TSTP*/\ + MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))/*HSUSB1TCLK*/\ + MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*HSUSB1TLD0*/\ + MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*MCSPI3_CS0*/\ + MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*HSUSB1TLD2*/\ + MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*HSUSB1TLD7*/\ + MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB1TLD4*/\ + MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB1TLD5*/\ + MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB1TLD6*/\ + MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB1TLD3*/\ + MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB1DIR*/\ + MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB1NXT*/\ + MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB2CLK*/\ + MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB2STP*/\ + MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB2DIR*/\ + MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB2TNXT*/\ + MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB2TLD0*/\ + MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))/*HSUSB2TLD1*/\ + /*Die to Die */\ + MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD0*/\ + MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD1*/\ + MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD2*/\ + MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD3*/\ + MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD4*/\ + MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD5*/\ + MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD6*/\ + MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD7*/\ + MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD8*/\ + MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD9*/\ + MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD10*/\ + MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD11*/\ + MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD12*/\ + MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD13*/\ + MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD14*/\ + MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD15*/\ + MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD16*/\ + MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD17*/\ + MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD18*/\ + MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD19*/\ + MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD20*/\ + MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD21*/\ + MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD22*/\ + MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD23*/\ + MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD24*/\ + MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD25*/\ + MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD26*/\ + MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD27*/\ + MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD28*/\ + MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD29*/\ + MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD30*/\ + MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD31*/\ + MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD32*/\ + MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD33*/\ + MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD34*/\ + MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD35*/\ + MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_MCAD36*/\ + MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2DCLK26MI*/\ + MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))/*D2DNRESRON*/\ + MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))/*D2DNRESARM*/\ + MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2DARM9IRQ*/\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2DUMA26FQ*/\ + MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2DSPINT*/\ + MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))/*D2D_FRINT*/\ + MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2DDMAREQ0*/\ + MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2DDMAREQ1*/\ + MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2DDMAREQ2*/\ + MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2DDMAREQ3*/\ + MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2DN3GTRST*/\ + MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2D_N3GTDI*/\ + MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))/*D2D_N3GTDO*/\ + MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2D_N3GTMS*/\ + MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2D_N3GTCK*/\ + MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))/*D2DN3GRTCK*/\ + MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))/*D2D_MSTDBY*/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*D2D_SWAKEUP */\ + MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2DIDLEREQ*/\ + MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))/*D2DIDLEACK*/\ + MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))/*D2D_MWRITE*/\ + MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))/*D2D_SWRITE*/\ + MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))/*D2D_MREAD*/\ + MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))/*D2D_SREAD*/\ + MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))/*D2DMBUSFLG*/\ + MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))/*D2DSBUSFLG*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*SDRC_CKE0 */\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/ + +#endif /* _BOARD_SDP_H_ */ diff --git a/board/ti/sdp3430/u-boot.lds b/board/ti/sdp3430/u-boot.lds new file mode 100644 index 0000000..4ecc6dd --- /dev/null +++ b/board/ti/sdp3430/u-boot.lds @@ -0,0 +1,63 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2009 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, gj@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm_cortexa8/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } + __exidx_start = .; + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } + __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/include/configs/omap3_sdp.h b/include/configs/omap3_sdp.h new file mode 100644 index 0000000..176617a --- /dev/null +++ b/include/configs/omap3_sdp.h @@ -0,0 +1,367 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments. + * Richard Woodruff r-woodruff2@ti.com + * Syed Mohammed Khasim x0khasim@ti.com + * Nishanth Menon nm@ti.com + * + * Configuration settings for the 3430 TI SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * NOTE: these #defines presume standard SDP jumper settings. + * In particular: + * - 26 MHz clock (not 19.2 or 38.4 MHz) + * - Boot from 128MB NOR, not NAND or OneNAND + * + * At this writing, OMAP3 U-Boot support doesn't permit concurrent + * support for all the flash types the board supports. + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_256K /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/*--------------------------------------------------------------------------*/ + +/* + * Hardware drivers + */ + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER 1 + +/* + * serial port - NS16550 compatible + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be + * swapped with UART2 via jumpering. Downsides of using J8: it doesn't + * support UART boot (that's only for UART3); it prevents sharing a Linux + * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards. + * + * UART boot uses UART3 on J9, and the SDP user's guide says to use + * that for console. Downsides of using J9: you can't use IRDA too; + * since UART3 isn't in the CORE power domain, it may be a bit less + * usable in certain PM-sensitive debug scenarios. + */ +#if 0 +#define CONSOLE_J9 /* else J8/UART1 (innermost) */ +#endif + +#ifdef CONSOLE_J9 +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ +#else +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 */ +#endif + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +/* + * I2C for power management setup + */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* OMITTED: single 1 Gbit MT29F1G NAND flash */ + +/* + * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash + */ +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */ +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ + +#define CONFIG_SYS_FLASH_CFI_WIDTH 2 +#define PHYS_FLASH_SIZE SZ_128M +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */ + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + + +/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */ + + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_SYS_ENV_SECT_SIZE SZ_256K +#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE) +/*--------------------------------------------------------------------------*/ + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_EXT2 /* EXT2 Support */ + +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +/*--------------------------------------------------------------------------*/ +/* + * MMC boot support + */ + +#if defined(CONFIG_CMD_MMC) +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 +#endif + +/*---------------------------------------------------------------------------- + * SMSC9115 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- + */ +#if defined(CONFIG_CMD_NET) + +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE DEBUG_BASE +#define CONFIG_LAN91C96_EXT_PHY + +#define CONFIG_BOOTP_SEND_HOSTNAME +/* + * BOOTP fields + */ +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 +#endif /* (CONFIG_CMD_NET) */ + +/* + * Environment setup + * + * Default boot order: mmc bootscript, MMC uImage, NOR image. + * Network booting environment must be configured at site. + */ + +/* allow overwriting serial config and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS0,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "norargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock3 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from MMC/SD ...; " \ + "autoscr ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from MMC/SD ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "norboot=echo Booting from NOR ...; " \ + "run norargs; " \ + "bootm 0x80000\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmcinit; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run norboot; " \ + "fi; " \ + "fi; " \ + "else run norboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 + + +/*--------------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP34XX SDP # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ + /* works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ + /* load address */ + +/*--------------------------------------------------------------------------*/ + +/* + * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/* + * SDRAM Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*--------------------------------------------------------------------------*/ + +/* + * NOR FLASH usage ... default nCS0: + * - one 256KB sector for U-Boot + * - one 256KB sector for its parameters (not all used) + * - eight sectors (2 MB) for kernel + * - rest for JFFS2 + */ + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN SZ_256K + +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +/* + * NAND FLASH usage ... default nCS1: + * - four 128KB sectors for X-Loader + * - four 128KB sectors for U-Boot + * - two 128KB sector for its parameters + * - 32 sectors (4 MB) for kernel + * - rest for filesystem + */ + +/* + * OneNAND FLASH usage ... default nCS2: + * - four 128KB sectors for X-Loader + * - two 128KB sectors for U-Boot + * - one 128KB sector for its parameters + * - sixteen sectors (2 MB) for kernel + * - rest for filesystem + */ + +/*--------------------------------------------------------------------------*/ + +#ifndef __ASSEMBLY__ +extern struct gpmc *gpmc_cfg; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + + +#endif /* __CONFIG_H */
Hi Nishanth,
On Fri, 2009-09-18 at 21:21 -0500, Nishanth Menon wrote:
From: David Brownell david-b@pacbell.net
Start of SDP3430 support in "mainline" u-boot mainline code
Original Patch written by David Brownell
I don't think the above comments are necessary. David will be credited with authorship already, and the subject line and text below make it clear what this patch does.
Support default jumpering and:
- UART1/ttyS0 console(legacy sdp3430 u-boot)
- UART3/ttyS2 console (matching other boards, and SDP HW docs)
- Ethernet
- mmc0
- NOR boot
TODO:
- mmc1
- NAND (boot or 128M storage)
- OneNAND (boot or 256M storage)
- Fix NOR env variable load
- Review SDRC timing configuration/DPLL configuration
- Dynamically read FPGA dip switch settings and map NOR/NAND/ONENAND devices to right chipselects
Currently the UART1 is enabled by default. for compatibility with other OMAP3 u-boot platforms, enable the #define of CONSOLE_J9.
Ref: SDP3430: http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&...
Signed-off-by: David Brownell david-b@pacbell.net Signed-off-by: Nishanth Menon nm@ti.com
MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/ti/sdp3430/Makefile | 49 ++++++ board/ti/sdp3430/config.mk | 33 ++++ board/ti/sdp3430/sdp.c | 194 ++++++++++++++++++++++ board/ti/sdp3430/sdp.h | 376 +++++++++++++++++++++++++++++++++++++++++++ board/ti/sdp3430/u-boot.lds | 63 +++++++ include/configs/omap3_sdp.h | 367 +++++++++++++++++++++++++++++++++++++++++ 9 files changed, 1087 insertions(+), 0 deletions(-) create mode 100644 board/ti/sdp3430/Makefile create mode 100644 board/ti/sdp3430/config.mk create mode 100644 board/ti/sdp3430/sdp.c create mode 100644 board/ti/sdp3430/sdp.h create mode 100644 board/ti/sdp3430/u-boot.lds create mode 100644 include/configs/omap3_sdp.h
The board config header file should be renamed to sdp.h from omap3_sdp.h. There was a recent thread discussing this convention "ARM Pull Request" around Sept 6.
diff --git a/MAINTAINERS b/MAINTAINERS index e9db278..adc8a63 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -619,6 +619,7 @@ Guennadi Liakhovetski g.liakhovetski@gmx.de Nishanth Menon nm@ti.com
omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
- omap3_sdp ARM CORTEX-A8 (OMAP3xx SoC)
You may as well keep the boards ordered alphabetically (and remove the omap_ prefix from sdp).
David Mller d.mueller@elsoft.ch
diff --git a/MAKEALL b/MAKEALL index f0ed8ea..53620eb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -588,6 +588,7 @@ LIST_ARM_CORTEX_A8=" \ omap3_pandora \ omap3_zoom1 \ omap3_zoom2 \
- omap3_sdp \
"
Ditto.
######################################################################### diff --git a/Makefile b/Makefile index 5a4a109..2626147 100644 --- a/Makefile +++ b/Makefile @@ -3172,6 +3172,9 @@ omap3_zoom1_config : unconfig omap3_zoom2_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
+omap3_sdp_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3
Ditto.
<snip>
+/******************************************************************************
- Routine: board_init
- Description: Early hardware init.
- *****************************************************************************/
+int board_init(void) +{
- DECLARE_GLOBAL_DATA_PTR;
I'd use the preferred multi-line comment style: /* * */
There are lots of other non-preferred multi-line comments throughout the patch as well.
I personally don't think its necessary to put "Routine: <name>" stuff for each function either. It doesn't add any benefit, adds cruft to grep output, and might get out of sync with the real function name at some point. If it were me, I would get rid of "Description: " text too. Its pretty obvious that the text "Early hardware init" is a description of the function.
Best, Peter
Peter Tyser said the following on 09/19/2009 09:34 AM: thanks for your review
Hi Nishanth,
On Fri, 2009-09-18 at 21:21 -0500, Nishanth Menon wrote:
From: David Brownell david-b@pacbell.net
Start of SDP3430 support in "mainline" u-boot mainline code
Original Patch written by David Brownell
I don't think the above comments are necessary. David will be credited with authorship already, and the subject line and text below make it clear what this patch does.
Ack..
create mode 100644 board/ti/sdp3430/sdp.h create mode 100644 board/ti/sdp3430/u-boot.lds create mode 100644 include/configs/omap3_sdp.h
The board config header file should be renamed to sdp.h from omap3_sdp.h. There was a recent thread discussing this convention "ARM Pull Request" around Sept 6.
sdp3430 - there are many software development platforms -> omap2420 based, omap2430 based etc.. Thanks for pointing this chain out.. a specific link describing the thought will help and prevent me misunderstanding the intention here.
diff --git a/MAINTAINERS b/MAINTAINERS index e9db278..adc8a63 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -619,6 +619,7 @@ Guennadi Liakhovetski g.liakhovetski@gmx.de Nishanth Menon nm@ti.com
omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
- omap3_sdp ARM CORTEX-A8 (OMAP3xx SoC)
You may as well keep the boards ordered alphabetically (and remove the omap_ prefix from sdp).
ack to alphabetical sort.
+/******************************************************************************
- Routine: board_init
- Description: Early hardware init.
- *****************************************************************************/
+int board_init(void) +{
- DECLARE_GLOBAL_DATA_PTR;
I'd use the preferred multi-line comment style: /*
*/
There are lots of other non-preferred multi-line comments throughout the patch as well.
ack.
I personally don't think its necessary to put "Routine: <name>" stuff for each function either. It doesn't add any benefit, adds cruft to grep output, and might get out of sync with the real function name at some point. If it were me, I would get rid of "Description: " text too. Its pretty obvious that the text "Early hardware init" is a description of the function.
not to all.. I dont like it either, I would rather go doxygen style.. will convert.
Regards, Nishanth Menon
MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/ti/sdp3430/Makefile | 49 ++++++ board/ti/sdp3430/config.mk | 33 ++++ board/ti/sdp3430/sdp.c | 194 ++++++++++++++++++++++ board/ti/sdp3430/sdp.h | 376 +++++++++++++++++++++++++++++++++++++++++++ board/ti/sdp3430/u-boot.lds | 63 +++++++ include/configs/omap3_sdp.h | 367 +++++++++++++++++++++++++++++++++++++++++ 9 files changed, 1087 insertions(+), 0 deletions(-) create mode 100644 board/ti/sdp3430/Makefile create mode 100644 board/ti/sdp3430/config.mk create mode 100644 board/ti/sdp3430/sdp.c create mode 100644 board/ti/sdp3430/sdp.h create mode 100644 board/ti/sdp3430/u-boot.lds
why is this u-boot.lds required here, when we already have it in /cpu/arm_cortexa8/
a diff between what is in the above location and what is in your patch suggests that they(u-boot.lds) are similar though not same.
create mode 100644 include/configs/omap3_sdp.h
Dear Nishanth Menon,
In message 1253326918-1670-7-git-send-email-nm@ti.com you wrote:
--===============1247028818==
From: David Brownell david-b@pacbell.net
Start of SDP3430 support in "mainline" u-boot mainline code
Original Patch written by David Brownell
Um... this seems redundant information to me (the "From:" line and the Signed-off-by: line already say that David Brownell is the author.
On the other hand, I'm missing explanations what SDP3430 might be?
diff --git a/MAINTAINERS b/MAINTAINERS index e9db278..adc8a63 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -619,6 +619,7 @@ Guennadi Liakhovetski g.liakhovetski@gmx.de Nishanth Menon nm@ti.com
omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
- omap3_sdp ARM CORTEX-A8 (OMAP3xx SoC)
Please keep lists sorted.
General remark:
The board name is "SDP3430", right? The board directory name is board/ti/sdp3430/, which is ok. But then the configuration name should be "sdp3430", too.
diff --git a/MAKEALL b/MAKEALL index f0ed8ea..53620eb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -588,6 +588,7 @@ LIST_ARM_CORTEX_A8=" \ omap3_pandora \ omap3_zoom1 \ omap3_zoom2 \
- omap3_sdp \
"
Ditto.
######################################################################### diff --git a/Makefile b/Makefile index 5a4a109..2626147 100644 --- a/Makefile +++ b/Makefile @@ -3172,6 +3172,9 @@ omap3_zoom1_config : unconfig omap3_zoom2_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
+omap3_sdp_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3
Here again. Please check all other similar places.
...
+static const u32 gpmc_sdp_nor[] = {
- 0x00001200, /*CONF1 */
- 0x001F1F00, /*CONF2 */
- 0x00080802, /*CONF3 */
- 0x1C091C09, /*CONF4 */
- 0x01131F1F, /*CONF5 */
- 0x1F0F03C2, /*CONF6 */
- /*CONF7- computed as params */
+}; +static const u32 gpmc_sdp_debug[] = {
- 0x00611200, /*CONF1 FPGA needs WAIT1 line-active Low to function now.. */
- 0x001F1F01, /*CONF2 */
- 0x00080803, /*CONF3 */
- 0x1D091D09, /*CONF4 */
- 0x041D1F1F, /*CONF5 */
- 0x1D0904C4, /*CONF6 */
- /*CONF7- computed as params */
+}; +static const u32 gpmc_sdp_onenand[] = {
- 0x00001200, /*CONF1 */
- 0x000F0F01, /*CONF2 */
- 0x00030301, /*CONF3 */
- 0x0F040F04, /*CONF4 */
- 0x010F1010, /*CONF5 */
- 0x1F060000, /*CONF6 */
- /*CONF7- computed as params */
+};
+static const u32 gpmc_sdp_nand[] = {
- 0x00000800, /*CONF1 */
- 0x00141400, /*CONF2 */
- 0x00141400, /*CONF3 */
- 0x0F010F01, /*CONF4 */
- 0x010C1414, /*CONF5 */
- 0x1F040A80, /*CONF6 */
- /*CONF7- computed as params */
+};
Please comment what all these magic numbers mean.
+/******************************************************************************
- Routine: board_init
- Description: Early hardware init.
- *****************************************************************************/
Incorrect multiline comment style. Please fix globally.
...
diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h new file mode 100644 index 0000000..5ad2920 --- /dev/null +++ b/board/ti/sdp3430/sdp.h
...
+#define MUX_SDP3430()\
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
...
Incorrect indentation.
What exacty is the purpose of the comment? It does not carry any information. Seems just a waste of line length to me?
diff --git a/board/ti/sdp3430/u-boot.lds b/board/ti/sdp3430/u-boot.lds new file mode 100644 index 0000000..4ecc6dd --- /dev/null +++ b/board/ti/sdp3430/u-boot.lds
Is it really necessary that this board uses a custom linke rscript? Cannot we use a generic one for several boards?
diff --git a/include/configs/omap3_sdp.h b/include/configs/omap3_sdp.h new file mode 100644 index 0000000..176617a --- /dev/null +++ b/include/configs/omap3_sdp.h
This should be include/configs/sdp3430.h, accorsing to the board name.
...
+/*
- Size of malloc() pool
- */
+#define CONFIG_ENV_SIZE SZ_256K /* Total Size Environment */
Please do not use any of these SZ_ defines; they will be removed soon.
+#if 0 +#define CONSOLE_J9 /* else J8/UART1 (innermost) */ +#endif
Please delete - don't add dead code.
+/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
Strictly speaking the comment is wrong. The timeouts are in milliseconds.
+/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
Only a single blank line in places like thsi, please.
+/* commands to include */ +#include <config_cmd_default.h>
+#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_EXT2 /* EXT2 Support */
We consider it good style to keep such lists sorted.
...
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
/* works on */+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
Has this been tested? Can you really overwrite low memory? No exception vectors needed there?
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
There is no need to undefine non-existent variables.
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
Does this really work? Is low memory unused on this CPU? [Dorry for asking stupid questions, just want to be sure...]
Best regards,
Wolfgang Denk
Wolfgang Denk said the following on 09/23/2009 10:51 PM:
Dear Nishanth Menon,
In message 1253326918-1670-7-git-send-email-nm@ti.com you wrote:
--===============1247028818==
From: David Brownell david-b@pacbell.net
Start of SDP3430 support in "mainline" u-boot mainline code
Original Patch written by David Brownell
Um... this seems redundant information to me (the "From:" line and the Signed-off-by: line already say that David Brownell is the author.
Acked as previously discussed.
On the other hand, I'm missing explanations what SDP3430 might be?
hmm.. my bad. will fix. I should really be adding a few more lines to README.omap3. I will do that along with this change.
diff --git a/MAINTAINERS b/MAINTAINERS index e9db278..adc8a63 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -619,6 +619,7 @@ Guennadi Liakhovetski g.liakhovetski@gmx.de Nishanth Menon nm@ti.com
omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
- omap3_sdp ARM CORTEX-A8 (OMAP3xx SoC)
Please keep lists sorted.
Ack
General remark:
The board name is "SDP3430", right? The board directory name is board/ti/sdp3430/, which is ok. But then the configuration name should be "sdp3430", too.
Thanks.
+static const u32 gpmc_sdp_nand[] = {
- 0x00000800, /*CONF1 */
- 0x00141400, /*CONF2 */
- 0x00141400, /*CONF3 */
- 0x0F010F01, /*CONF4 */
- 0x010C1414, /*CONF5 */
- 0x1F040A80, /*CONF6 */
- /*CONF7- computed as params */
+};
Please comment what all these magic numbers mean.
these are configuration register values for GPMC (General Purpose Memory Controller) I should be indeed adding proper comments here. will do.
+/******************************************************************************
- Routine: board_init
- Description: Early hardware init.
- *****************************************************************************/
Incorrect multiline comment style. Please fix globally.
Ack
...
diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h new file mode 100644 index 0000000..5ad2920 --- /dev/null +++ b/board/ti/sdp3430/sdp.h
...
+#define MUX_SDP3430()\
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
...
Incorrect indentation.
(having spend almost an hr cleaning that piece of mux header up) groan.. any recommendations? is it because of the " "?
What exacty is the purpose of the comment? It does not carry any information. Seems just a waste of line length to me?
you mean /* SDRC_D0 */? hmmm.. might actually make sense if I am not using default mux mode 0 to note why I am using a new value.
diff --git a/board/ti/sdp3430/u-boot.lds b/board/ti/sdp3430/u-boot.lds new file mode 100644 index 0000000..4ecc6dd --- /dev/null +++ b/board/ti/sdp3430/u-boot.lds
Is it really necessary that this board uses a custom linke rscript? Cannot we use a generic one for several boards?
Ack.
diff --git a/include/configs/omap3_sdp.h b/include/configs/omap3_sdp.h new file mode 100644 index 0000000..176617a --- /dev/null +++ b/include/configs/omap3_sdp.h
This should be include/configs/sdp3430.h, accorsing to the board name.
Ack. I guess this is a hangover from the days where we wanted all omap3 boards to look similar.
...
+/*
- Size of malloc() pool
- */
+#define CONFIG_ENV_SIZE SZ_256K /* Total Size Environment */
Please do not use any of these SZ_ defines; they will be removed soon.
Ack..
+#if 0 +#define CONSOLE_J9 /* else J8/UART1 (innermost) */ +#endif
Please delete - don't add dead code.
CONSOLE_J9 is really an option, but I get your point here I should be using #undef even if i wanted to allow folks to tweak around.. #if 0s are *evil*
+/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
Strictly speaking the comment is wrong. The timeouts are in milliseconds.
gotcha. Ack.
+/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
Only a single blank line in places like thsi, please.
ok ok.. though I think you are nit picking ;)..
+/* commands to include */ +#include <config_cmd_default.h>
+#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_EXT2 /* EXT2 Support */
We consider it good style to keep such lists sorted.
I suppose Alphabetical sort?
...
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
/* works on */+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */Has this been tested? Can you really overwrite low memory? No exception vectors needed there?
yep it does boot :D.. exception vectors are stored in SRAM(which is a different address range).. but you have a point here -> will my sdram test actually overwrite my u-boot itself - heh heh, wont be much use then .. will check and fix. thanks
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
There is no need to undefine non-existent variables.
yep, will check
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */Does this really work? Is low memory unused on this CPU? [Dorry for asking stupid questions, just want to be sure...]
yes, it does -> see previous comment. Regards, Nishanth Menon
On Fri, 2009-09-18 at 21:21 -0500, Nishanth Menon wrote:
This is questionable if this is really required as the av_ static initalized values should have been loaded to sdram as part of the boot process and initialization should have been done.
Is there a reason you need to do this fixup? Based on your commit message its unclear if this patch is really needed...
Signed-off-by: Nishanth Menon <nm void mem_malloc_init(ulong start, ulong size) {
- u8 i;
- av_[0] = av_[1] = 0;
- for (i = 0; i < 128; i++)
av_[2 + i * 2] = av_[2 + i * 2 + 1] = bin_at(i);- mem_malloc_start = start; mem_malloc_end = start + size; mem_malloc_brk = start;
If you are going to do this fixup, av_ should not be initialized with values (you're currently doing the same initialization 2 times). In general, we could probably shave a bit off of U-Boot's size by leaving av_ uninitialized and implementing your manual calculation of av_ above, but I'm not sure why this change should be included in this patch series.
Best, Peter
Peter Tyser said the following on 09/19/2009 09:03 AM:
On Fri, 2009-09-18 at 21:21 -0500, Nishanth Menon wrote:
This is questionable if this is really required as the av_ static initalized values should have been loaded to sdram as part of the boot process and initialization should have been done.
Is there a reason you need to do this fixup? Based on your commit message its unclear if this patch is really needed...
Essentially, the loaded memory from the NOR looks all corrupted. I am unable to convince myself why the SDRAM is not updated with the static default inits - SDRAM corruption would have cracked everything else and scope measurement looks good too.
Signed-off-by: Nishanth Menon <nm void mem_malloc_init(ulong start, ulong size) {
- u8 i;
- av_[0] = av_[1] = 0;
- for (i = 0; i < 128; i++)
av_[2 + i * 2] = av_[2 + i * 2 + 1] = bin_at(i);- mem_malloc_start = start; mem_malloc_end = start + size; mem_malloc_brk = start;
If you are going to do this fixup, av_ should not be initialized with values (you're currently doing the same initialization 2 times). In general, we could probably shave a bit off of U-Boot's size by leaving av_ uninitialized and implementing your manual calculation of av_ above,
yep.. missed finishing that out.. :(
but I'm not sure why this change should be included in this patch series.
This patch is need for booting SDP3430 from NOR flash.
Regards, Nishanth Menon
On Sat, 2009-09-19 at 10:37 -0500, Nishanth Menon wrote:
Peter Tyser said the following on 09/19/2009 09:03 AM:
On Fri, 2009-09-18 at 21:21 -0500, Nishanth Menon wrote:
This is questionable if this is really required as the av_ static initalized values should have been loaded to sdram as part of the boot process and initialization should have been done.
Is there a reason you need to do this fixup? Based on your commit message its unclear if this patch is really needed...
Essentially, the loaded memory from the NOR looks all corrupted. I am unable to convince myself why the SDRAM is not updated with the static default inits - SDRAM corruption would have cracked everything else and scope measurement looks good too.
Signed-off-by: Nishanth Menon <nm void mem_malloc_init(ulong start, ulong size) {
- u8 i;
- av_[0] = av_[1] = 0;
- for (i = 0; i < 128; i++)
av_[2 + i * 2] = av_[2 + i * 2 + 1] = bin_at(i);- mem_malloc_start = start; mem_malloc_end = start + size; mem_malloc_brk = start;
If you are going to do this fixup, av_ should not be initialized with values (you're currently doing the same initialization 2 times). In general, we could probably shave a bit off of U-Boot's size by leaving av_ uninitialized and implementing your manual calculation of av_ above,
yep.. missed finishing that out.. :(
but I'm not sure why this change should be included in this patch series.
This patch is need for booting SDP3430 from NOR flash.
Once the initialized values for av_ are removed, this patch would be useful for everyone. It looks like it removes a few hundred bytes of code size, so I'm all for it. I'd be a bit concerned about why your board wasn't loading the initialized av_ table though. Seems like it would be indicative of a larger problem...
So in any case, I like the patch because it reduces code size, but I don't think the explanation or commit message of "for an unknown reason it makes my board work" commit message is the best. Its affecting every board, so at a minimum it should describe how it benefits them - eg changing static initialization into dynamic initialization saves some space.
That's my $.02, feel free to proceed as you see fit as I don't have any real power here:)
Best, Peter
Dear Nishanth Menon,
In message 4AB4FAD6.20002@gmail.com you wrote:
This patch is need for booting SDP3430 from NOR flash.
There must be some problem elsewhere. It's extremely unlikely that just a single board has this problem; it's much more likely that there is a bug in the board port, and/or it's linker script.
Best regards,
Wolfgang Denk
Wolfgang Denk said the following on 09/23/2009 11:04 PM:
Dear Nishanth Menon,
In message 4AB4FAD6.20002@gmail.com you wrote:
This patch is need for booting SDP3430 from NOR flash.
There must be some problem elsewhere. It's extremely unlikely that just a single board has this problem; it's much more likely that there is a bug in the board port, and/or it's linker script.
Yes, I tend to agree on this. but that said, as pointed out earlier in this thread by Peter Tyser, it might actually save a few bytes of code.. but I need to really root cause this out before sending out patchset v2. Regards, Nishanth Menon
Dear Nishanth Menon,
In message 1253326918-1670-2-git-send-email-nm@ti.com you wrote:
Defaults are for infenion DDR timings.
Typo: Infineon.
Best regards,
Wolfgang Denk
participants (5)
-
Nishanth Menon -
Nishanth Menon -
Paulraj, Sandeep -
Peter Tyser -
Wolfgang Denk