[PATCH v1 0/4] ulp wdog

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[PATCH] ARM: dts: stm32: Remove...

Alice Guo (OSS)

9 Oct 2022 9 Oct '22

10 a.m.

Alice Guo (3): watchdog: ulp_wdog: Update watchdog driver for imx93 watchdog: ulp_wdog: enable watchdog interrupt on imx93 watchdog: ulp_wdog: add driver model for ulp watchdog driver

Ye Li (1): ulp_wdog: Update ulp wdog driver for 32bits command

drivers/watchdog/ulp_wdog.c | 159 ++++++++++++++++++++++++++++++------ 1 file changed, 135 insertions(+), 24 deletions(-)

-- 2.17.1

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Alice Guo (OSS)

9 Oct 9 Oct

10 a.m.

New subject: [PATCH v1 1/4] ulp_wdog: Update ulp wdog driver for 32bits command

From: Ye Li ye.li@nxp.com

To use 32bits refresh and unlock command as default, check the CMD32EN bit to select the corresponding commands.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Alice Guo alice.guo@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com --- drivers/watchdog/ulp_wdog.c | 52 +++++++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 16 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index ecd35ef22a..c40e785d0a 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -28,11 +28,15 @@ struct wdog_regs { #define UNLOCK_WORD0 0xC520 /* 1st unlock word */ #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */

+#define UNLOCK_WORD 0xD928C520 /* unlock word */ +#define REFRESH_WORD 0xB480A602 /* refresh word */ + #define WDGCS_WDGE BIT(7) #define WDGCS_WDGUPDATE BIT(5)

#define WDGCS_RCS BIT(10) #define WDGCS_ULK BIT(11) +#define WDGCS_CMD32EN BIT(13) #define WDGCS_FLG BIT(14)

#define WDG_BUS_CLK (0x0) @@ -52,20 +56,30 @@ void hw_watchdog_reset(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;

- dmb(); - __raw_writel(REFRESH_WORD0, &wdog->cnt); - __raw_writel(REFRESH_WORD1, &wdog->cnt); - dmb(); + if (readl(&wdog->cs) & WDGCS_CMD32EN) { + writel(REFRESH_WORD, &wdog->cnt); + } else { + dmb(); + __raw_writel(REFRESH_WORD0, &wdog->cnt); + __raw_writel(REFRESH_WORD1, &wdog->cnt); + dmb(); + } }

void hw_watchdog_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - - dmb(); - __raw_writel(UNLOCK_WORD0, &wdog->cnt); - __raw_writel(UNLOCK_WORD1, &wdog->cnt); - dmb(); + u32 cmd32 = 0; + + if (readl(&wdog->cs) & WDGCS_CMD32EN) { + writel(UNLOCK_WORD, &wdog->cnt); + cmd32 = WDGCS_CMD32EN; + } else { + dmb(); + __raw_writel(UNLOCK_WORD0, &wdog->cnt); + __raw_writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + }

/* Wait WDOG Unlock */ while (!(readl(&wdog->cs) & WDGCS_ULK)) @@ -75,7 +89,7 @@ void hw_watchdog_init(void) writel(0, &wdog->win);

/* setting 1-kHz clock source, enable counter running, and clear interrupt */ - writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs); + writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs);

/* Wait WDOG reconfiguration */ while (!(readl(&wdog->cs) & WDGCS_RCS)) @@ -87,11 +101,17 @@ void hw_watchdog_init(void) void reset_cpu(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - - dmb(); - __raw_writel(UNLOCK_WORD0, &wdog->cnt); - __raw_writel(UNLOCK_WORD1, &wdog->cnt); - dmb(); + u32 cmd32 = 0; + + if (readl(&wdog->cs) & WDGCS_CMD32EN) { + writel(UNLOCK_WORD, &wdog->cnt); + cmd32 = WDGCS_CMD32EN; + } else { + dmb(); + __raw_writel(UNLOCK_WORD0, &wdog->cnt); + __raw_writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + }

/* Wait WDOG Unlock */ while (!(readl(&wdog->cs) & WDGCS_ULK)) @@ -101,7 +121,7 @@ void reset_cpu(void) writel(0, &wdog->win);

/* enable counter running */ - writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs); + writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);

/* Wait WDOG reconfiguration */ while (!(readl(&wdog->cs) & WDGCS_RCS))

-- 2.17.1

Stefan Roese

18 Oct 18 Oct

8:17 a.m.

New subject: [PATCH v1 1/4] ulp_wdog: Update ulp wdog driver for 32bits command

On 09.10.22 10:00, Alice Guo (OSS) wrote:

...

From: Ye Li ye.li@nxp.com

To use 32bits refresh and unlock command as default, check the CMD32EN bit to select the corresponding commands.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Alice Guo alice.guo@nxp.com Reviewed-by: Peng Fan peng.fan@nxp.com

drivers/watchdog/ulp_wdog.c | 52 +++++++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 16 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index ecd35ef22a..c40e785d0a 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -28,11 +28,15 @@ struct wdog_regs { #define UNLOCK_WORD0 0xC520 /* 1st unlock word */ #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */

+#define UNLOCK_WORD 0xD928C520 /* unlock word */ +#define REFRESH_WORD 0xB480A602 /* refresh word */

#define WDGCS_WDGE BIT(7) #define WDGCS_WDGUPDATE BIT(5)

#define WDGCS_RCS BIT(10) #define WDGCS_ULK BIT(11)

+#define WDGCS_CMD32EN BIT(13) #define WDGCS_FLG BIT(14)

#define WDG_BUS_CLK (0x0) @@ -52,20 +56,30 @@ void hw_watchdog_reset(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;

dmb();

__raw_writel(REFRESH_WORD0, &wdog->cnt);

__raw_writel(REFRESH_WORD1, &wdog->cnt);

dmb();
if (readl(&wdog->cs) & WDGCS_CMD32EN) {
writel(REFRESH_WORD, &wdog->cnt);
} else {
dmb();
__raw_writel(REFRESH_WORD0, &wdog->cnt);
__raw_writel(REFRESH_WORD1, &wdog->cnt);
dmb();
} }

void hw_watchdog_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
dmb();

__raw_writel(UNLOCK_WORD0, &wdog->cnt);

__raw_writel(UNLOCK_WORD1, &wdog->cnt);

dmb();
u32 cmd32 = 0;

if (readl(&wdog->cs) & WDGCS_CMD32EN) {
writel(UNLOCK_WORD, &wdog->cnt);
cmd32 = WDGCS_CMD32EN;
} else {
dmb();
__raw_writel(UNLOCK_WORD0, &wdog->cnt);
__raw_writel(UNLOCK_WORD1, &wdog->cnt);
dmb();
}

/* Wait WDOG Unlock */ while (!(readl(&wdog->cs) & WDGCS_ULK))
@@ -75,7 +89,7 @@ void hw_watchdog_init(void) writel(0, &wdog->win);

/* setting 1-kHz clock source, enable counter running, and clear interrupt */

writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs);

writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs);

I know you're just copying / re-structuring old code here, but could you please also change this minor coding style issue:

WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) -> WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8)

Other than this:

Reviewed-by: Stefan Roese sr@denx.de

Thanks, Stefan

...

/* Wait WDOG reconfiguration */ while (!(readl(&wdog->cs) & WDGCS_RCS)) @@ -87,11 +101,17 @@ void hw_watchdog_init(void) void reset_cpu(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;

dmb();

__raw_writel(UNLOCK_WORD0, &wdog->cnt);

__raw_writel(UNLOCK_WORD1, &wdog->cnt);

dmb();
u32 cmd32 = 0;

if (readl(&wdog->cs) & WDGCS_CMD32EN) {
writel(UNLOCK_WORD, &wdog->cnt);
cmd32 = WDGCS_CMD32EN;
} else {
dmb();
__raw_writel(UNLOCK_WORD0, &wdog->cnt);
__raw_writel(UNLOCK_WORD1, &wdog->cnt);
dmb();
}

/* Wait WDOG Unlock */ while (!(readl(&wdog->cs) & WDGCS_ULK))
@@ -101,7 +121,7 @@ void reset_cpu(void) writel(0, &wdog->win);

/* enable counter running */

writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);

writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);

/* Wait WDOG reconfiguration */ while (!(readl(&wdog->cs) & WDGCS_RCS))

Viele Grüße, Stefan Roese

-- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de

Alice Guo (OSS)

9 Oct 9 Oct

10 a.m.

New subject: [PATCH v1 2/4] watchdog: ulp_wdog: Update watchdog driver for imx93

From: Alice Guo alice.guo@nxp.com

The WDOG clocks are sourced from the fixed 32KHz (lpo_clk).When the timeout period exceeds 2 seconds, the value written to the TOVAL register is larger than 16-bit can represent. Enabling watchdog prescaler to solve this problem.

Signed-off-by: Alice Guo alice.guo@nxp.com --- drivers/watchdog/ulp_wdog.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index c40e785d0a..843f95aa4f 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -36,6 +36,7 @@ struct wdog_regs {

#define WDGCS_RCS BIT(10) #define WDGCS_ULK BIT(11) +#define WDOG_CS_PRES BIT(12) #define WDGCS_CMD32EN BIT(13) #define WDGCS_FLG BIT(14)

@@ -89,7 +90,12 @@ void hw_watchdog_init(void) writel(0, &wdog->win);

/* setting 1-kHz clock source, enable counter running, and clear interrupt */ +#if defined(CONFIG_ARCH_IMX9) + writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8) | + WDGCS_FLG | WDOG_CS_PRES), &wdog->cs); +#else writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs); +#endif

/* Wait WDOG reconfiguration */ while (!(readl(&wdog->cs) & WDGCS_RCS)) @@ -117,11 +123,15 @@ void reset_cpu(void) while (!(readl(&wdog->cs) & WDGCS_ULK)) ;

- hw_watchdog_set_timeout(5); /* 5ms timeout */ + hw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout for imx93 */ writel(0, &wdog->win);

/* enable counter running */ +#if defined(CONFIG_ARCH_IMX9) + writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES), &wdog->cs); +#else writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs); +#endif

/* Wait WDOG reconfiguration */ while (!(readl(&wdog->cs) & WDGCS_RCS))

-- 2.17.1

Stefan Roese

18 Oct 18 Oct

8:19 a.m.

New subject: [PATCH v1 2/4] watchdog: ulp_wdog: Update watchdog driver for imx93

On 09.10.22 10:00, Alice Guo (OSS) wrote:

...

From: Alice Guo alice.guo@nxp.com

The WDOG clocks are sourced from the fixed 32KHz (lpo_clk).When the timeout period exceeds 2 seconds, the value written to the TOVAL register is larger than 16-bit can represent. Enabling watchdog prescaler to solve this problem.

Signed-off-by: Alice Guo alice.guo@nxp.com

drivers/watchdog/ulp_wdog.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index c40e785d0a..843f95aa4f 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -36,6 +36,7 @@ struct wdog_regs {

#define WDGCS_RCS BIT(10) #define WDGCS_ULK BIT(11) +#define WDOG_CS_PRES BIT(12) #define WDGCS_CMD32EN BIT(13) #define WDGCS_FLG BIT(14)

@@ -89,7 +90,12 @@ void hw_watchdog_init(void) writel(0, &wdog->win);

/* setting 1-kHz clock source, enable counter running, and clear interrupt */ +#if defined(CONFIG_ARCH_IMX9)
writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8) |
      WDGCS_FLG | WDOG_CS_PRES), &wdog->cs);
+#else writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs); +#endif

Could you please change from using #ifdef to if (IS_ENABLED)?

if (IS_ENABLED(CONFIG_ARCH_IMX9)) { ...

...

/* Wait WDOG reconfiguration */ while (!(readl(&wdog->cs) & WDGCS_RCS)) @@ -117,11 +123,15 @@ void reset_cpu(void) while (!(readl(&wdog->cs) & WDGCS_ULK)) ;

hw_watchdog_set_timeout(5); /* 5ms timeout */

hw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout for imx93 */ writel(0, &wdog->win);

/* enable counter running */

+#if defined(CONFIG_ARCH_IMX9)

writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES), &wdog->cs);

+#else writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs); +#endif

Here as well please.

Thanks, Stefan

Alice Guo (OSS)

9 Oct 9 Oct

10 a.m.

New subject: [PATCH v1 3/4] watchdog: ulp_wdog: enable watchdog interrupt on imx93

From: Alice Guo alice.guo@nxp.com

The reset source of the external PMIC on i.MX93 is WDOG_ANY PAD and the source of WDOG_ANY PAD is interrupt. Therefore, using PMIC to reset needs to enable the watchdog interrupt.

Signed-off-by: Alice Guo alice.guo@nxp.com --- drivers/watchdog/ulp_wdog.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 843f95aa4f..49f8900cd3 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -39,6 +39,7 @@ struct wdog_regs { #define WDOG_CS_PRES BIT(12) #define WDGCS_CMD32EN BIT(13) #define WDGCS_FLG BIT(14) +#define WDGCS_INT BIT(6)

#define WDG_BUS_CLK (0x0) #define WDG_LPO_CLK (0x1) @@ -92,7 +93,7 @@ void hw_watchdog_init(void) /* setting 1-kHz clock source, enable counter running, and clear interrupt */ #if defined(CONFIG_ARCH_IMX9) writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8) | - WDGCS_FLG | WDOG_CS_PRES), &wdog->cs); + WDGCS_FLG | WDOG_CS_PRES | WDGCS_INT), &wdog->cs); #else writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs); #endif @@ -128,7 +129,7 @@ void reset_cpu(void)

/* enable counter running */ #if defined(CONFIG_ARCH_IMX9) - writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES), &wdog->cs); + writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES | WDGCS_INT), &wdog->cs); #else writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs); #endif

-- 2.17.1

Alice Guo (OSS)

10:01 a.m.

New subject: [PATCH v1 4/4] watchdog: ulp_wdog: add driver model for ulp watchdog driver

From: Alice Guo alice.guo@nxp.com

Enable driver model for ulp watchdog timer. When CONFIG_WDT=y and the status of device node is "okay", initr_watchdog will be called and finally calls ulp_wdt_probe() and ulp_wdt_start().

Signed-off-by: Alice Guo alice.guo@nxp.com Reviewed-by: Ye Li ye.li@nxp.com --- drivers/watchdog/ulp_wdog.c | 94 ++++++++++++++++++++++++++++++++++--- 1 file changed, 87 insertions(+), 7 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 49f8900cd3..93cf6e253d 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -7,6 +7,8 @@ #include <cpu_func.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> +#include <dm.h> +#include <wdt.h>

/* * MX7ULP WDOG Register Map @@ -18,6 +20,11 @@ struct wdog_regs { u32 win; };

+struct ulp_wdt_priv { + struct wdog_regs *wdog; + u32 clk_rate; +}; + #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS #define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500 #endif @@ -46,6 +53,9 @@ struct wdog_regs { #define WDG_32KHZ_CLK (0x2) #define WDG_EXT_CLK (0x3)

+#define CLK_RATE_1KHZ 1000 +#define CLK_RATE_32KHZ 125 + void hw_watchdog_set_timeout(u16 val) { /* setting timeout value */ @@ -54,10 +64,8 @@ void hw_watchdog_set_timeout(u16 val) writel(val, &wdog->toval); }

-void hw_watchdog_reset(void) +void ulp_watchdog_reset(struct wdog_regs *wdog) { - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - if (readl(&wdog->cs) & WDGCS_CMD32EN) { writel(REFRESH_WORD, &wdog->cnt); } else { @@ -68,9 +76,8 @@ void hw_watchdog_reset(void) } }

-void hw_watchdog_init(void) +void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout) { - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; u32 cmd32 = 0;

if (readl(&wdog->cs) & WDGCS_CMD32EN) { @@ -87,7 +94,7 @@ void hw_watchdog_init(void) while (!(readl(&wdog->cs) & WDGCS_ULK)) ;

- hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS); + hw_watchdog_set_timeout(timeout); writel(0, &wdog->win);

/* setting 1-kHz clock source, enable counter running, and clear interrupt */ @@ -102,7 +109,21 @@ void hw_watchdog_init(void) while (!(readl(&wdog->cs) & WDGCS_RCS)) ;

- hw_watchdog_reset(); + ulp_watchdog_reset(wdog); +} + +void hw_watchdog_reset(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; + + ulp_watchdog_reset(wdog); +} + +void hw_watchdog_init(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; + + ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS); }

void reset_cpu(void) @@ -142,3 +163,62 @@ void reset_cpu(void)

while (1); } + +static int ulp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct ulp_wdt_priv *priv = dev_get_priv(dev); + u64 timeout = 0; + + timeout = (timeout_ms * priv->clk_rate) / 1000; + if (timeout > U16_MAX) + return -EINVAL; + + ulp_watchdog_init(priv->wdog, (u16)timeout); + + return 0; +} + +static int ulp_wdt_reset(struct udevice *dev) +{ + struct ulp_wdt_priv *priv = dev_get_priv(dev); + + ulp_watchdog_reset(priv->wdog); + + return 0; +} + +static int ulp_wdt_probe(struct udevice *dev) +{ + struct ulp_wdt_priv *priv = dev_get_priv(dev); + + priv->wdog = dev_read_addr_ptr(dev); + if (!priv->wdog) + return -EINVAL; + + priv->clk_rate = (u32)dev_get_driver_data(dev); + if (!priv->clk_rate) + return -EINVAL; + + return 0; +} + +static const struct wdt_ops ulp_wdt_ops = { + .start = ulp_wdt_start, + .reset = ulp_wdt_reset, +}; + +static const struct udevice_id ulp_wdt_ids[] = { + { .compatible = "fsl,imx7ulp-wdt", .data = CLK_RATE_1KHZ }, + { .compatible = "fsl,imx8ulp-wdt", .data = CLK_RATE_1KHZ }, + { .compatible = "fsl,imx93-wdt", .data = CLK_RATE_32KHZ }, + {} +}; + +U_BOOT_DRIVER(ulp_wdt) = { + .name = "ulp_wdt", + .id = UCLASS_WDT, + .of_match = ulp_wdt_ids, + .priv_auto = sizeof(struct ulp_wdt_priv), + .probe = ulp_wdt_probe, + .ops = &ulp_wdt_ops, +};

-- 2.17.1

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Alice Guo (OSS)
Stefan Roese