This is not used anywhere, so drop it.

Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com --- include/configs/socfpga_common.h | 1 - 1 file changed, 1 deletion(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c9cbf8f5e3..f182e9e71b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -280,7 +280,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);

/* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 #endif

The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference.

Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com --- include/configs/socfpga_common.h | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f182e9e71b..181af9b646 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -275,12 +275,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);

/* SPL QSPI boot support */ #ifdef CONFIG_SPL_SPI_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 +#endif #endif

/* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 +#endif #endif

/*

The Kconfig checked for SoCFPGA Arria10 as a platform, instead of checking for specific board configuration, which works with one single platform in tree, but not with multiple. Fix it.

Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com --- board/altera/arria10-socdk/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig index b80cc6d6f9..621dc97024 100644 --- a/board/altera/arria10-socdk/Kconfig +++ b/board/altera/arria10-socdk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_SOCFPGA_ARRIA10 +if TARGET_SOCFPGA_ARRIA10_SOCDK

config SYS_CPU default "armv7"

On Wed, 2019-03-06 at 22:05 +0100, Marek Vasut wrote:

The bootrom seems to leave the D-cache in messed up state, make sure the SPL disables it so it can not interfere with operation.

Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com

Reviewed-by: Tien Fong Chee tien.fong.chee@intel.com

---

arch/arm/mach-socfpga/spl_a10.c         | 2 ++  include/configs/socfpga_arria10_socdk.h | 2 --  2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach- socfpga/spl_a10.c index c97eacb424..c8e73d47c0 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -77,6 +77,8 @@ void spl_board_init(void)    void board_init_f(ulong dummy)  {

• dcache_disable();

socfpga_init_security_policies();   socfpga_sdram_remap_zero();   diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 58e446b60a..0f116fbf2d 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -15,8 +15,6 @@  /*   * U-Boot general configurations   */ -/* Cache options */ -#define CONFIG_SYS_DCACHE_OFF    /* Memory configurations  */  #define PHYS_SDRAM_1_SIZE 0x40000000