On Sun, Oct 1, 2023 at 10:17 PM Jonas Karlman jonas@kwiboo.se wrote:

rx_pkt is allocated and not used for anything, remove it.

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com

---

v2:

• Collect r-b tag

drivers/net/dwc_eth_qos.c | 11 ----------- drivers/net/dwc_eth_qos.h | 1 - 2 files changed, 12 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 1e92bd9ca9c0..555eaee3bbc3 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1314,22 +1314,12 @@ static int eqos_probe_resources_core(struct udevice *dev) } debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);

•   eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
  

•   if (!eqos->rx_pkt) {
  

•           debug("%s: malloc(rx_pkt) failed\n", __func__);
  

•           ret = -ENOMEM;
  

•           goto err_free_rx_dma_buf;
  

•   }
  

•   debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
  

•   eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
                    EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
  
    debug("%s: OK\n", __func__);
    return 0;
  
  

-err_free_rx_dma_buf:

•   free(eqos->rx_dma_buf);
  

err_free_tx_dma_buf: free(eqos->tx_dma_buf); err_free_descs: @@ -1348,7 +1338,6 @@ static int eqos_remove_resources_core(struct udevice *dev)

    debug("%s(dev=%p):\n", __func__, dev);

•   free(eqos->rx_pkt);
    free(eqos->rx_dma_buf);
    free(eqos->tx_dma_buf);
    eqos_free_descs(eqos->rx_descs);
  

diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index a6b719af809f..06a082da72ef 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -273,7 +273,6 @@ struct eqos_priv { unsigned int desc_per_cacheline; void *tx_dma_buf; void *rx_dma_buf;

•   void *rx_pkt;
    bool started;
    bool reg_access_ok;
    bool clk_ck_enabled;
  

-- 2.42.0

Reviewed-by: Ramon Fried rfried.dev@gmail.com

On Sun, Oct 1, 2023 at 10:17 PM Jonas Karlman jonas@kwiboo.se wrote:

Return error code when phy_connect fails or no link can be established.

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com

---

v2:

• Collect r-b tag

drivers/net/dwc_eth_qos.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 555eaee3bbc3..7565e716823a 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -811,6 +811,7 @@ static int eqos_start(struct udevice *dev)

            if (!eqos->phy) {
                    pr_err("phy_connect() failed");

•                   ret = -ENODEV;
                    goto err_stop_resets;
            }
  
  

@@ -838,6 +839,7 @@ static int eqos_start(struct udevice *dev)

    if (!eqos->phy->link) {
            pr_err("No link");

•           ret = -EAGAIN;
            goto err_shutdown_phy;
    }
  
  

-- 2.42.0

Reviewed-by: Ramon Fried rfried.dev@gmail.com

On Sun, Oct 1, 2023 at 10:17 PM Jonas Karlman jonas@kwiboo.se wrote:

Remove spam of RX packet not available debug messages when waiting to receive a packet.

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com

---

v2:

• Collect r-b tag

drivers/net/dwc_eth_qos.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 7565e716823a..24fb3fac1f12 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1193,14 +1193,12 @@ static int eqos_recv(struct udevice *dev, int flags, uchar **packetp) struct eqos_desc *rx_desc; int length;

•   debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
  

•   rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true);
    eqos->config->ops->eqos_inval_desc(rx_desc);
  

•   if (rx_desc->des3 & EQOS_DESC3_OWN) {
  

•           debug("%s: RX packet not available\n", __func__);
  

•   if (rx_desc->des3 & EQOS_DESC3_OWN)
            return -EAGAIN;
  

•   }
  

•   debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
  
    *packetp = eqos->rx_dma_buf +
            (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
  

-- 2.42.0

Reviewed-by: Ramon Fried rfried.dev@gmail.com

On Sun, Oct 1, 2023 at 10:17 PM Jonas Karlman jonas@kwiboo.se wrote:

Add a new glue driver for Rockchip SoCs, i.e RK3568, with a GMAC based on Synopsys DWC Ethernet QoS IP.

rk_gmac_ops was ported from linux commit: 3bb3d6b1c195 ("net: stmmac: Add RK3566/RK3568 SoC support")

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com

---

Cc: David Wu david.wu@rock-chips.com Cc: Ezequiel Garcia ezequiel@collabora.com

---

v2:

• Add comment about ported code intentionally left close to 1:1 with linux
• Collect r-b tag

drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 8 +- drivers/net/dwc_eth_qos.h | 2 + drivers/net/dwc_eth_qos_rockchip.c | 357 +++++++++++++++++++++++++++++ 5 files changed, 374 insertions(+), 2 deletions(-) create mode 100644 drivers/net/dwc_eth_qos_rockchip.c

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 0ed39a61e4de..29304fd77759 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -225,6 +225,14 @@ config DWC_ETH_QOS_IMX The Synopsys Designware Ethernet QOS IP block with the specific configuration used in IMX soc.

+config DWC_ETH_QOS_ROCKCHIP

•   bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs"
  

•   depends on DWC_ETH_QOS
  

•   select DM_ETH_PHY
  

•   help
  

•     The Synopsys Designware Ethernet QOS IP block with specific
  

•     configuration used in Rockchip SoCs.
  

config DWC_ETH_QOS_STM32 bool "Synopsys DWC Ethernet QOS device support for STM32" depends on DWC_ETH_QOS diff --git a/drivers/net/Makefile b/drivers/net/Makefile index d4af253b6f28..1d444f5b4a69 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o +obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o obj-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 24fb3fac1f12..9fb98a2c3c74 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1707,7 +1707,12 @@ static const struct udevice_id eqos_ids[] = { .data = (ulong)&eqos_imx_config }, #endif

+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)

•   {
  

•           .compatible = "rockchip,rk3568-gmac",
  

•           .data = (ulong)&eqos_rockchip_config
  

•   },
  

+#endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM) { .compatible = "qcom,qcs404-ethqos", @@ -1720,7 +1725,6 @@ static const struct udevice_id eqos_ids[] = { .data = (ulong)&eqos_jh7110_config }, #endif

•   { }
  

};

diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index 06a082da72ef..e3222e1e17e5 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -82,6 +82,7 @@ struct eqos_mac_regs { #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8 +#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) @@ -287,5 +288,6 @@ void eqos_flush_buffer_generic(void *buf, size_t size); int eqos_null_ops(struct udevice *dev);

extern struct eqos_config eqos_imx_config; +extern struct eqos_config eqos_rockchip_config; extern struct eqos_config eqos_qcom_config; extern struct eqos_config eqos_jh7110_config; diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c new file mode 100644 index 000000000000..05edc098f50d --- /dev/null +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*

• • Copyright Contributors to the U-Boot project.
• • rk_gmac_ops ported from linux drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
• • Ported code is intentionally left as close as possible with linux counter
• • part in order to simplify future porting of fixes and support for other SoCs.
• */

+#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <net.h> +#include <phy.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> +#include <asm/gpio.h> +#include <linux/delay.h>

+#include "dwc_eth_qos.h"

+struct rk_gmac_ops {

•   const char *compatible;
  

•   int (*set_to_rgmii)(struct udevice *dev,
  

•                       int tx_delay, int rx_delay);
  

•   int (*set_to_rmii)(struct udevice *dev);
  

•   int (*set_gmac_speed)(struct udevice *dev);
  

•   u32 regs[3];
  

+};

+struct rockchip_platform_data {

•   struct reset_ctl_bulk resets;
  

•   const struct rk_gmac_ops *ops;
  

•   int id;
  

•   struct regmap *grf;
  

+};

+#define HIWORD_UPDATE(val, mask, shift) \

•           ((val) << (shift) | (mask) << ((shift) + 16))
  

+#define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16)) +#define GRF_CLR_BIT(nr) (BIT((nr) + 16))

+#define RK3568_GRF_GMAC0_CON0 0x0380 +#define RK3568_GRF_GMAC0_CON1 0x0384 +#define RK3568_GRF_GMAC1_CON0 0x0388 +#define RK3568_GRF_GMAC1_CON1 0x038c

+/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ +#define RK3568_GMAC_PHY_INTF_SEL_RGMII \

•           (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
  

+#define RK3568_GMAC_PHY_INTF_SEL_RMII \

•           (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
  

+#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) +#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) +#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) +#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) +#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) +#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)

+/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ +#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) +#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)

+static int rk3568_set_to_rgmii(struct udevice *dev,

•                          int tx_delay, int rx_delay)
  

+{

•   struct eth_pdata *pdata = dev_get_plat(dev);
  

•   struct rockchip_platform_data *data = pdata->priv_pdata;
  

•   u32 con0, con1;
  

•   con0 = (data->id == 1) ? RK3568_GRF_GMAC1_CON0 :
  

•                            RK3568_GRF_GMAC0_CON0;
  

•   con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
  

•                            RK3568_GRF_GMAC0_CON1;
  

•   regmap_write(data->grf, con0,
  

•                RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
  

•                RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
  

•   regmap_write(data->grf, con1,
  

•                RK3568_GMAC_PHY_INTF_SEL_RGMII |
  

•                RK3568_GMAC_RXCLK_DLY_ENABLE |
  

•                RK3568_GMAC_TXCLK_DLY_ENABLE);
  

•   return 0;
  

+}

+static int rk3568_set_to_rmii(struct udevice *dev) +{

•   struct eth_pdata *pdata = dev_get_plat(dev);
  

•   struct rockchip_platform_data *data = pdata->priv_pdata;
  

•   u32 con1;
  

•   con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
  

•                            RK3568_GRF_GMAC0_CON1;
  

•   regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
  

•   return 0;
  

+}

+static int rk3568_set_gmac_speed(struct udevice *dev) +{

•   struct eqos_priv *eqos = dev_get_priv(dev);
  

•   ulong rate;
  

•   int ret;
  

•   switch (eqos->phy->speed) {
  

•   case SPEED_10:
  

•           rate = 2500000;
  

•           break;
  

•   case SPEED_100:
  

•           rate = 25000000;
  

•           break;
  

•   case SPEED_1000:
  

•           rate = 125000000;
  

•           break;
  

•   default:
  

•           return -EINVAL;
  

•   }
  

•   ret = clk_set_rate(&eqos->clk_tx, rate);
  

•   if (ret < 0)
  

•           return ret;
  

•   return 0;
  

+}

+static const struct rk_gmac_ops rk_gmac_ops[] = {

•   {
  

•           .compatible = "rockchip,rk3568-gmac",
  

•           .set_to_rgmii = rk3568_set_to_rgmii,
  

•           .set_to_rmii = rk3568_set_to_rmii,
  

•           .set_gmac_speed = rk3568_set_gmac_speed,
  

•           .regs = {
  

•                   0xfe2a0000, /* gmac0 */
  

•                   0xfe010000, /* gmac1 */
  

•                   0x0, /* sentinel */
  

•           },
  

•   },
  

•   { }
  

+};

+static const struct rk_gmac_ops *get_rk_gmac_ops(struct udevice *dev) +{

•   const struct rk_gmac_ops *ops = rk_gmac_ops;
  

•   while (ops->compatible) {
  

•           if (device_is_compatible(dev, ops->compatible))
  

•                   return ops;
  

•           ops++;
  

•   }
  

•   return NULL;
  

+}

+static int eqos_probe_resources_rk(struct udevice *dev) +{

•   struct eqos_priv *eqos = dev_get_priv(dev);
  

•   struct eth_pdata *pdata = dev_get_plat(dev);
  

•   struct rockchip_platform_data *data;
  

•   int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE;
  

•   int ret;
  

•   data = calloc(1, sizeof(struct rockchip_platform_data));
  

•   if (!data)
  

•           return -ENOMEM;
  

•   data->ops = get_rk_gmac_ops(dev);
  

•   if (!data->ops) {
  

•           ret = -EINVAL;
  

•           goto err_free;
  

•   }
  

•   for (int i = 0; data->ops->regs[i]; i++) {
  

•           if (data->ops->regs[i] == (u32)eqos->regs) {
  

•                   data->id = i;
  

•                   break;
  

•           }
  

•   }
  

•   pdata->priv_pdata = data;
  

•   pdata->phy_interface = eqos->config->interface(dev);
  

•   pdata->max_speed = eqos->max_speed;
  

•   if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
  

•           pr_err("Invalid PHY interface\n");
  

•           ret = -EINVAL;
  

•           goto err_free;
  

•   }
  

•   data->grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
  

•   if (IS_ERR(data->grf)) {
  

•           dev_err(dev, "Missing rockchip,grf property\n");
  

•           ret = -EINVAL;
  

•           goto err_free;
  

•   }
  

•   ret = reset_get_bulk(dev, &data->resets);
  

•   if (ret < 0)
  

•           goto err_free;
  

•   reset_assert_bulk(&data->resets);
  

•   ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
  

•   if (ret) {
  

•           dev_dbg(dev, "clk_get_by_name(stmmaceth) failed: %d", ret);
  

•           goto err_release_resets;
  

•   }
  

•   ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
  

•   if (ret) {
  

•           dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
  

•           goto err_free_clk_master_bus;
  

•   }
  

•   /* snps,reset props are deprecated, do bare minimum to support them */
  

•   if (dev_read_bool(dev, "snps,reset-active-low"))
  

•           reset_flags |= GPIOD_ACTIVE_LOW;
  

•   dev_read_u32_array(dev, "snps,reset-delays-us", eqos->reset_delays, 3);
  

•   gpio_request_by_name(dev, "snps,reset-gpio", 0,
  

•                        &eqos->phy_reset_gpio, reset_flags);
  

•   return 0;
  

+err_free_clk_master_bus:

•   clk_free(&eqos->clk_master_bus);
  

+err_release_resets:

•   reset_release_bulk(&data->resets);
  

+err_free:

•   free(data);
  

•   return ret;
  

+}

+static int eqos_remove_resources_rk(struct udevice *dev) +{

•   struct eqos_priv *eqos = dev_get_priv(dev);
  

•   struct eth_pdata *pdata = dev_get_plat(dev);
  

•   struct rockchip_platform_data *data = pdata->priv_pdata;
  

•   if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
  

•           dm_gpio_free(dev, &eqos->phy_reset_gpio);
  

•   clk_free(&eqos->clk_tx);
  

•   clk_free(&eqos->clk_master_bus);
  

•   reset_release_bulk(&data->resets);
  

•   free(data);
  

•   return 0;
  

+}

+static int eqos_stop_resets_rk(struct udevice *dev) +{

•   struct eth_pdata *pdata = dev_get_plat(dev);
  

•   struct rockchip_platform_data *data = pdata->priv_pdata;
  

•   return reset_assert_bulk(&data->resets);
  

+}

+static int eqos_start_resets_rk(struct udevice *dev) +{

•   struct eth_pdata *pdata = dev_get_plat(dev);
  

•   struct rockchip_platform_data *data = pdata->priv_pdata;
  

•   return reset_deassert_bulk(&data->resets);
  

+}

+static int eqos_stop_clks_rk(struct udevice *dev) +{

•   return 0;
  

+}

+static int eqos_start_clks_rk(struct udevice *dev) +{

•   struct eqos_priv *eqos = dev_get_priv(dev);
  

•   struct eth_pdata *pdata = dev_get_plat(dev);
  

•   struct rockchip_platform_data *data = pdata->priv_pdata;
  

•   int tx_delay, rx_delay, ret;
  

•   if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
  

•           udelay(eqos->reset_delays[1]);
  

•           ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
  

•           if (ret < 0)
  

•                   return ret;
  

•           udelay(eqos->reset_delays[2]);
  

•   }
  

•   tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30);
  

•   rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);
  

•   switch (pdata->phy_interface) {
  

•   case PHY_INTERFACE_MODE_RGMII:
  

•           return data->ops->set_to_rgmii(dev, tx_delay, rx_delay);
  

•   case PHY_INTERFACE_MODE_RGMII_ID:
  

•           return data->ops->set_to_rgmii(dev, 0, 0);
  

•   case PHY_INTERFACE_MODE_RGMII_RXID:
  

•           return data->ops->set_to_rgmii(dev, tx_delay, 0);
  

•   case PHY_INTERFACE_MODE_RGMII_TXID:
  

•           return data->ops->set_to_rgmii(dev, 0, rx_delay);
  

•   case PHY_INTERFACE_MODE_RMII:
  

•           return data->ops->set_to_rmii(dev);
  

•   }
  

•   return -EINVAL;
  

+}

+static int eqos_set_tx_clk_speed_rk(struct udevice *dev) +{

•   struct eth_pdata *pdata = dev_get_plat(dev);
  

•   struct rockchip_platform_data *data = pdata->priv_pdata;
  

•   return data->ops->set_gmac_speed(dev);
  

+}

+static ulong eqos_get_tick_clk_rate_rk(struct udevice *dev) +{

•   struct eqos_priv *eqos = dev_get_priv(dev);
  

•   return clk_get_rate(&eqos->clk_master_bus);
  

+}

+static struct eqos_ops eqos_rockchip_ops = {

•   .eqos_inval_desc = eqos_inval_desc_generic,
  

•   .eqos_flush_desc = eqos_flush_desc_generic,
  

•   .eqos_inval_buffer = eqos_inval_buffer_generic,
  

•   .eqos_flush_buffer = eqos_flush_buffer_generic,
  

•   .eqos_probe_resources = eqos_probe_resources_rk,
  

•   .eqos_remove_resources = eqos_remove_resources_rk,
  

•   .eqos_stop_resets = eqos_stop_resets_rk,
  

•   .eqos_start_resets = eqos_start_resets_rk,
  

•   .eqos_stop_clks = eqos_stop_clks_rk,
  

•   .eqos_start_clks = eqos_start_clks_rk,
  

•   .eqos_calibrate_pads = eqos_null_ops,
  

•   .eqos_disable_calibration = eqos_null_ops,
  

•   .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_rk,
  

•   .eqos_get_enetaddr = eqos_null_ops,
  

•   .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_rk,
  

+};

+struct eqos_config eqos_rockchip_config = {

•   .reg_access_always_ok = false,
  

•   .mdio_wait = 10,
  

•   .swr_wait = 50,
  

•   .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
  

•   .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
  

•   .axi_bus_width = EQOS_AXI_WIDTH_64,
  

•   .interface = dev_read_phy_mode,
  

•   .ops = &eqos_rockchip_ops,
  

+};

2.42.0

Reviewed-by: Ramon Fried rfried.dev@gmail.com

Hi,

On Sun, Oct 01, 2023 at 07:17:20PM +0000, Jonas Karlman wrote:

Add rk_gmac_ops and other special handling that is needed for GMAC to work on RK3588.

rk_gmac_ops was ported from linux commits: 2f2b60a0ec28 ("net: ethernet: stmmac: dwmac-rk: Add gmac support for rk3588") 88619e77b33d ("net: stmmac: rk3588: Allow multiple gmac controller")

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com

---

Cc: David Wu david.wu@rock-chips.com Cc: Sebastian Reichel sebastian.reichel@collabora.com Cc: Benjamin Gaignard benjamin.gaignard@collabora.com

---

Looks like I've send my R-b to v1 while you were preparing v2. Since nothing changed this is still:

Reviewed-by: Sebastian Reichel sebastian.reichel@collabora.com

Greetings,

-- Sebastian

v2:

• Collect r-b tag

drivers/net/dwc_eth_qos.c | 4 + drivers/net/dwc_eth_qos_rockchip.c | 182 ++++++++++++++++++++++++++++- 2 files changed, 182 insertions(+), 4 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 9fb98a2c3c74..dc04416865dd 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1712,6 +1712,10 @@ static const struct udevice_id eqos_ids[] = { .compatible = "rockchip,rk3568-gmac", .data = (ulong)&eqos_rockchip_config },

• {

• .compatible = "rockchip,rk3588-gmac",
  

• .data = (ulong)&eqos_rockchip_config
  

• },

#endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM) { diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index 05edc098f50d..20fd3a25c3dd 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -28,6 +28,7 @@ struct rk_gmac_ops { int tx_delay, int rx_delay); int (*set_to_rmii)(struct udevice *dev); int (*set_gmac_speed)(struct udevice *dev);

• void (*set_clock_selection)(struct udevice *dev, bool enable); u32 regs[3];

};

@@ -35,7 +36,9 @@ struct rockchip_platform_data { struct reset_ctl_bulk resets; const struct rk_gmac_ops *ops; int id;

• bool clock_input; struct regmap *grf;
• struct regmap *php_grf;

};

#define HIWORD_UPDATE(val, mask, shift) \ @@ -129,6 +132,137 @@ static int rk3568_set_gmac_speed(struct udevice *dev) return 0; }

+/* sys_grf */ +#define RK3588_GRF_GMAC_CON7 0x031c +#define RK3588_GRF_GMAC_CON8 0x0320 +#define RK3588_GRF_GMAC_CON9 0x0324

+#define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) +#define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) +#define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) +#define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)

+#define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) +#define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)

+/* php_grf */ +#define RK3588_GRF_GMAC_CON0 0x0008 +#define RK3588_GRF_CLK_CON1 0x0070

+#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \

• (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))

+#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \

• (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))

+#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) +#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))

+#define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4) +#define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4)

+#define RK3588_GMAC_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) +#define RK3588_GMAC_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)

+#define RK3588_GMAC_CLK_RGMII_DIV1(id) \

• 	(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
  

+#define RK3588_GMAC_CLK_RGMII_DIV5(id) \

• 	(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
  

+#define RK3588_GMAC_CLK_RGMII_DIV50(id) \

• 	(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
  

+#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) +#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)

+static int rk3588_set_to_rgmii(struct udevice *dev,

• 	       int tx_delay, int rx_delay)
  

+{

• struct eth_pdata *pdata = dev_get_plat(dev);
• struct rockchip_platform_data *data = pdata->priv_pdata;
• u32 offset_con, id = data->id;
• offset_con = data->id == 1 ? RK3588_GRF_GMAC_CON9 :

• 		     RK3588_GRF_GMAC_CON8;
  

• regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,

•      RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
  

• regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,

•      RK3588_GMAC_CLK_RGMII_MODE(id));
  

• regmap_write(data->grf, RK3588_GRF_GMAC_CON7,

•      RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
  

•      RK3588_GMAC_TXCLK_DLY_ENABLE(id));
  

• regmap_write(data->grf, offset_con,

•      RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
  

•      RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
  

• return 0;

+}

+static int rk3588_set_to_rmii(struct udevice *dev) +{

• struct eth_pdata *pdata = dev_get_plat(dev);
• struct rockchip_platform_data *data = pdata->priv_pdata;
• regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,

•      RK3588_GMAC_PHY_INTF_SEL_RMII(data->id));
  

• regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,

•      RK3588_GMAC_CLK_RMII_MODE(data->id));
  

• return 0;

+}

+static int rk3588_set_gmac_speed(struct udevice *dev) +{

• struct eqos_priv *eqos = dev_get_priv(dev);
• struct eth_pdata *pdata = dev_get_plat(dev);
• struct rockchip_platform_data *data = pdata->priv_pdata;
• u32 val = 0, id = data->id;
• switch (eqos->phy->speed) {
• case SPEED_10:

• if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
  

• 	val = RK3588_GMAC_CLK_RMII_DIV20(id);
  

• else
  

• 	val = RK3588_GMAC_CLK_RGMII_DIV50(id);
  

• break;
  

• case SPEED_100:

• if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
  

• 	val = RK3588_GMAC_CLK_RMII_DIV2(id);
  

• else
  

• 	val = RK3588_GMAC_CLK_RGMII_DIV5(id);
  

• break;
  

• case SPEED_1000:

• if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
  

• 	val = RK3588_GMAC_CLK_RGMII_DIV1(id);
  

• else
  

• 	return -EINVAL;
  

• break;
  

• default:

• return -EINVAL;
  

• }
• regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
• return 0;

+}

+static void rk3588_set_clock_selection(struct udevice *dev, bool enable) +{

• struct eth_pdata *pdata = dev_get_plat(dev);
• struct rockchip_platform_data *data = pdata->priv_pdata;
• u32 val = data->clock_input ? RK3588_GMAC_CLK_SELET_IO(data->id) :

• 		      RK3588_GMAC_CLK_SELET_CRU(data->id);
  

• val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(data->id) :

• 	RK3588_GMAC_CLK_RMII_GATE(data->id);
  

• regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);

+}

static const struct rk_gmac_ops rk_gmac_ops[] = { { .compatible = "rockchip,rk3568-gmac", @@ -141,6 +275,18 @@ static const struct rk_gmac_ops rk_gmac_ops[] = { 0x0, /* sentinel */ }, },

• {

• .compatible = "rockchip,rk3588-gmac",
  

• .set_to_rgmii = rk3588_set_to_rgmii,
  

• .set_to_rmii = rk3588_set_to_rmii,
  

• .set_gmac_speed = rk3588_set_gmac_speed,
  

• .set_clock_selection = rk3588_set_clock_selection,
  

• .regs = {
  

• 	0xfe1b0000, /* gmac0 */
  

• 	0xfe1c0000, /* gmac1 */
  

• 	0x0, /* sentinel */
  

• },
  

• }, { }

};

@@ -162,6 +308,7 @@ static int eqos_probe_resources_rk(struct udevice *dev) struct eqos_priv *eqos = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); struct rockchip_platform_data *data;

• const char *clock_in_out; int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE; int ret;

@@ -199,6 +346,16 @@ static int eqos_probe_resources_rk(struct udevice *dev) goto err_free; }

• if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {

• data->php_grf =
  

• 	syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
  

• if (IS_ERR(data->php_grf)) {
  

• 	dev_err(dev, "Missing rockchip,php-grf property\n");
  

• 	ret = -EINVAL;
  

• 	goto err_free;
  

• }
  

• }
• ret = reset_get_bulk(dev, &data->resets); if (ret < 0) goto err_free;

@@ -211,12 +368,20 @@ static int eqos_probe_resources_rk(struct udevice *dev) goto err_release_resets; }

• ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
• if (ret) {

• dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
  

• goto err_free_clk_master_bus;
  

• if (device_is_compatible(dev, "rockchip,rk3568-gmac")) {

• ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
  

• if (ret) {
  

• 	dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
  

• 	goto err_free_clk_master_bus;
  

• }
  

  }

• clock_in_out = dev_read_string(dev, "clock_in_out");

• if (clock_in_out && !strcmp(clock_in_out, "input"))

• data->clock_input = true;
  

• else

• data->clock_input = false;
  

• /* snps,reset props are deprecated, do bare minimum to support them */ if (dev_read_bool(dev, "snps,reset-active-low")) reset_flags |= GPIOD_ACTIVE_LOW;

@@ -273,6 +438,12 @@ static int eqos_start_resets_rk(struct udevice *dev)

static int eqos_stop_clks_rk(struct udevice *dev) {

• struct eth_pdata *pdata = dev_get_plat(dev);
• struct rockchip_platform_data *data = pdata->priv_pdata;
• if (data->ops->set_clock_selection)

• data->ops->set_clock_selection(dev, false);
  

• return 0;

}

@@ -293,6 +464,9 @@ static int eqos_start_clks_rk(struct udevice *dev) udelay(eqos->reset_delays[2]); }

• if (data->ops->set_clock_selection)

• data->ops->set_clock_selection(dev, true);
  

• tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30); rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);

-- 2.42.0

Hi Jonas,

On 2023-10-01 21:17, Jonas Karlman wrote:

Add rk_gmac_ops and other special handling that is needed for GMAC to work on RK3588.

rk_gmac_ops was ported from linux commits: 2f2b60a0ec28 ("net: ethernet: stmmac: dwmac-rk: Add gmac support for rk3588") 88619e77b33d ("net: stmmac: rk3588: Allow multiple gmac controller")

I've updated from U-Boot 2023.07.2 to 2024.01, and noticed Ethernet issue on Linux. On a ODROID-M1 with 8GB of RAM I had a packet drop rate of ~20%:

107 packets transmitted, 87 received, 18.6916% packet loss, time 107390ms rtt min/avg/max/mdev = 0.337/0.405/0.889/0.076 ms

SSH connections feel very sluggy, presumably due to packet losses.

Strangely, the same build works just fine on another ODROID-M1 with 4GB of RAM. I swapped Ethernet cable and switches to rule this out. It really seems to bee that particular unit which is problematic.

Disabling this driver fixes the Etherent issue on Linux.

Do you have an idea what this could be? I am happy to run commands or test patches to debug this.

-- Stefan

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com

---

Cc: David Wu david.wu@rock-chips.com Cc: Sebastian Reichel sebastian.reichel@collabora.com Cc: Benjamin Gaignard benjamin.gaignard@collabora.com

---

v2:

• Collect r-b tag

drivers/net/dwc_eth_qos.c | 4 + drivers/net/dwc_eth_qos_rockchip.c | 182 ++++++++++++++++++++++++++++- 2 files changed, 182 insertions(+), 4 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 9fb98a2c3c74..dc04416865dd 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1712,6 +1712,10 @@ static const struct udevice_id eqos_ids[] = { .compatible = "rockchip,rk3568-gmac", .data = (ulong)&eqos_rockchip_config },

• {

• .compatible = "rockchip,rk3588-gmac",
  

• .data = (ulong)&eqos_rockchip_config
  

• },

#endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM) { diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index 05edc098f50d..20fd3a25c3dd 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -28,6 +28,7 @@ struct rk_gmac_ops { int tx_delay, int rx_delay); int (*set_to_rmii)(struct udevice *dev); int (*set_gmac_speed)(struct udevice *dev);

• void (*set_clock_selection)(struct udevice *dev, bool enable); u32 regs[3];

};

@@ -35,7 +36,9 @@ struct rockchip_platform_data { struct reset_ctl_bulk resets; const struct rk_gmac_ops *ops; int id;

• bool clock_input; struct regmap *grf;
• struct regmap *php_grf;

};

#define HIWORD_UPDATE(val, mask, shift) \ @@ -129,6 +132,137 @@ static int rk3568_set_gmac_speed(struct udevice *dev) return 0; }

+/* sys_grf */ +#define RK3588_GRF_GMAC_CON7 0x031c +#define RK3588_GRF_GMAC_CON8 0x0320 +#define RK3588_GRF_GMAC_CON9 0x0324

+#define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) +#define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) +#define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) +#define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)

+#define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) +#define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)

+/* php_grf */ +#define RK3588_GRF_GMAC_CON0 0x0008 +#define RK3588_GRF_CLK_CON1 0x0070

+#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \

• (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 +

(id) * 6)) +#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \

• (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 +

(id) * 6))

+#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) +#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))

+#define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4) +#define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4)

+#define RK3588_GMAC_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) +#define RK3588_GMAC_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)

+#define RK3588_GMAC_CLK_RGMII_DIV1(id) \

• 	(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
  

+#define RK3588_GMAC_CLK_RGMII_DIV5(id) \

• 	(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
  

+#define RK3588_GMAC_CLK_RGMII_DIV50(id) \

• 	(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
  

+#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) +#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)

+static int rk3588_set_to_rgmii(struct udevice *dev,

• 	       int tx_delay, int rx_delay)
  

+{

• struct eth_pdata *pdata = dev_get_plat(dev);
• struct rockchip_platform_data *data = pdata->priv_pdata;
• u32 offset_con, id = data->id;
• offset_con = data->id == 1 ? RK3588_GRF_GMAC_CON9 :

• 		     RK3588_GRF_GMAC_CON8;
  

• regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,

•      RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
  

• regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,

•      RK3588_GMAC_CLK_RGMII_MODE(id));
  

• regmap_write(data->grf, RK3588_GRF_GMAC_CON7,

•      RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
  

•      RK3588_GMAC_TXCLK_DLY_ENABLE(id));
  

• regmap_write(data->grf, offset_con,

•      RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
  

•      RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
  

• return 0;

+}

+static int rk3588_set_to_rmii(struct udevice *dev) +{

• struct eth_pdata *pdata = dev_get_plat(dev);
• struct rockchip_platform_data *data = pdata->priv_pdata;
• regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,

•      RK3588_GMAC_PHY_INTF_SEL_RMII(data->id));
  

• regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,

•      RK3588_GMAC_CLK_RMII_MODE(data->id));
  

• return 0;

+}

+static int rk3588_set_gmac_speed(struct udevice *dev) +{

• struct eqos_priv *eqos = dev_get_priv(dev);
• struct eth_pdata *pdata = dev_get_plat(dev);
• struct rockchip_platform_data *data = pdata->priv_pdata;
• u32 val = 0, id = data->id;
• switch (eqos->phy->speed) {
• case SPEED_10:

• if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
  

• 	val = RK3588_GMAC_CLK_RMII_DIV20(id);
  

• else
  

• 	val = RK3588_GMAC_CLK_RGMII_DIV50(id);
  

• break;
  

• case SPEED_100:

• if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
  

• 	val = RK3588_GMAC_CLK_RMII_DIV2(id);
  

• else
  

• 	val = RK3588_GMAC_CLK_RGMII_DIV5(id);
  

• break;
  

• case SPEED_1000:

• if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
  

• 	val = RK3588_GMAC_CLK_RGMII_DIV1(id);
  

• else
  

• 	return -EINVAL;
  

• break;
  

• default:

• return -EINVAL;
  

• }
• regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
• return 0;

+}

+static void rk3588_set_clock_selection(struct udevice *dev, bool enable) +{

• struct eth_pdata *pdata = dev_get_plat(dev);
• struct rockchip_platform_data *data = pdata->priv_pdata;
• u32 val = data->clock_input ? RK3588_GMAC_CLK_SELET_IO(data->id) :

• 		      RK3588_GMAC_CLK_SELET_CRU(data->id);
  

• val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(data->id) :

• 	RK3588_GMAC_CLK_RMII_GATE(data->id);
  

• regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);

+}

static const struct rk_gmac_ops rk_gmac_ops[] = { { .compatible = "rockchip,rk3568-gmac", @@ -141,6 +275,18 @@ static const struct rk_gmac_ops rk_gmac_ops[] = { 0x0, /* sentinel */ }, },

• {

• .compatible = "rockchip,rk3588-gmac",
  

• .set_to_rgmii = rk3588_set_to_rgmii,
  

• .set_to_rmii = rk3588_set_to_rmii,
  

• .set_gmac_speed = rk3588_set_gmac_speed,
  

• .set_clock_selection = rk3588_set_clock_selection,
  

• .regs = {
  

• 	0xfe1b0000, /* gmac0 */
  

• 	0xfe1c0000, /* gmac1 */
  

• 	0x0, /* sentinel */
  

• },
  

• }, { }

};

@@ -162,6 +308,7 @@ static int eqos_probe_resources_rk(struct udevice *dev) struct eqos_priv *eqos = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); struct rockchip_platform_data *data;

• const char *clock_in_out; int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE; int ret;

@@ -199,6 +346,16 @@ static int eqos_probe_resources_rk(struct udevice *dev) goto err_free; }

• if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {

• data->php_grf =
  

• 	syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
  

• if (IS_ERR(data->php_grf)) {
  

• 	dev_err(dev, "Missing rockchip,php-grf property\n");
  

• 	ret = -EINVAL;
  

• 	goto err_free;
  

• }
  

• }
• ret = reset_get_bulk(dev, &data->resets); if (ret < 0) goto err_free;

@@ -211,12 +368,20 @@ static int eqos_probe_resources_rk(struct udevice *dev) goto err_release_resets; }

• ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
• if (ret) {

• dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
  

• goto err_free_clk_master_bus;
  

• if (device_is_compatible(dev, "rockchip,rk3568-gmac")) {

• ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
  

• if (ret) {
  

• 	dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
  

• 	goto err_free_clk_master_bus;
  

• }
  

  }

• clock_in_out = dev_read_string(dev, "clock_in_out");

• if (clock_in_out && !strcmp(clock_in_out, "input"))

• data->clock_input = true;
  

• else

• data->clock_input = false;
  

• /* snps,reset props are deprecated, do bare minimum to support them */ if (dev_read_bool(dev, "snps,reset-active-low")) reset_flags |= GPIOD_ACTIVE_LOW;

@@ -273,6 +438,12 @@ static int eqos_start_resets_rk(struct udevice *dev)

static int eqos_stop_clks_rk(struct udevice *dev) {

• struct eth_pdata *pdata = dev_get_plat(dev);
• struct rockchip_platform_data *data = pdata->priv_pdata;
• if (data->ops->set_clock_selection)

• data->ops->set_clock_selection(dev, false);
  

• return 0;

}

@@ -293,6 +464,9 @@ static int eqos_start_clks_rk(struct udevice *dev) udelay(eqos->reset_delays[2]); }

• if (data->ops->set_clock_selection)

• data->ops->set_clock_selection(dev, true);
  

• tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30); rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);

Hi,

On Sunday, 1 October 2023 21:17:21 CEST Jonas Karlman wrote:

Enable DWC_ETH_QOS_ROCKCHIP and related PHY driver on RK356x boards that have an enabled gmac node.

Signed-off-by: Jonas Karlman jonas@kwiboo.se Reviewed-by: Kever Yang kever.yang@rock-chips.com

---

... configs/odroid-m1-rk3568_defconfig | 3 +++ configs/quartz64-a-rk3566_defconfig | 3 +++ configs/quartz64-b-rk3566_defconfig | 3 +++ ... configs/soquartz-blade-rk3566_defconfig | 3 +++ configs/soquartz-cm4-rk3566_defconfig | 3 +++ configs/soquartz-model-a-rk3566_defconfig | 3 +++ 11 files changed, 35 insertions(+), 6 deletions(-) ... diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig index 3dda5c1f9170..96b4e9ecdaff 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -82,6 +82,9 @@ CONFIG_SF_DEFAULT_BUS=4 CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig index 6853cd6c44b4..bf4d4cd2b8ed 100644 --- a/configs/quartz64-a-rk3566_defconfig +++ b/configs/quartz64-a-rk3566_defconfig @@ -81,6 +81,9 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig index aa29fff14643..358687ab5d7f 100644 --- a/configs/quartz64-b-rk3566_defconfig +++ b/configs/quartz64-b-rk3566_defconfig @@ -79,6 +79,9 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y

Some time ago I reported to Jonas privately that I had a problem with my Quartz64 Model A and B and that I bisected it to this commit. I just verified that the problem is still present in 2024.07, so I guess it's time to report it to the (right) Mailing List.

The problem: packet loss, varying, but sometimes massive Q64-A: The packet loss was usually between 8% and 30% Q64-B: Packet loss up to 80% sometimes and this also resulted (then) in its inability to receive a DHCP address.

https://lore.kernel.org/linux-rockchip/27139798.WhXITi6ROJ@bagend/ is where I brought this issue (also) up publicly, but that was on the linux-rockchip ML. The discussion that followed may provide some clues.

When looking up the mail I'm now replying too, I noticed a reply by Stefan Agner with very similar symptoms, but on Odroid M1.

And the fix in my case has always been easy:

diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig index 1ea8e0f40cc..641452f9162 100644 --- a/configs/quartz64-a-rk3566_defconfig +++ b/configs/quartz64-a-rk3566_defconfig @@ -67,9 +67,6 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_MOTORCOMM=y -CONFIG_DWC_ETH_QOS=y -CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig index f61b2c181a1..aae5d66edeb 100644 --- a/configs/quartz64-b-rk3566_defconfig +++ b/configs/quartz64-b-rk3566_defconfig @@ -65,9 +65,6 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_REALTEK=y -CONFIG_DWC_ETH_QOS=y -CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y

IOW: a (partial) revert of commit 25f56459aebc

It _could_ be that the issue is also present on the various SOQuartz devices/boards, but I don't have those, so I can't check that. But AFAIK they are rather similar to Q64-A and the change has also been the same ... as was the case for Odroid-M1.

In case it's useful I have a log from the serial session with the Q64-A (212.5 KiB) available. Serial on Q64-B doesn't work, so I don't have that.

Cheers, Diederik