[PATCH v2 00/13] armv8: layerscape: spin table relocation fixes and cleanups
Fix bootefi on layerscape boards which use spin table for secondary cores bringup. There two main issues here: (1) bootefi doesn't kick the secondary cores (2) bootefi reserves a 64kb region for runtime services code on ARM64 which overlaps the spin table code.
We will fix (1) by removing the need to kick the secondary cores. For (2), we will make the spin table code relocatable and if the efi_loader support is enabled we will dynamically allocate a page for the spin table code and relocate it there. While we are at it, clean up the whole spin table code for layerscape.
Please note, no current board in u-boot should be using spin tables, because NXP officially only supports TF-A, which uses PSCI for secondary cores booting. Only the pending Kontron SMARC-sAL28 board will be using this method. U-Boot support is still pending, see: https://patchwork.ozlabs.org/project/uboot/list/?series=175926
This was tested on said board, both with CONFIG_ARMV8_SWITCH_TO_EL1 defined and undefined.
Michael Walle (13): armv8: layerscape: fix spin-table support armv8: layerscape: pretty print info about SMP cores armv8: layerscape: properly use CPU_RELEASE_ADDR armv8: layerscape: move spin table into own module armv8: layerscape: load function pointer using ADR armv8: layerscape: fix alignment for spin table armv8: layerscape: remove determine_mp_bootpg() armv8: layerscape: simplify get_spin_tbl_addr() calls armv8: layerscape: make wake_secondary_core_n() static armv8: freescale: drop first .ltorg directive in spintable.S armv8: layerscape: clean exported symbols in spintable.S armv8: layerscape: relocate spin table if EFI_LOADER is enabled armv8: layerscape: rework spin table
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 2 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 9 +- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 165 ++---------------- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 79 ++++++--- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 118 +++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/mp.h | 8 +- include/configs/kontron_sl28.h | 2 +- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 2 +- 13 files changed, 201 insertions(+), 194 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/spintable.S
Spin tables are broken with bootefi. This is because - in contrast to the booti call chain - there is no call to smp_kick_all_cpus(). Due to this missing call the secondary CPUs are never released from their "wait for interrupt state", see secondary_boot_func() in lowlevel.S.
Originally, this "wait for interrupt" is there to make sure, the spin table is cleared before the secondary cores read it for the first time. But the boot flow for the layerscape architecture is different from that. The CPUs are release from their BootROM _after_ U-Boot's spin-table is cleared, see fsl_layerscape_wake_seconday_cores() in mp.c. Thus, there is no need to wait for this interrupt and no need for kicking all cores on cpu_release. An atomic 64bit write to the spin-table and a "sev" is sufficient.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 7 ------- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 9 +++++---- 2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 711ab87556..2a8d592cc5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -474,13 +474,6 @@ ENTRY(secondary_boot_func) mov x4, #1 str x4, [x11, #8] /* STATUS */ dsb sy -#if defined(CONFIG_GICV3) - gic_wait_for_interrupt_m x0 -#elif defined(CONFIG_GICV2) - bl get_gic_offset - mov x0, x1 - gic_wait_for_interrupt_m x0, w1 -#endif
slave_cpu: wfe diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 1ea887b331..e078d1cd37 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -277,11 +277,12 @@ int cpu_release(u32 nr, int argc, char *const argv[]) flush_dcache_range((unsigned long)table, (unsigned long)table + SPIN_TABLE_ELEM_SIZE); asm volatile("dsb st"); - smp_kick_all_cpus(); /* only those with entry addr set will run */ + /* - * When the first release command runs, all cores are set to go. Those - * without a valid entry address will be trapped by "wfe". "sev" kicks - * them off to check the address again. When set, they continue to run. + * The secondary CPUs polling the spin-table above for a non-zero + * value. To save power "wfe" is called. Thus call "sev" here to + * wake the CPUs and let them check the spin-table again (see + * slave_cpu loop in lowlevel.S) */ asm volatile("sev");
Make the print of the starting address a debug output and pretty print the info about online cores.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index e078d1cd37..b5916ff3f3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -6,6 +6,7 @@ #include <common.h> #include <cpu_func.h> #include <image.h> +#include <log.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/system.h> @@ -98,7 +99,7 @@ int fsl_layerscape_wake_seconday_cores(void) (unsigned long)table + (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
- printf("Waking secondary cores to start from %lx\n", gd->relocaddr); + debug("Waking secondary cores to start from %lx\n", gd->relocaddr);
#ifdef CONFIG_FSL_LSCH3 gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); @@ -168,11 +169,11 @@ int fsl_layerscape_wake_seconday_cores(void) udelay(10); } if (timeout <= 0) { - printf("Not all cores (0x%x) are up (0x%x)\n", - cores, cpu_up_mask); + printf("CPU: Failed to bring up some cores (mask 0x%x)\n", + cores ^ cpu_up_mask); return 1; } - printf("All (%d) cores are up.\n", hweight32(cores)); + printf("CPU: %d cores online\n", hweight32(cores));
return 0; }
The generic armv8 code already has support to bring up the secondary cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to the spin table code; instead just return early and let the common armv8 code handle the jump. This way we can actually use the CPU_RELEASE_ADDR feature.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 14 ++++++++++++-- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 1 - include/configs/kontron_sl28.h | 2 +- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 2 +- 9 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 2a8d592cc5..d75013eb9c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -208,8 +208,13 @@ ENTRY(lowlevel_init) branch_if_master x0, x1, 2f
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY) - ldr x0, =secondary_boot_func - blr x0 + /* + * Formerly, here was a jump to secondary_boot_func, but we just + * return early here and let the generic code in start.S handle + * the jump to secondary_boot_func. + */ + mov lr, x29 /* Restore LR */ + ret #endif
2: @@ -421,6 +426,11 @@ ENDPROC(__asm_flush_l3_dcache) #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP + .align 3 + .global secondary_boot_addr +secondary_boot_addr: + .quad secondary_boot_func + /* Keep literals not used by the secondary boot code outside it */ .ltorg
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index 00aa91b0a2..623977651a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -43,7 +43,6 @@ static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } #endif void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); -void secondary_boot_func(void); int is_core_online(u64 cpu_id); u32 cpu_pos_mask(void); #endif diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 70546d6f15..f97671bba1 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -32,7 +32,7 @@ #define CONFIG_SYS_MEMTEST_END 0x9fffffff
/* SMP */ -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr
/* generic timer */ #define COUNTER_FREQUENCY 25000000 diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 33d9687eeb..540959d737 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -28,7 +28,7 @@ /* * SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 985f40412c..1c4bd5c68d 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -47,7 +47,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
-#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 24db23b3c3..176633da33 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -48,7 +48,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
-#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index a7373429ba..a9ca354851 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -48,7 +48,7 @@ /* * SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr
#ifdef CONFIG_PCI #define CONFIG_CMD_PCI diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index b58776a788..7a192f4807 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -42,7 +42,7 @@ /* * SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr
#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS #ifdef CONFIG_SYS_FSL_HAS_DP_DDR diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 5ab924457e..a96f8b993c 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -53,7 +53,7 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
/* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */ /*
Move it out of lowlevel.S into spintable.S. On layerscape, the secondary CPUs are brought up in main u-boot. This will make it possible to only compile the spin table code for the main u-boot and omit it in SPL.
This saves about 720 bytes in the SPL.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 2 +- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 154 +---------------- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 155 ++++++++++++++++++ 3 files changed, 161 insertions(+), 150 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/spintable.S
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index e398aecd12..9ecb372b4e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -6,7 +6,7 @@ obj-y += cpu.o obj-y += lowlevel.o obj-y += soc.o ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_MP) += mp.o spintable.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index d75013eb9c..a519f6ed67 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -11,14 +11,16 @@ #include <asm/gic.h> #include <asm/macro.h> #include <asm/arch-fsl-layerscape/soc.h> -#ifdef CONFIG_MP -#include <asm/arch/mp.h> -#endif #ifdef CONFIG_FSL_LSCH3 #include <asm/arch-fsl-layerscape/immap_lsch3.h> #endif #include <asm/u-boot.h>
+ .align 3 + .weak secondary_boot_addr +secondary_boot_addr: + .quad 0 + /* Get GIC offset * For LS1043a rev1.0, GIC base address align with 4k. * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT] @@ -424,149 +426,3 @@ ENTRY(__asm_flush_l3_dcache) ret ENDPROC(__asm_flush_l3_dcache) #endif /* CONFIG_SYS_FSL_HAS_CCN504 */ - -#ifdef CONFIG_MP - .align 3 - .global secondary_boot_addr -secondary_boot_addr: - .quad secondary_boot_func - - /* Keep literals not used by the secondary boot code outside it */ - .ltorg - - /* Using 64 bit alignment since the spin table is accessed as data */ - .align 4 - .global secondary_boot_code - /* Secondary Boot Code starts here */ -secondary_boot_code: - .global __spin_table -__spin_table: - .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE - - .align 2 -ENTRY(secondary_boot_func) - /* - * MPIDR_EL1 Fields: - * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) - * MPIDR[7:2] = AFF0_RES - * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3) - * MPIDR[23:16] = AFF2_CLUSTERID - * MPIDR[24] = MT - * MPIDR[29:25] = RES0 - * MPIDR[30] = U - * MPIDR[31] = ME - * MPIDR[39:32] = AFF3 - * - * Linear Processor ID (LPID) calculation from MPIDR_EL1: - * (We only use AFF0_CPUID and AFF1_CLUSTERID for now - * until AFF2_CLUSTERID and AFF3 have non-zero values) - * - * LPID = MPIDR[15:8] | MPIDR[1:0] - */ - mrs x0, mpidr_el1 - ubfm x1, x0, #8, #15 - ubfm x2, x0, #0, #1 - orr x10, x2, x1, lsl #2 /* x10 has LPID */ - ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */ - /* - * offset of the spin table element for this core from start of spin - * table (each elem is padded to 64 bytes) - */ - lsl x1, x10, #6 - ldr x0, =__spin_table - /* physical address of this cpus spin table element */ - add x11, x1, x0 - - ldr x0, =__real_cntfrq - ldr x0, [x0] - msr cntfrq_el0, x0 /* set with real frequency */ - str x9, [x11, #16] /* LPID */ - mov x4, #1 - str x4, [x11, #8] /* STATUS */ - dsb sy - -slave_cpu: - wfe - ldr x0, [x11] - cbz x0, slave_cpu -#ifndef CONFIG_ARMV8_SWITCH_TO_EL1 - mrs x1, sctlr_el2 -#else - mrs x1, sctlr_el1 -#endif - tbz x1, #25, cpu_is_le - rev x0, x0 /* BE to LE conversion */ -cpu_is_le: - ldr x5, [x11, #24] - cbz x5, 1f - -#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x4, secondary_switch_to_el1 - ldr x5, =ES_TO_AARCH64 -#else - ldr x4, [x11] - ldr x5, =ES_TO_AARCH32 -#endif - bl secondary_switch_to_el2 - -1: -#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x4, secondary_switch_to_el1 -#else - ldr x4, [x11] -#endif - ldr x5, =ES_TO_AARCH64 - bl secondary_switch_to_el2 - -ENDPROC(secondary_boot_func) - -ENTRY(secondary_switch_to_el2) - switch_el x6, 1f, 0f, 0f -0: ret -1: armv8_switch_to_el2_m x4, x5, x6 -ENDPROC(secondary_switch_to_el2) - -ENTRY(secondary_switch_to_el1) - mrs x0, mpidr_el1 - ubfm x1, x0, #8, #15 - ubfm x2, x0, #0, #1 - orr x10, x2, x1, lsl #2 /* x10 has LPID */ - - lsl x1, x10, #6 - ldr x0, =__spin_table - /* physical address of this cpus spin table element */ - add x11, x1, x0 - - ldr x4, [x11] - - ldr x5, [x11, #24] - cbz x5, 2f - - ldr x5, =ES_TO_AARCH32 - bl switch_to_el1 - -2: ldr x5, =ES_TO_AARCH64 - -switch_to_el1: - switch_el x6, 0f, 1f, 0f -0: ret -1: armv8_switch_to_el1_m x4, x5, x6 -ENDPROC(secondary_switch_to_el1) - - /* Ensure that the literals used by the secondary boot code are - * assembled within it (this is required so that we can protect - * this area with a single memreserve region - */ - .ltorg - - /* 64 bit alignment for elements accessed as data */ - .align 4 - .global __real_cntfrq -__real_cntfrq: - .quad COUNTER_FREQUENCY - .globl __secondary_boot_code_size - .type __secondary_boot_code_size, %object - /* Secondary Boot Code ends here */ -__secondary_boot_code_size: - .quad .-secondary_boot_code -#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S new file mode 100644 index 0000000000..d71ec13eaf --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014-2015 Freescale Semiconductor + * Copyright 2019 NXP + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> +#include <asm/system.h> +#include <asm/arch/mp.h> + + .align 3 + .global secondary_boot_addr +secondary_boot_addr: + .quad secondary_boot_func + + /* Keep literals not used by the secondary boot code outside it */ + .ltorg + + /* Using 64 bit alignment since the spin table is accessed as data */ + .align 4 + .global secondary_boot_code + /* Secondary Boot Code starts here */ +secondary_boot_code: + .global __spin_table +__spin_table: + .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE + + .align 2 +ENTRY(secondary_boot_func) + /* + * MPIDR_EL1 Fields: + * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) + * MPIDR[7:2] = AFF0_RES + * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3) + * MPIDR[23:16] = AFF2_CLUSTERID + * MPIDR[24] = MT + * MPIDR[29:25] = RES0 + * MPIDR[30] = U + * MPIDR[31] = ME + * MPIDR[39:32] = AFF3 + * + * Linear Processor ID (LPID) calculation from MPIDR_EL1: + * (We only use AFF0_CPUID and AFF1_CLUSTERID for now + * until AFF2_CLUSTERID and AFF3 have non-zero values) + * + * LPID = MPIDR[15:8] | MPIDR[1:0] + */ + mrs x0, mpidr_el1 + ubfm x1, x0, #8, #15 + ubfm x2, x0, #0, #1 + orr x10, x2, x1, lsl #2 /* x10 has LPID */ + ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */ + /* + * offset of the spin table element for this core from start of spin + * table (each elem is padded to 64 bytes) + */ + lsl x1, x10, #6 + ldr x0, =__spin_table + /* physical address of this cpus spin table element */ + add x11, x1, x0 + + ldr x0, =__real_cntfrq + ldr x0, [x0] + msr cntfrq_el0, x0 /* set with real frequency */ + str x9, [x11, #16] /* LPID */ + mov x4, #1 + str x4, [x11, #8] /* STATUS */ + dsb sy + +slave_cpu: + wfe + ldr x0, [x11] + cbz x0, slave_cpu +#ifndef CONFIG_ARMV8_SWITCH_TO_EL1 + mrs x1, sctlr_el2 +#else + mrs x1, sctlr_el1 +#endif + tbz x1, #25, cpu_is_le + rev x0, x0 /* BE to LE conversion */ +cpu_is_le: + ldr x5, [x11, #24] + cbz x5, 1f + +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x4, secondary_switch_to_el1 + ldr x5, =ES_TO_AARCH64 +#else + ldr x4, [x11] + ldr x5, =ES_TO_AARCH32 +#endif + bl secondary_switch_to_el2 + +1: +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x4, secondary_switch_to_el1 +#else + ldr x4, [x11] +#endif + ldr x5, =ES_TO_AARCH64 + bl secondary_switch_to_el2 + +ENDPROC(secondary_boot_func) + +ENTRY(secondary_switch_to_el2) + switch_el x6, 1f, 0f, 0f +0: ret +1: armv8_switch_to_el2_m x4, x5, x6 +ENDPROC(secondary_switch_to_el2) + +ENTRY(secondary_switch_to_el1) + mrs x0, mpidr_el1 + ubfm x1, x0, #8, #15 + ubfm x2, x0, #0, #1 + orr x10, x2, x1, lsl #2 /* x10 has LPID */ + + lsl x1, x10, #6 + ldr x0, =__spin_table + /* physical address of this cpus spin table element */ + add x11, x1, x0 + + ldr x4, [x11] + + ldr x5, [x11, #24] + cbz x5, 2f + + ldr x5, =ES_TO_AARCH32 + bl switch_to_el1 + +2: ldr x5, =ES_TO_AARCH64 + +switch_to_el1: + switch_el x6, 0f, 1f, 0f +0: ret +1: armv8_switch_to_el1_m x4, x5, x6 +ENDPROC(secondary_switch_to_el1) + + /* Ensure that the literals used by the secondary boot code are + * assembled within it (this is required so that we can protect + * this area with a single memreserve region + */ + .ltorg + + /* 64 bit alignment for elements accessed as data */ + .align 4 + .global __real_cntfrq +__real_cntfrq: + .quad COUNTER_FREQUENCY + .globl __secondary_boot_code_size + .type __secondary_boot_code_size, %object + /* Secondary Boot Code ends here */ +__secondary_boot_code_size: + .quad .-secondary_boot_code
Don't use LDR to load a pointer to a function. This will generate a literal which cannot be relocated. Use ADR which is PC-relative and therefore can easily be relocated.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index d71ec13eaf..ac9c622aee 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -57,11 +57,11 @@ ENTRY(secondary_boot_func) * table (each elem is padded to 64 bytes) */ lsl x1, x10, #6 - ldr x0, =__spin_table + adr x0, __spin_table /* physical address of this cpus spin table element */ add x11, x1, x0
- ldr x0, =__real_cntfrq + adr x0, __real_cntfrq ldr x0, [x0] msr cntfrq_el0, x0 /* set with real frequency */ str x9, [x11, #16] /* LPID */ @@ -117,7 +117,7 @@ ENTRY(secondary_switch_to_el1) orr x10, x2, x1, lsl #2 /* x10 has LPID */
lsl x1, x10, #6 - ldr x0, =__spin_table + adr x0, __spin_table /* physical address of this cpus spin table element */ add x11, x1, x0
Fix the alignment so it will match the comments. The spin table has to be 8 byte aligned, so ".align 3" is enough.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index ac9c622aee..a92f930e04 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -19,7 +19,7 @@ secondary_boot_addr: .ltorg
/* Using 64 bit alignment since the spin table is accessed as data */ - .align 4 + .align 3 .global secondary_boot_code /* Secondary Boot Code starts here */ secondary_boot_code: @@ -144,7 +144,7 @@ ENDPROC(secondary_switch_to_el1) .ltorg
/* 64 bit alignment for elements accessed as data */ - .align 4 + .align 3 .global __real_cntfrq __real_cntfrq: .quad COUNTER_FREQUENCY
Only the PowerPC architecture needs this function. Remove it.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 5 ----- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 1 - 2 files changed, 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index b5916ff3f3..d57b2898d4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -23,11 +23,6 @@ void *get_spin_tbl_addr(void) return &__spin_table; }
-phys_addr_t determine_mp_bootpg(void) -{ - return (phys_addr_t)&secondary_boot_code; -} - void update_os_arch_secondary_cores(uint8_t os_arch) { u64 *table = get_spin_tbl_addr(); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index 623977651a..3b470439bd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -42,7 +42,6 @@ int fsl_layerscape_wake_seconday_cores(void); static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } #endif void *get_spin_tbl_addr(void); -phys_addr_t determine_mp_bootpg(void); int is_core_online(u64 cpu_id); u32 cpu_pos_mask(void); #endif
There is no need to cast around. Assign the address to the local variable and use it.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index d57b2898d4..c4692dcd85 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -76,7 +76,7 @@ int fsl_layerscape_wake_seconday_cores(void) #endif u32 cores, cpu_up_mask = 1; int i, timeout = 10; - u64 *table = get_spin_tbl_addr(); + u64 *table;
#ifdef COUNTER_FREQUENCY_REAL /* update for secondary cores */ @@ -89,6 +89,7 @@ int fsl_layerscape_wake_seconday_cores(void) /* Clear spin table so that secondary processors * observe the correct value after waking up from wfe. */ + table = get_spin_tbl_addr(); memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); flush_dcache_range((unsigned long)table, (unsigned long)table + @@ -185,9 +186,9 @@ static int is_pos_valid(unsigned int pos)
int is_core_online(u64 cpu_id) { - u64 *table; + u64 *table = get_spin_tbl_addr(); int pos = id_to_core(cpu_id); - table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY; + table += pos * WORDS_PER_SPIN_TABLE_ENTRY; return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; }
@@ -233,18 +234,16 @@ static int core_to_pos(int nr)
int cpu_status(u32 nr) { - u64 *table; + u64 *table = get_spin_tbl_addr(); int pos;
if (nr == 0) { - table = (u64 *)get_spin_tbl_addr(); printf("table base @ 0x%p\n", table); } else { pos = core_to_pos(nr); if (pos < 0) return -1; - table = (u64 *)get_spin_tbl_addr() + pos * - WORDS_PER_SPIN_TABLE_ENTRY; + table += pos * WORDS_PER_SPIN_TABLE_ENTRY; printf("table @ 0x%p\n", table); printf(" addr - 0x%016llx\n", table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]); @@ -260,7 +259,7 @@ int cpu_status(u32 nr) int cpu_release(u32 nr, int argc, char *const argv[]) { u64 boot_addr; - u64 *table = (u64 *)get_spin_tbl_addr(); + u64 *table = get_spin_tbl_addr(); int pos;
pos = core_to_pos(nr);
This function is not used outside the module. Make it static.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index c4692dcd85..753215add0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -39,7 +39,7 @@ void update_os_arch_secondary_cores(uint8_t os_arch) }
#ifdef CONFIG_FSL_LSCH3 -void wake_secondary_core_n(int cluster, int core, int cluster_cores) +static void wake_secondary_core_n(int cluster, int core, int cluster_cores) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
Now that the spin table is in a separate module, this is no longer necessary. Drop it.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index a92f930e04..0e38cd009b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -15,8 +15,6 @@ secondary_boot_addr: .quad secondary_boot_func
- /* Keep literals not used by the secondary boot code outside it */ - .ltorg
/* Using 64 bit alignment since the spin table is accessed as data */ .align 3
Add a new variable secondary_boot_code_start, which holds a pointer to the start of the spin table code. This will help to relocate the code section. While at it, move the size variable from the end to the beginning so there is a common section for the variables. Remove any other symbols.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 9 +++---- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 4 ++- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 26 ++++++++++--------- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 ++--- 4 files changed, 24 insertions(+), 21 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 9c7546028a..9c1e0c76f3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -54,7 +54,6 @@ void ft_fixup_cpu(void *blob) fdt32_t *reg; int addr_cells; u64 val, core_id; - size_t *boot_code_size = &(__secondary_boot_code_size); u32 mask = cpu_pos_mask(); int off_prev = -1;
@@ -145,11 +144,11 @@ remove_psci_node: "cpu", 4); }
- fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code, - *boot_code_size); + fdt_add_mem_rsv(blob, (uintptr_t)secondary_boot_code_start, + secondary_boot_code_size); #if CONFIG_IS_ENABLED(EFI_LOADER) - efi_add_memory_map((uintptr_t)&secondary_boot_code, *boot_code_size, - EFI_RESERVED_MEMORY_TYPE); + efi_add_memory_map((uintptr_t)secondary_boot_code_start, + secondary_boot_code_size, EFI_RESERVED_MEMORY_TYPE); #endif } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 753215add0..d50c5a437b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -15,12 +15,14 @@ #include <linux/delay.h> #include "cpu.h" #include <asm/arch-fsl-layerscape/soc.h> +#include <efi_loader.h>
DECLARE_GLOBAL_DATA_PTR;
void *get_spin_tbl_addr(void) { - return &__spin_table; + /* the spin table is at the beginning */ + return secondary_boot_code_start; }
void update_os_arch_secondary_cores(uint8_t os_arch) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index 0e38cd009b..f082e10231 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -10,23 +10,28 @@ #include <asm/system.h> #include <asm/arch/mp.h>
- .align 3 - .global secondary_boot_addr +.align 3 +.global secondary_boot_addr secondary_boot_addr: - .quad secondary_boot_func + .quad __secondary_boot_func + +.global secondary_boot_code_start +secondary_boot_code_start: + .quad __secondary_boot_code_start
+.global secondary_boot_code_size +secondary_boot_code_size: + .quad __secondary_boot_code_end - __secondary_boot_code_start
/* Using 64 bit alignment since the spin table is accessed as data */ .align 3 - .global secondary_boot_code /* Secondary Boot Code starts here */ -secondary_boot_code: - .global __spin_table +__secondary_boot_code_start: __spin_table: .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
.align 2 -ENTRY(secondary_boot_func) +ENTRY(__secondary_boot_func) /* * MPIDR_EL1 Fields: * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) @@ -100,7 +105,7 @@ cpu_is_le: ldr x5, =ES_TO_AARCH64 bl secondary_switch_to_el2
-ENDPROC(secondary_boot_func) +ENDPROC(__secondary_boot_func)
ENTRY(secondary_switch_to_el2) switch_el x6, 1f, 0f, 0f @@ -146,8 +151,5 @@ ENDPROC(secondary_switch_to_el1) .global __real_cntfrq __real_cntfrq: .quad COUNTER_FREQUENCY - .globl __secondary_boot_code_size - .type __secondary_boot_code_size, %object /* Secondary Boot Code ends here */ -__secondary_boot_code_size: - .quad .-secondary_boot_code +__secondary_boot_code_end: diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index 3b470439bd..faac8f1128 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -32,10 +32,10 @@
#define id_to_core(x) ((x & 3) | (x >> 6)) #ifndef __ASSEMBLY__ -extern u64 __spin_table[]; extern u64 __real_cntfrq; -extern u64 *secondary_boot_code; -extern size_t __secondary_boot_code_size; +extern void *secondary_boot_addr; +extern void *secondary_boot_code_start; +extern size_t secondary_boot_code_size; #ifdef CONFIG_MP int fsl_layerscape_wake_seconday_cores(void); #else
On ARM64, a 64kb region is reserved for the runtime services code. Unfortunately, this code overlaps with the spin table code, which also needs to be reserved. Thus now that the code is relocatable, allocate a new page from EFI, copy the spin table code into it, update any pointers to the old region and the start the secondary CPUs.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index d50c5a437b..bd85351705 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -79,6 +79,10 @@ int fsl_layerscape_wake_seconday_cores(void) u32 cores, cpu_up_mask = 1; int i, timeout = 10; u64 *table; +#ifdef CONFIG_EFI_LOADER + u64 reloc_addr = U32_MAX; + efi_status_t ret; +#endif
#ifdef COUNTER_FREQUENCY_REAL /* update for secondary cores */ @@ -87,6 +91,38 @@ int fsl_layerscape_wake_seconday_cores(void) (unsigned long)&__real_cntfrq + 8); #endif
+#ifdef CONFIG_EFI_LOADER + /* + * EFI will reserve 64kb for its runtime services. This will probably + * overlap with our spin table code, which is why we have to relocate + * it. + * Keep this after the __real_cntfrq update, so we have it when we + * copy the complete section here. + */ + ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, + EFI_RESERVED_MEMORY_TYPE, + efi_size_in_pages(secondary_boot_code_size), + &reloc_addr); + if (ret == EFI_SUCCESS) { + debug("Relocating spin table from %llx to %llx (size %lx)\n", + (u64)secondary_boot_code_start, reloc_addr, + secondary_boot_code_size); + memcpy((void *)reloc_addr, secondary_boot_code_start, + secondary_boot_code_size); + flush_dcache_range(reloc_addr, + reloc_addr + secondary_boot_code_size); + + /* set new entry point for secondary cores */ + secondary_boot_addr += (void *)reloc_addr - + secondary_boot_code_start; + flush_dcache_range((unsigned long)&secondary_boot_addr, + (unsigned long)&secondary_boot_addr + 8); + + /* this will be used to reserve the memory */ + secondary_boot_code_start = (void *)reloc_addr; + } +#endif + cores = cpu_mask(); /* Clear spin table so that secondary processors * observe the correct value after waking up from wfe.
On 6/1/20 9:53 PM, Michael Walle wrote:
On ARM64, a 64kb region is reserved for the runtime services code. Unfortunately, this code overlaps with the spin table code, which also needs to be reserved. Thus now that the code is relocatable, allocate a new page from EFI, copy the spin table code into it, update any pointers to the old region and the start the secondary CPUs.
Signed-off-by: Michael Walle michael@walle.cc
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index d50c5a437b..bd85351705 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -79,6 +79,10 @@ int fsl_layerscape_wake_seconday_cores(void) u32 cores, cpu_up_mask = 1; int i, timeout = 10; u64 *table; +#ifdef CONFIG_EFI_LOADER
- u64 reloc_addr = U32_MAX;
- efi_status_t ret;
+#endif
#ifdef COUNTER_FREQUENCY_REAL /* update for secondary cores */ @@ -87,6 +91,38 @@ int fsl_layerscape_wake_seconday_cores(void) (unsigned long)&__real_cntfrq + 8); #endif
+#ifdef CONFIG_EFI_LOADER
- /*
* EFI will reserve 64kb for its runtime services. This will probably* overlap with our spin table code, which is why we have to relocate* it.* Keep this after the __real_cntfrq update, so we have it when we* copy the complete section here.*/- ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
EFI_RESERVED_MEMORY_TYPE,efi_size_in_pages(secondary_boot_code_size),&reloc_addr);- if (ret == EFI_SUCCESS) {
debug("Relocating spin table from %llx to %llx (size %lx)\n",(u64)secondary_boot_code_start, reloc_addr,secondary_boot_code_size);memcpy((void *)reloc_addr, secondary_boot_code_start,secondary_boot_code_size);flush_dcache_range(reloc_addr,reloc_addr + secondary_boot_code_size);/* set new entry point for secondary cores */secondary_boot_addr += (void *)reloc_addr -secondary_boot_code_start;flush_dcache_range((unsigned long)&secondary_boot_addr,(unsigned long)&secondary_boot_addr + 8);
Wouldn't you want to flush the complete target range of memcpy() and afterwards call invalidate_icache_all(). At least this is what we do in other cases after copying instructions. Cf. efi_runtime_relocate().
Best regards
Heinrich
/* this will be used to reserve the memory */secondary_boot_code_start = (void *)reloc_addr;- }
+#endif
- cores = cpu_mask(); /* Clear spin table so that secondary processors
- observe the correct value after waking up from wfe.
Am 2020-06-02 22:00, schrieb Heinrich Schuchardt:
On 6/1/20 9:53 PM, Michael Walle wrote:
On ARM64, a 64kb region is reserved for the runtime services code. Unfortunately, this code overlaps with the spin table code, which also needs to be reserved. Thus now that the code is relocatable, allocate a new page from EFI, copy the spin table code into it, update any pointers to the old region and the start the secondary CPUs.
Signed-off-by: Michael Walle michael@walle.cc
arch/arm/cpu/armv8/fsl-layerscape/mp.c | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index d50c5a437b..bd85351705 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -79,6 +79,10 @@ int fsl_layerscape_wake_seconday_cores(void) u32 cores, cpu_up_mask = 1; int i, timeout = 10; u64 *table; +#ifdef CONFIG_EFI_LOADER
- u64 reloc_addr = U32_MAX;
- efi_status_t ret;
+#endif
#ifdef COUNTER_FREQUENCY_REAL /* update for secondary cores */ @@ -87,6 +91,38 @@ int fsl_layerscape_wake_seconday_cores(void) (unsigned long)&__real_cntfrq + 8); #endif
+#ifdef CONFIG_EFI_LOADER
- /*
* EFI will reserve 64kb for its runtime services. This willprobably
* overlap with our spin table code, which is why we have torelocate
* it.* Keep this after the __real_cntfrq update, so we have it when we* copy the complete section here.*/- ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
EFI_RESERVED_MEMORY_TYPE,efi_size_in_pages(secondary_boot_code_size),&reloc_addr);- if (ret == EFI_SUCCESS) {
debug("Relocating spin table from %llx to %llx (size %lx)\n",(u64)secondary_boot_code_start, reloc_addr,secondary_boot_code_size);memcpy((void *)reloc_addr, secondary_boot_code_start,secondary_boot_code_size);flush_dcache_range(reloc_addr,reloc_addr + secondary_boot_code_size);
dcache flush is done here. but icache is missing, correct.
/* set new entry point for secondary cores */secondary_boot_addr += (void *)reloc_addr -secondary_boot_code_start;flush_dcache_range((unsigned long)&secondary_boot_addr,(unsigned long)&secondary_boot_addr + 8);Wouldn't you want to flush the complete target range of memcpy() and afterwards call invalidate_icache_all(). At least this is what we do in other cases after copying instructions. Cf. efi_runtime_relocate().
see above.
-michael
/* this will be used to reserve the memory */secondary_boot_code_start = (void *)reloc_addr;- }
+#endif
- cores = cpu_mask(); /* Clear spin table so that secondary processors
- observe the correct value after waking up from wfe.
There are two issues:
(1) The spin table doesn't convert the endianness of the jump address. Although there is code for it, the result isn't used at all (x0). (2) If something goes wrong, the function returns. But that doesn't make sense at all.
Use the actual converted jump address as destination to fix. If there is an error, jump to a trap loop. And rearrange the code exception level switching code to make it smaller and clearer.
This reduces the size of the spin table code section from 696 bytes to 424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696 bytes to 632 bytes.
Signed-off-by: Michael Walle michael@walle.cc --- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 83 +++++-------------- 1 file changed, 23 insertions(+), 60 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index f082e10231..363ded03e6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -31,7 +31,7 @@ __spin_table: .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
.align 2 -ENTRY(__secondary_boot_func) +__secondary_boot_func: /* * MPIDR_EL1 Fields: * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) @@ -72,73 +72,36 @@ ENTRY(__secondary_boot_func) str x4, [x11, #8] /* STATUS */ dsb sy
-slave_cpu: +1: wfe - ldr x0, [x11] - cbz x0, slave_cpu -#ifndef CONFIG_ARMV8_SWITCH_TO_EL1 + ldr x4, [x11] + cbz x4, 1b mrs x1, sctlr_el2 -#else - mrs x1, sctlr_el1 -#endif - tbz x1, #25, cpu_is_le - rev x0, x0 /* BE to LE conversion */ -cpu_is_le: - ldr x5, [x11, #24] - cbz x5, 1f - + tbz x1, #25, 2f + rev x4, x4 /* BE to LE conversion */ +2: + ldr x6, =ES_TO_AARCH64 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x4, secondary_switch_to_el1 - ldr x5, =ES_TO_AARCH64 -#else - ldr x4, [x11] - ldr x5, =ES_TO_AARCH32 + adr x5, 3f + switch_el x7, 0f, _dead_loop, _dead_loop +0: armv8_switch_to_el2_m x5, x6, x7 #endif - bl secondary_switch_to_el2 - -1: +3: + ldr x7, [x11, #24] /* ARCH_COMP */ + cbz x7, 4f + ldr x6, =ES_TO_AARCH32 +4: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x4, secondary_switch_to_el1 + switch_el x7, _dead_loop, 0f, _dead_loop +0: armv8_switch_to_el1_m x4, x6, x7 #else - ldr x4, [x11] + switch_el x7, 0f, _dead_loop, _dead_loop +0: armv8_switch_to_el2_m x4, x6, x7 #endif - ldr x5, =ES_TO_AARCH64 - bl secondary_switch_to_el2 - -ENDPROC(__secondary_boot_func) - -ENTRY(secondary_switch_to_el2) - switch_el x6, 1f, 0f, 0f -0: ret -1: armv8_switch_to_el2_m x4, x5, x6 -ENDPROC(secondary_switch_to_el2) - -ENTRY(secondary_switch_to_el1) - mrs x0, mpidr_el1 - ubfm x1, x0, #8, #15 - ubfm x2, x0, #0, #1 - orr x10, x2, x1, lsl #2 /* x10 has LPID */ - - lsl x1, x10, #6 - adr x0, __spin_table - /* physical address of this cpus spin table element */ - add x11, x1, x0 - - ldr x4, [x11] - - ldr x5, [x11, #24] - cbz x5, 2f
- ldr x5, =ES_TO_AARCH32 - bl switch_to_el1 - -2: ldr x5, =ES_TO_AARCH64 - -switch_to_el1: - switch_el x6, 0f, 1f, 0f -0: ret -1: armv8_switch_to_el1_m x4, x5, x6 -ENDPROC(secondary_switch_to_el1) +_dead_loop: + wfe + b _dead_loop
/* Ensure that the literals used by the secondary boot code are * assembled within it (this is required so that we can protect
participants (2)
-
Heinrich Schuchardt -
Michael Walle