Add device tree for T2080RDB board and enable CONFIG_OF_CONTROL so that device tree can be compiled. Update board README for device tree usage.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - No change.

arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/t2080rdb.dts | 17 +++++++++++++++++ board/freescale/t208xrdb/README | 19 +++++++++++++++++++ configs/T2080RDB_NAND_defconfig | 2 ++ configs/T2080RDB_SDCARD_defconfig | 2 ++ configs/T2080RDB_SPIFLASH_defconfig | 2 ++ configs/T2080RDB_defconfig | 3 +++ 7 files changed, 46 insertions(+) create mode 100644 arch/powerpc/dts/t2080rdb.dts

diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 6a28f80..388a4b2 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+

dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb +dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb

diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts new file mode 100644 index 0000000..49c1765 --- /dev/null +++ b/arch/powerpc/dts/t2080rdb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T2080RDB Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "t2080.dtsi" + +/ { + model = "fsl,T2080RDB"; + compatible = "fsl,T2080RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; +}; diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index 42b2b92..9e4b28f 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -262,3 +262,22 @@ How to update the ucode of Freescale FMAN

For more details, please refer to T2080PCIe-RDB User Guide and access website www.freescale.com and Freescale QorIQ SDK Infocenter document. + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for t2080rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for NOR boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 1bb90f3..7eb7058 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -10,10 +10,12 @@ CONFIG_TARGET_T2080RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_TEXT_BASE=0xFFFD8000 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 1a7070c..9ea6698 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_TARGET_T2080RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_BOOTDELAY=10 diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index ceb0230..988897b 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index e782ba0..3f7e282 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -2,9 +2,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_CONTROL=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_R=y @@ -26,6 +28,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" # CONFIG_CMD_IRQ is not set +CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y

Add device tree for T1024RDB board and enable CONFIG_OF_CONTROL so that device tree can be compiled. Update board README for device tree usage.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - No change.

arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/e5500_power_isa.dtsi | 34 +++++++++++++++++++++++ arch/powerpc/dts/t1024rdb.dts | 17 ++++++++++++ arch/powerpc/dts/t102x.dtsi | 52 +++++++++++++++++++++++++++++++++++ board/freescale/t102xrdb/README | 19 +++++++++++++ configs/T1024RDB_NAND_defconfig | 2 ++ configs/T1024RDB_SDCARD_defconfig | 2 ++ configs/T1024RDB_SPIFLASH_defconfig | 2 ++ configs/T1024RDB_defconfig | 3 ++ 9 files changed, 132 insertions(+) create mode 100644 arch/powerpc/dts/e5500_power_isa.dtsi create mode 100644 arch/powerpc/dts/t1024rdb.dts create mode 100644 arch/powerpc/dts/t102x.dtsi

diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 9002393..b7acba5 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+

+dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb diff --git a/arch/powerpc/dts/e5500_power_isa.dtsi b/arch/powerpc/dts/e5500_power_isa.dtsi new file mode 100644 index 0000000..0a0943b --- /dev/null +++ b/arch/powerpc/dts/e5500_power_isa.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * e5500 Power ISA Device Tree Source (include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/ { + cpus { + power-isa-version = "2.06"; + power-isa-b; // Base + power-isa-e; // Embedded + power-isa-atb; // Alternate Time Base + power-isa-cs; // Cache Specification + power-isa-ds; // Decorated Storage + power-isa-e.ed; // Embedded.Enhanced Debug + power-isa-e.pd; // Embedded.External PID + power-isa-e.hv; // Embedded.Hypervisor + power-isa-e.le; // Embedded.Little-Endian + power-isa-e.pm; // Embedded.Performance Monitor + power-isa-e.pc; // Embedded.Processor Control + power-isa-ecl; // Embedded Cache Locking + power-isa-exp; // External Proxy + power-isa-fp; // Floating Point + power-isa-fp.r; // Floating Point.Record + power-isa-mmc; // Memory Coherence + power-isa-scpm; // Store Conditional Page Mobility + power-isa-wt; // Wait + power-isa-64; // 64-bit + fsl,eref-deo; // Data Cache Extended Operations + mmu-type = "power-embedded"; + }; +}; diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts new file mode 100644 index 0000000..19a6652 --- /dev/null +++ b/arch/powerpc/dts/t1024rdb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T1024RDB Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "t102x.dtsi" + +/ { + model = "fsl,T1024RDB"; + compatible = "fsl,T1024RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; +}; diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi new file mode 100644 index 0000000..2393e31 --- /dev/null +++ b/arch/powerpc/dts/t102x.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T102X Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e5500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e5500@0 { + device_type = "cpu"; + reg = <0>; + #cooling-cells = <2>; + }; + cpu1: PowerPC,e5500@1 { + device_type = "cpu"; + reg = <1>; + #cooling-cells = <2>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; +}; diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index a0af25a..dde3f8c 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -251,6 +251,25 @@ Software configurations and board settings SW3[3] = '0' for eMMC (or 'switch emmc' by software)

+device tree support and how to enable it for different configs +-------------------------------------------------------------- +device tree support is available for t1024rdb for below mentioned boot, +1. nor boot +2. nand boot +3. sd boot +4. spiflash boot + +to enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. config_default_device_tree="t1024rdb" (change default device tree name if required) +2. config_of_control +3. config_mpc85xx_have_reset_vector if reset vector is located at + config_reset_vector_address - 0xffc + +if device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for nor boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. + 2-stage NAND/SPI/SD boot loader ------------------------------- PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index ea00def..30acd0e 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -7,6 +7,8 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 6b966b6..7569e4e 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -8,6 +8,8 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 59e1e77..470674b 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -9,6 +9,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 683a619..146551d 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_T1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -29,6 +30,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" +CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y

Add device tree for P1020RDB boards and enable CONFIG_OF_CONTROL so that device tree can be compiled. Update board README for device tree usage.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - No change.

arch/powerpc/dts/Makefile | 2 ++ arch/powerpc/dts/e500v2_power_isa.dtsi | 26 +++++++++++++++++++++++ arch/powerpc/dts/p1020-post.dtsi | 27 ++++++++++++++++++++++++ arch/powerpc/dts/p1020.dtsi | 31 ++++++++++++++++++++++++++++ arch/powerpc/dts/p1020rdb-pc.dts | 23 +++++++++++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 23 +++++++++++++++++++++ arch/powerpc/dts/p1020rdb-pd.dts | 23 +++++++++++++++++++++ board/freescale/p1_p2_rdb_pc/README | 19 +++++++++++++++++ configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_defconfig | 3 +++ configs/P1020RDB-PC_NAND_defconfig | 2 ++ configs/P1020RDB-PC_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_defconfig | 3 +++ configs/P1020RDB-PD_NAND_defconfig | 2 ++ configs/P1020RDB-PD_SDCARD_defconfig | 2 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PD_defconfig | 3 +++ 20 files changed, 201 insertions(+) create mode 100644 arch/powerpc/dts/e500v2_power_isa.dtsi create mode 100644 arch/powerpc/dts/p1020-post.dtsi create mode 100644 arch/powerpc/dts/p1020.dtsi create mode 100644 arch/powerpc/dts/p1020rdb-pc.dts create mode 100644 arch/powerpc/dts/p1020rdb-pc_36b.dts create mode 100644 arch/powerpc/dts/p1020rdb-pd.dts

diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index f0d49aa..3a806bd 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+

+dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb +dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb diff --git a/arch/powerpc/dts/e500v2_power_isa.dtsi b/arch/powerpc/dts/e500v2_power_isa.dtsi new file mode 100644 index 0000000..010e8e5 --- /dev/null +++ b/arch/powerpc/dts/e500v2_power_isa.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * e500v2 Power ISA Device Tree Source (include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/ { + cpus { + power-isa-version = "2.03"; + power-isa-b; // Base + power-isa-e; // Embedded + power-isa-atb; // Alternate Time Base + power-isa-cs; // Cache Specification + power-isa-e.le; // Embedded.Little-Endian + power-isa-e.pm; // Embedded.Performance Monitor + power-isa-ecl; // Embedded Cache Locking + power-isa-mmc; // Memory Coherence + power-isa-sp; // Signal Processing Engine + power-isa-sp.fd; // SPE.Embedded Float Scalar Double + power-isa-sp.fs; // SPE.Embedded Float Scalar Single + power-isa-sp.fv; // SPE.Embedded Float Vector + mmu-type = "power-embedded"; + }; +}; diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi new file mode 100644 index 0000000..e1a4f50 --- /dev/null +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p1020-immr", "simple-bus"; + bus-frequency = <0x0>; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +}; diff --git a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi new file mode 100644 index 0000000..ee2b6f4 --- /dev/null +++ b/arch/powerpc/dts/p1020.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500v2_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,P1020@0 { + device_type = "cpu"; + reg = <0>; + }; + cpu1: PowerPC,P1020@1 { + device_type = "cpu"; + reg = <1>; + }; + }; +}; diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts new file mode 100644 index 0000000..fd68b8b --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020RDB-PC Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p1020.dtsi" + +/ { + model = "fsl,P1020RDB-PC"; + compatible = "fsl,P1020RDB-PC"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + }; +}; + +/include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts new file mode 100644 index 0000000..a23d031 --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020RDB-PC (36-bit address map) Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p1020.dtsi" + +/ { + model = "fsl,P1020RDB-PC"; + compatible = "fsl,P1020RDB-PC"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc@fffe00000 { + ranges = <0x0 0xf 0xffe00000 0x100000>; + }; +}; + +/include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts new file mode 100644 index 0000000..81f25a3 --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pd.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020RDB-PD Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p1020.dtsi" + +/ { + model = "fsl,P1020RDB-PD"; + compatible = "fsl,P1020RDB-PD"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + }; +}; + +/include/ "p1020-post.dtsi" diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index f4cc43f..26902de 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -45,3 +45,22 @@ enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below

'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for p1020rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for NOR boot. +2. use 'u-boot-with-spl.bin' for other boot. diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index a1b61f9..8fce49d 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -7,6 +7,8 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index c1e4386..80a4a0a 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -8,6 +8,8 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 4c97d99..ee565d4 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -9,6 +9,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 8ada9bb..7d7c55f 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -1,8 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 409c7c0..b729089 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -7,6 +7,8 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 1dd5b69..4622efd 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -8,6 +8,8 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 5f30b8a..9cd897f 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -9,6 +9,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index dec97c4..595ff5f 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -1,8 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 1d7fa4d..b45122d 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -7,6 +7,8 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 137527b..c559879 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -8,6 +8,8 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index a822d44..1de88fc 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -9,6 +9,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 0f25faf..0963553 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -2,7 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1020RDB_PD=y +CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y

Add device tree for P1041RDB board and enable CONFIG_OF_CONTROL so that device tree can be compiled. Update board README for device tree usage.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - No change.

arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/e500mc_power_isa.dtsi | 33 ++++++++++++++++++ arch/powerpc/dts/p2041.dtsi | 63 ++++++++++++++++++++++++++++++++++ arch/powerpc/dts/p2041rdb.dts | 18 ++++++++++ board/freescale/p2041rdb/README | 18 ++++++++++ configs/P2041RDB_NAND_defconfig | 3 ++ configs/P2041RDB_SDCARD_defconfig | 3 ++ configs/P2041RDB_SPIFLASH_defconfig | 3 ++ configs/P2041RDB_defconfig | 3 ++ 9 files changed, 145 insertions(+) create mode 100644 arch/powerpc/dts/e500mc_power_isa.dtsi create mode 100644 arch/powerpc/dts/p2041.dtsi create mode 100644 arch/powerpc/dts/p2041rdb.dts

diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index bee1e2d..3123249 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb +dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb diff --git a/arch/powerpc/dts/e500mc_power_isa.dtsi b/arch/powerpc/dts/e500mc_power_isa.dtsi new file mode 100644 index 0000000..e486ae5 --- /dev/null +++ b/arch/powerpc/dts/e500mc_power_isa.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * e500mc Power ISA Device Tree Source (include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/ { + cpus { + power-isa-version = "2.06"; + power-isa-b; // Base + power-isa-e; // Embedded + power-isa-atb; // Alternate Time Base + power-isa-cs; // Cache Specification + power-isa-ds; // Decorated Storage + power-isa-e.ed; // Embedded.Enhanced Debug + power-isa-e.pd; // Embedded.External PID + power-isa-e.hv; // Embedded.Hypervisor + power-isa-e.le; // Embedded.Little-Endian + power-isa-e.pm; // Embedded.Performance Monitor + power-isa-e.pc; // Embedded.Processor Control + power-isa-ecl; // Embedded Cache Locking + power-isa-exp; // External Proxy + power-isa-fp; // Floating Point + power-isa-fp.r; // Floating Point.Record + power-isa-mmc; // Memory Coherence + power-isa-scpm; // Store Conditional Page Mobility + power-isa-wt; // Wait + fsl,eref-deo; // Data Cache Extended Operations + mmu-type = "power-embedded"; + }; +}; diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi new file mode 100644 index 0000000..9aa0422 --- /dev/null +++ b/arch/powerpc/dts/p2041.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2041 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500mc_power_isa.dtsi" + +/ { + compatible = "fsl,P2041"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e500mc@0 { + device_type = "cpu"; + reg = <0>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e500mc@1 { + device_type = "cpu"; + reg = <1>; + fsl,portid-mapping = <0x40000000>; + }; + cpu2: PowerPC,e500mc@2 { + device_type = "cpu"; + reg = <2>; + fsl,portid-mapping = <0x20000000>; + }; + cpu3: PowerPC,e500mc@3 { + device_type = "cpu"; + reg = <3>; + fsl,portid-mapping = <0x10000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; +}; diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts new file mode 100644 index 0000000..6e9d9c0 --- /dev/null +++ b/arch/powerpc/dts/p2041rdb.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2041RDB Device Tree Source + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p2041.dtsi" + +/ { + model = "fsl,P2041RDB"; + compatible = "fsl,P2041RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + +}; diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README index 9b5539f..79f77e4 100644 --- a/board/freescale/p2041rdb/README +++ b/board/freescale/p2041rdb/README @@ -85,6 +85,24 @@ Boot from SPI flash SW1[1-5] = 10100 Note: 1 stands for 'on', 0 stands for 'off'

+Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for p2041rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CONFIG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin' +instead of u-boot.bin for all boot. + CPLD command ============ The CPLD is used to control the power sequence and some serdes lane diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 44966d8..73baf49 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P2041RDB=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 3d558c5..d75f8b1 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P2041RDB=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 4fb3794..925f0cd 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P2041RDB=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 2a70296..1923b7a 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P2041RDB=y +CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y

Add device tree for P4080DS board and enable CONFIG_OF_CONTROL so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - No change.

arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/p4080.dtsi | 83 ++++++++++++++++++++++++++++++++++++++ arch/powerpc/dts/p4080ds.dts | 18 +++++++++ configs/P4080DS_SDCARD_defconfig | 3 ++ configs/P4080DS_SPIFLASH_defconfig | 3 ++ configs/P4080DS_defconfig | 3 ++ 6 files changed, 111 insertions(+) create mode 100644 arch/powerpc/dts/p4080.dtsi create mode 100644 arch/powerpc/dts/p4080ds.dts

diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index fe2d4e4..ffd929c 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb +dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi new file mode 100644 index 0000000..7c8dbae --- /dev/null +++ b/arch/powerpc/dts/p4080.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P4080/P4040 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500mc_power_isa.dtsi" + +/ { + compatible = "fsl,P4080"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e500mc@0 { + device_type = "cpu"; + reg = <0>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e500mc@1 { + device_type = "cpu"; + reg = <1>; + fsl,portid-mapping = <0x40000000>; + }; + cpu2: PowerPC,e500mc@2 { + device_type = "cpu"; + reg = <2>; + fsl,portid-mapping = <0x20000000>; + }; + cpu3: PowerPC,e500mc@3 { + device_type = "cpu"; + reg = <3>; + fsl,portid-mapping = <0x10000000>; + }; + cpu4: PowerPC,e500mc@4 { + device_type = "cpu"; + reg = <4>; + fsl,portid-mapping = <0x08000000>; + }; + cpu5: PowerPC,e500mc@5 { + device_type = "cpu"; + reg = <5>; + fsl,portid-mapping = <0x04000000>; + }; + cpu6: PowerPC,e500mc@6 { + device_type = "cpu"; + reg = <6>; + fsl,portid-mapping = <0x02000000>; + }; + cpu7: PowerPC,e500mc@7 { + device_type = "cpu"; + reg = <7>; + fsl,portid-mapping = <0x01000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; +}; diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts new file mode 100644 index 0000000..15a0f66 --- /dev/null +++ b/arch/powerpc/dts/p4080ds.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P4080DS Device Tree Source + * + * Copyright 2011 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "p4080.dtsi" + +/ { + model = "fsl,P4080DS"; + compatible = "fsl,P4080DS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + +}; diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index b67e12a..0aaf09a 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P4080DS=y +CONFIG_DEFAULT_DEVICE_TREE="p4080ds" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index b108367..3a91df2 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P4080DS=y +CONFIG_DEFAULT_DEVICE_TREE="p4080ds" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index ee4f51d..d89d69f 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P4080DS=y +CONFIG_DEFAULT_DEVICE_TREE="p4080ds" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y

Add CONFIG_RESET_VECTOR_ADDRESS definition with the default value in u-boot.dtsi to fix the build error below. In the configuration header file of some MPC85xx boards, there is not the definition of CONFIG_RESET_VECTOR_ADDRESS, while CONFIG_SYS_MPC85XX_NO_RESETVEC is also not defined. In this case, it will lack of definition of CONFIG_RESET_VECTOR_ADDRESS in u-boot.dtsi, and the address 0xfffffffc will be used as the boot page by default.

Error log: DTC arch/powerpc/dts/mpc8548cds.dtb DTC arch/powerpc/dts/mpc8548cds_36b.dtb Error: arch/powerpc/dts/u-boot.dtsi:28.15-16 syntax error FATAL ERROR: Unable to parse input tree Error: arch/powerpc/dts/u-boot.dtsi:28.15-16 syntax error FATAL ERROR: Unable to parse input tree scripts/Makefile.lib:308: recipe for target 'arch/powerpc/dts/mpc8548cds.dtb' failed make[2]: *** [arch/powerpc/dts/mpc8548cds.dtb] Error 1 make[2]: *** Waiting for unfinished jobs.... scripts/Makefile.lib:308: recipe for target 'arch/powerpc/dts/mpc8548cds_36b.dtb' failed make[2]: *** [arch/powerpc/dts/mpc8548cds_36b.dtb] Error 1 dts/Makefile:38: recipe for target 'arch-dtbs' failed make[1]: *** [arch-dtbs] Error 2 Makefile:1038: recipe for target 'dts/dt.dtb' failed make: *** [dts/dt.dtb] Error 2

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - No change.

arch/powerpc/dts/u-boot.dtsi | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/powerpc/dts/u-boot.dtsi b/arch/powerpc/dts/u-boot.dtsi index 213d543..9661f4d 100644 --- a/arch/powerpc/dts/u-boot.dtsi +++ b/arch/powerpc/dts/u-boot.dtsi @@ -24,6 +24,9 @@ #endif }; #ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif powerpc-mpc85xx-bootpg-resetvec { offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; };

Add device tree for MPC8548CDS board and enable CONFIG_OF_CONTROL so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - No change.

arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/mpc8548-post.dtsi | 27 +++++++++++++++++++++++++++ arch/powerpc/dts/mpc8548.dtsi | 27 +++++++++++++++++++++++++++ arch/powerpc/dts/mpc8548cds.dts | 23 +++++++++++++++++++++++ arch/powerpc/dts/mpc8548cds_36b.dts | 23 +++++++++++++++++++++++ configs/MPC8548CDS_36BIT_defconfig | 3 +++ configs/MPC8548CDS_defconfig | 3 +++ configs/MPC8548CDS_legacy_defconfig | 3 +++ 8 files changed, 110 insertions(+) create mode 100644 arch/powerpc/dts/mpc8548-post.dtsi create mode 100644 arch/powerpc/dts/mpc8548.dtsi create mode 100644 arch/powerpc/dts/mpc8548cds.dts create mode 100644 arch/powerpc/dts/mpc8548cds_36b.dts

diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 0e234cc..021c85f 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+

+dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi new file mode 100644 index 0000000..5533a4b --- /dev/null +++ b/arch/powerpc/dts/mpc8548-post.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8548 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8548-immr", "simple-bus"; + bus-frequency = <0x0>; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +}; diff --git a/arch/powerpc/dts/mpc8548.dtsi b/arch/powerpc/dts/mpc8548.dtsi new file mode 100644 index 0000000..b24567d --- /dev/null +++ b/arch/powerpc/dts/mpc8548.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8548CDS Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e500v2_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8548@0 { + device_type = "cpu"; + reg = <0>; + }; + }; +}; diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts new file mode 100644 index 0000000..cceea34 --- /dev/null +++ b/arch/powerpc/dts/mpc8548cds.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8548CDS Device Tree Source + * + * Copyright 2006 - 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "mpc8548.dtsi" + +/ { + model = "fsl,MPC8548CDS"; + compatible = "fsl,MPC8548CDS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc8548@e0000000 { + ranges = <0x0 0x0 0xe0000000 0x100000>; + }; +}; + +/include/ "mpc8548-post.dtsi" diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts b/arch/powerpc/dts/mpc8548cds_36b.dts new file mode 100644 index 0000000..faff35c --- /dev/null +++ b/arch/powerpc/dts/mpc8548cds_36b.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * MPC8548CDS (36-bit address map) Device Tree Source + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "mpc8548.dtsi" + +/ { + model = "fsl,MPC8548CDS"; + compatible = "fsl,MPC8548CDS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + soc: soc8548@fe0000000 { + ranges = <0x0 0xf 0xe0000000 0x100000>; + }; +}; + +/include/ "mpc8548-post.dtsi" diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 672dc78..f259f19 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -1,8 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y +CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 09726d2..72239da 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -1,8 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y +CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" +CONFIG_OF_CONTROL=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 4a2d11f..f2420c3 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -1,8 +1,11 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xFFF80000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y +CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" +CONFIG_OF_CONTROL=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY"