This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF, which are clock gates in the HDMI output path for the RK3399.

As these are enabled by default (i.e. after reset), we don't implement any logic to actively open/close these clock gates and simply assume that their reset-default has not been changed.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---

drivers/clk/rockchip/clk_rk3399.c | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 72395e2..d820ea6 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -879,6 +879,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART0: case SCLK_UART2: return 24000000; + break; + case PCLK_HDMI_CTRL: + break; case DCLK_VOP0: case DCLK_VOP1: break; @@ -916,6 +919,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SPI0...SCLK_SPI5: ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); break; + case PCLK_HDMI_CTRL: + case PCLK_VIO_GRF: + /* the PCLK gates for video are enabled by default */ + break; case DCLK_VOP0: case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);

This commit enables RK3399 support for HDMI through the following changes: - adds a driverdata structure to mirror some subtle version differences between the RK3399 VOPs and those in the RK3288 (e.g. the pin-polarity configuration) - configures the VOP to output 32bpp for HDMI - handles whether a VOP can output 10BIT data or not (i.e. RGBaaa vs. RGB888) using the driverdata structure

And as we touch this file anyway, we also increase the size of the framebuffer to a slightly overzealous 4K2K@32bpp.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---

arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 11 ++ drivers/video/rockchip/rk_vop.c | 180 ++++++++++++++++++++---- 2 files changed, 161 insertions(+), 30 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h index 0ce3d67..bca6860 100644 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -196,9 +196,20 @@ enum vop_modes { #define V_DSP_DEN_POL(x) (((x) & 1) << 6) #define V_DSP_VSYNC_POL(x) (((x) & 1) << 5) #define V_DSP_HSYNC_POL(x) (((x) & 1) << 4) +#define V_DSP_PIN_POL(x) (((x) & 0xf) << 4) #define V_DSP_OUT_MODE(x) ((x) & 0xf)

/* VOP_DSP_CTRL1 */ +#define V_RK3399_DSP_MIPI_POL(x) ((x) << 28) +#define V_RK3399_DSP_EDP_POL(x) ((x) << 24) +#define V_RK3399_DSP_HDMI_POL(x) ((x) << 20) +#define V_RK3399_DSP_LVDS_POL(x) ((x) << 16) + +#define M_RK3399_DSP_MIPI_POL (V_RK3399_DSP_MIPI_POL(0xf)) +#define M_RK3399_DSP_EDP_POL (V_RK3399_DSP_EDP_POL(0xf)) +#define M_RK3399_DSP_HDMI_POL (V_RK3399_DSP_HDMI_POL(0xf)) +#define M_RK3399_DSP_LVDS_POL (V_RK3399_DSP_LVDS_POL(0xf)) + #define M_DSP_LAYER3_SEL (3 << 14) #define M_DSP_LAYER2_SEL (3 << 12) #define M_DSP_LAYER1_SEL (3 << 10) diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index bc02f80..01b4b6a 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

+#define DEBUG + #include <common.h> #include <clk.h> #include <display.h> @@ -28,11 +30,78 @@

DECLARE_GLOBAL_DATA_PTR;

+enum vop_pol { + HSYNC_POSITIVE = 0, + VSYNC_POSITIVE = 1, + DEN_NEGATIVE = 2, + DCLK_INVERT = 3 +}; + struct rk_vop_priv { struct rk3288_vop *regs; struct rk3288_grf *grf; };

+enum vop_features { + VOP_FEATURE_OUTPUT_10BIT = (1 << 0), +}; + +struct rkvop_driverdata { + /* configuration */ + u32 features; + /* block-specific setters/getters */ + void (*set_pin_polarity)(struct udevice *, enum vop_modes, u32); +}; + +static void rk3288_set_pin_polarity(struct udevice *dev, + enum vop_modes mode, u32 polarity) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + + /* The RK3328 VOP (v3.1) has its polarity configuration in ctrl0 */ + clrsetbits_le32(&regs->dsp_ctrl0, + M_DSP_DCLK_POL | M_DSP_DEN_POL | + M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, + V_DSP_PIN_POL(polarity)); +} + +static void rk3399_set_pin_polarity(struct udevice *dev, + enum vop_modes mode, u32 polarity) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + + /* + * The RK3399 VOPs (v3.5 and v3.6) require a per-mode setting of + * the polarity configuration (in ctrl1). + */ + switch (mode) { + case VOP_MODE_HDMI: + clrsetbits_le32(&regs->dsp_ctrl1, + M_RK3399_DSP_HDMI_POL, + V_RK3399_DSP_HDMI_POL(polarity)); + break; + + case VOP_MODE_EDP: + clrsetbits_le32(&regs->dsp_ctrl1, + M_RK3399_DSP_EDP_POL, + V_RK3399_DSP_EDP_POL(polarity)); + break; + + case VOP_MODE_MIPI: + clrsetbits_le32(&regs->dsp_ctrl1, + M_RK3399_DSP_MIPI_POL, + V_RK3399_DSP_MIPI_POL(polarity)); + break; + + case VOP_MODE_LVDS: + /* The RK3399 has neither parallel RGB nor LVDS output. */ + default: + debug("%s: unsupported output mode %x\n", __func__, mode); + } +} + void rkvop_enable(struct rk3288_vop *regs, ulong fbbase, int fb_bits_per_pixel, const struct display_timing *edid) { @@ -89,50 +158,77 @@ void rkvop_enable(struct rk3288_vop *regs, ulong fbbase, writel(0x01, &regs->reg_cfg_done); /* enable reg config */ }

-void rkvop_mode_set(struct rk3288_vop *regs, - const struct display_timing *edid, enum vop_modes mode) +static void rkvop_set_pin_polarity(struct udevice *dev, + enum vop_modes mode, u32 polarity) { - u32 hactive = edid->hactive.typ; - u32 vactive = edid->vactive.typ; - u32 hsync_len = edid->hsync_len.typ; - u32 hback_porch = edid->hback_porch.typ; - u32 vsync_len = edid->vsync_len.typ; - u32 vback_porch = edid->vback_porch.typ; - u32 hfront_porch = edid->hfront_porch.typ; - u32 vfront_porch = edid->vfront_porch.typ; - uint flags; - int mode_flags; + struct rkvop_driverdata *ops = + (struct rkvop_driverdata *)dev_get_driver_data(dev); + + if (ops->set_pin_polarity) + ops->set_pin_polarity(dev, mode, polarity); +} + +static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs;

switch (mode) { case VOP_MODE_HDMI: clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); break; + case VOP_MODE_EDP: - default: clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, V_EDP_OUT_EN(1)); break; + case VOP_MODE_LVDS: clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN, V_RGB_OUT_EN(1)); break; + + default: + debug("%s: unsupported output mode %x\n", __func__, mode); } +}

- if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP) - /* RGBaaa */ - mode_flags = 15; - else - /* RGB888 */ - mode_flags = 0; +void rkvop_mode_set(struct udevice *dev, + const struct display_timing *edid, enum vop_modes mode) +{ + struct rk_vop_priv *priv = dev_get_priv(dev); + struct rk3288_vop *regs = priv->regs; + struct rkvop_driverdata *data = + (struct rkvop_driverdata *)dev_get_driver_data(dev); + + u32 hactive = edid->hactive.typ; + u32 vactive = edid->vactive.typ; + u32 hsync_len = edid->hsync_len.typ; + u32 hback_porch = edid->hback_porch.typ; + u32 vsync_len = edid->vsync_len.typ; + u32 vback_porch = edid->vback_porch.typ; + u32 hfront_porch = edid->hfront_porch.typ; + u32 vfront_porch = edid->vfront_porch.typ; + int mode_flags; + u32 pin_polarity;

- flags = V_DSP_OUT_MODE(mode_flags) | - V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) | - V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)); + pin_polarity = BIT(DCLK_INVERT); + if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH) + pin_polarity |= BIT(HSYNC_POSITIVE); + if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH) + pin_polarity |= BIT(VSYNC_POSITIVE);

- clrsetbits_le32(&regs->dsp_ctrl0, - M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, - flags); + rkvop_set_pin_polarity(dev, mode, pin_polarity); + rkvop_enable_output(dev, mode); + + mode_flags = 0; /* RGB888 */ + if ((data->features & VOP_FEATURE_OUTPUT_10BIT) && + (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)) + mode_flags = 15; /* RGBaaa */ + + clrsetbits_le32(&regs->dsp_ctrl0, M_DSP_OUT_MODE, + V_DSP_OUT_MODE(mode_flags));

writel(V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch), @@ -249,8 +345,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase, return ret; }

- rkvop_mode_set(regs, &timing, vop_id); - + rkvop_mode_set(dev, &timing, vop_id); rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);

ret = display_enable(disp, 1 << l2bpp, &timing); @@ -341,19 +436,44 @@ static int rk_vop_bind(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);

- plat->size = 1920 * 1080 * 2; + /* + * Let's allocate an excessively large framebuffer (i.e. the + * maximum any of the supported VOP variants can output), so + * we are prepared for the day when someone first tries to + * drive a 4K2K HDMI signal from the bootloader. + */ + plat->size = 4096 * 2160 * 4;

return 0; }

-static const struct video_ops rk_vop_ops = { +struct rkvop_driverdata rk3288_driverdata = { + .features = VOP_FEATURE_OUTPUT_10BIT, + .set_pin_polarity = rk3288_set_pin_polarity, +}; + +struct rkvop_driverdata rk3399_lit_driverdata = { + .set_pin_polarity = rk3399_set_pin_polarity, +}; + +struct rkvop_driverdata rk3399_big_driverdata = { + .features = VOP_FEATURE_OUTPUT_10BIT, + .set_pin_polarity = rk3399_set_pin_polarity, };

static const struct udevice_id rk_vop_ids[] = { - { .compatible = "rockchip,rk3288-vop" }, + { .compatible = "rockchip,rk3288-vop", + .data = (ulong)&rk3288_driverdata }, + { .compatible = "rockchip,rk3399-vop-big", + .data = (ulong)&rk3399_big_driverdata }, + { .compatible = "rockchip,rk3399-vop-lit", + .data = (ulong)&rk3399_lit_driverdata }, { } };

+static const struct video_ops rk_vop_ops = { +}; + U_BOOT_DRIVER(rk_vop) = { .name = "rk_vop", .id = UCLASS_VIDEO,

This commit enables the RK3399 HDMI TX, which is very similar to the one found on the RK3288. The differences between the two SoCs (mainly the input VOP selection) is abstracted away through the driverdata.

Note that the I2C communication for reading the EDID works well with the default settings, but does not with the alternate settings used on the RK3288... so this configuration aspect also is part of the driverdata.

Having some sort of DTS-based configuration for the regulator dependencies would be nice for the future, but for now we simply use lists of regulator names (also via driverdata) that we probe.

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---

arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 5 + drivers/video/rockchip/rk_hdmi.c | 165 +++++++++++++++++++----- 2 files changed, 135 insertions(+), 35 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index 22d8d97..ddd558e 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -462,6 +462,11 @@ enum { GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT, GRF_UART_DBG_SEL_C = 2,

+ /* GRF_SOC_CON20 */ + GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6, + GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6, + GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6, + /* PMUGRF_GPIO0A_IOMUX */ PMUGRF_GPIO0A6_SEL_SHIFT = 12, PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT, diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index db07588..ea92551 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -1,10 +1,13 @@ /* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH * Copyright (c) 2015 Google, Inc * Copyright 2014 Rockchip Inc. * * SPDX-License-Identifier: GPL-2.0+ */

+#define DEBUG + #include <common.h> #include <clk.h> #include <display.h> @@ -16,12 +19,25 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/hardware.h> #include <asm/arch/grf_rk3288.h> +#include <asm/arch/grf_rk3399.h> #include <power/regulator.h>

struct rk_hdmi_priv { struct dw_hdmi hdmi; - struct rk3288_grf *grf; + void *grf; +}; + +struct rkhdmi_driverdata { + /* configuration */ + u8 i2c_clk_high; + u8 i2c_clk_low; + const char * const *regulator_names; + u32 regulator_names_cnt; + /* setters/getters */ + int (*set_input_vop)(struct udevice *dev); + int (*clk_config)(struct udevice *dev); };

static const struct hdmi_phy_config rockchip_phy_config[] = { @@ -65,6 +81,60 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { } };

+static int rk3288_set_input_vop(struct udevice *dev) +{ + struct rk_hdmi_priv *priv = dev_get_priv(dev); + struct display_plat *uc_plat = dev_get_uclass_platdata(dev); + int vop_id = uc_plat->source_id; + struct rk3288_grf *grf = priv->grf; + + /* hdmi source select hdmi controller */ + rk_setreg(&grf->soc_con6, 1 << 15); + + /* hdmi data from vop id */ + rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0); + + return 0; +} + +static int rk3399_set_input_vop(struct udevice *dev) +{ + struct rk_hdmi_priv *priv = dev_get_priv(dev); + struct display_plat *uc_plat = dev_get_uclass_platdata(dev); + int vop_id = uc_plat->source_id; + struct rk3399_grf_regs *grf = priv->grf; + + /* hdmi data from vop id */ + rk_clrsetreg(&grf->soc_con20, GRF_RK3399_HDMI_VOP_SEL_MASK, + (vop_id == 1) ? GRF_RK3399_HDMI_VOP_SEL_L : 0); + + return 0; +} + +static int rk3288_clk_config(struct udevice *dev) +{ + struct display_plat *uc_plat = dev_get_uclass_platdata(dev); + struct clk clk; + int ret; + + /* + * Configure the maximum clock to permit whatever resolution the + * monitor wants + */ + ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); + if (ret >= 0) { + ret = clk_set_rate(&clk, 384000000); + clk_free(&clk); + } + if (ret < 0) { + debug("%s: Failed to set clock in source device '%s': ret=%d\n", + __func__, uc_plat->src_dev->name, ret); + return ret; + } + + return 0; +} + static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) { struct rk_hdmi_priv *priv = dev_get_priv(dev); @@ -83,20 +153,16 @@ static int rk_hdmi_enable(struct udevice *dev, int panel_bpp, static int rk_hdmi_ofdata_to_platdata(struct udevice *dev) { struct rk_hdmi_priv *priv = dev_get_priv(dev); + struct rkhdmi_driverdata *data = + (struct rkhdmi_driverdata *)dev_get_driver_data(dev); struct dw_hdmi *hdmi = &priv->hdmi;

hdmi->ioaddr = (ulong)dev_get_addr(dev); hdmi->mpll_cfg = rockchip_mpll_cfg; hdmi->phy_cfg = rockchip_phy_config; - hdmi->i2c_clk_high = 0x7a; - hdmi->i2c_clk_low = 0x8d; + hdmi->i2c_clk_high = data->i2c_clk_high; + hdmi->i2c_clk_low = data->i2c_clk_low;

- /* - * TODO(sjg@chromium.org): The above values don't work - these ones - * work better, but generate lots of errors in the data. - */ - hdmi->i2c_clk_high = 0x0d; - hdmi->i2c_clk_low = 0x0d; hdmi->reg_io_width = 4; hdmi->phy_set = dw_hdmi_phy_cfg;

@@ -107,13 +173,15 @@ static int rk_hdmi_ofdata_to_platdata(struct udevice *dev)

static int rk_hdmi_probe(struct udevice *dev) { - struct display_plat *uc_plat = dev_get_uclass_platdata(dev); + struct rkhdmi_driverdata *data = + (struct rkhdmi_driverdata *)dev_get_driver_data(dev); struct rk_hdmi_priv *priv = dev_get_priv(dev); struct dw_hdmi *hdmi = &priv->hdmi; struct udevice *reg; struct clk clk; + const char *regulator_name; int ret; - int vop_id = uc_plat->source_id; + int i;

ret = clk_get_by_index(dev, 0, &clk); if (ret >= 0) { @@ -125,33 +193,27 @@ static int rk_hdmi_probe(struct udevice *dev) return ret; }

- /* - * Configure the maximum clock to permit whatever resolution the - * monitor wants - */ - ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); - if (ret >= 0) { - ret = clk_set_rate(&clk, 384000000); - clk_free(&clk); - } - if (ret < 0) { - debug("%s: Failed to set clock in source device '%s': ret=%d\n", - __func__, uc_plat->src_dev->name, ret); - return ret; + if (data->clk_config) { + ret = data->clk_config(dev); + if (ret < 0) + return ret; }

- ret = regulator_get_by_platname("vcc50_hdmi", &reg); - if (!ret) - ret = regulator_set_enable(reg, true); - if (ret) - debug("%s: Cannot set regulator vcc50_hdmi\n", __func__); + for (i = 0; i < data->regulator_names_cnt; ++i) { + regulator_name = data->regulator_names[i]; + debug("%s: probing regulator '%s'\n", __func__, regulator_name);

- /* hdmi source select hdmi controller */ - rk_setreg(&priv->grf->soc_con6, 1 << 15); + ret = regulator_autoset_by_name(regulator_name, &reg); + if (!ret) + ret = regulator_set_enable(reg, true); + }

- /* hdmi data from vop id */ - rk_clrsetreg(&priv->grf->soc_con6, 1 << 4, - (vop_id == 1) ? (1 << 4) : 0); + if (!data->set_input_vop) { + debug("%s: data->set_input_vop not set\n", __func__); + return -1; + } + + data->set_input_vop(dev);

ret = dw_hdmi_phy_wait_for_hpd(hdmi); if (ret < 0) { @@ -170,8 +232,41 @@ static const struct dm_display_ops rk_hdmi_ops = { .enable = rk_hdmi_enable, };

+static const char * const rk3288_regulator_names[] = { + "vcc50_hdmi", +}; + +static const struct rkhdmi_driverdata rk3288_driverdata = { + /* + * TODO(sjg@chromium.org): The above values don't work - these ones + * work better, but generate lots of errors in the data. + */ + .i2c_clk_high = 0x0d, + .i2c_clk_low = 0x0d, + .regulator_names = rk3288_regulator_names, + .regulator_names_cnt = ARRAY_SIZE(rk3288_regulator_names), + .set_input_vop = rk3288_set_input_vop, + .clk_config = rk3288_clk_config, +}; + +static const char * const rk3399_regulator_names[] = { + "vcc1v8_hdmi", + "vcc0v9_hdmi" +}; + +static const struct rkhdmi_driverdata rk3399_driverdata = { + .i2c_clk_high = 0x7a, + .i2c_clk_low = 0x8d, + .regulator_names = rk3399_regulator_names, + .regulator_names_cnt = ARRAY_SIZE(rk3399_regulator_names), + .set_input_vop = rk3399_set_input_vop, +}; + static const struct udevice_id rk_hdmi_ids[] = { - { .compatible = "rockchip,rk3288-dw-hdmi" }, + { .compatible = "rockchip,rk3288-dw-hdmi", + .data = (ulong)&rk3288_driverdata }, + { .compatible = "rockchip,rk3399-dw-hdmi", + .data = (ulong)&rk3399_driverdata }, { } };