[U-Boot] [PATCH v2 1/2] SECURE_BOOT: Update bootscript and its hdr addresses
Update bootscript and its hdr addresses for Layerscape Chasis 3 based platforms instead of individual SoCs.
Signed-off-by: Sumit Garg sumit.garg@nxp.com Signed-off-by: Udit Agarwal udit.agarwal@nxp.com ---
Changes for V2: Modified the subject
arch/arm/include/asm/fsl_secure_boot.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 933e09c..f34ffc7 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -84,7 +84,7 @@ * Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD) */ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ defined(CONFIG_SD_BOOT) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif @@ -92,11 +92,11 @@ * The address needs to be modified according to NOR, NAND, SD and * DDR memory map */ -#ifdef CONFIG_LS2080A -#define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000 -#define CONFIG_BS_ADDR_DEVICE 0x583900000 -#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 -#define CONFIG_BS_ADDR_RAM 0xa3900000 +#ifdef CONFIG_FSL_LSCH3 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000 +#define CONFIG_BS_ADDR_DEVICE 0x580e00000 +#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000 +#define CONFIG_BS_ADDR_RAM 0xa0e00000 #define CONFIG_BS_HDR_SIZE 0x00002000 #define CONFIG_BS_SIZE 0x00001000 #else
Add secure boot validation of MC, DPC images using esbc_validate command.
Signed-off-by: Sumit Garg sumit.garg@nxp.com Signed-off-by: Udit Agarwal udit.agarwal@nxp.com ---
Changes for V2: Use of #ifdef instead of #ifndef with CONFIG_SECURE_BOOT macro and coresponding changes in mcinitcmd command.
include/configs/ls2080aqds.h | 21 ++++++++++++++++++++- include/configs/ls2080ardb.h | 30 ++++++++++++++++++++++++++++-- 2 files changed, 48 insertions(+), 3 deletions(-)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 838568f..6d566e8 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -365,6 +365,7 @@ unsigned long get_board_ddr_clk(void);
/* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CONFIG_SECURE_BOOT #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ @@ -376,8 +377,26 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ + "mcinitcmd=esbc_validate 0x580c80000;" \ + "esbc_validate 0x580cc0000;" \ + "fsl_mc start mc 0x580300000" \ " 0x580800000 \0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581100000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" +#endif /* CONFIG_SECURE_BOOT */ +
#ifdef CONFIG_FSL_MC_ENET #define CONFIG_FSL_MEMAC diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 32fa0eb..ee99126 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -328,6 +328,7 @@ unsigned long get_board_sys_clk(void);
/* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CONFIG_SECURE_BOOT #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "scriptaddr=0x80800000\0" \ @@ -345,9 +346,34 @@ unsigned long get_board_sys_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "fdtfile=fsl-ls2080a-rdb.dtb\0" \ - "mcinitcmd=fsl_mc start mc 0x580300000" \ - " 0x580800000 \0" \ + "mcinitcmd=esbc_validate 0x580c80000;" \ + "esbc_validate 0x580cc0000;" \ + "fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" \ BOOTENV +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581100000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "fdtfile=fsl-ls2080a-rdb.dtb\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" \ + BOOTENV +#endif +
#undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
On 01/05/2017 08:30 PM, Udit Agarwal wrote:
Update bootscript and its hdr addresses for Layerscape Chasis 3 based platforms instead of individual SoCs.
Signed-off-by: Sumit Garg sumit.garg@nxp.com Signed-off-by: Udit Agarwal udit.agarwal@nxp.com
Changes for V2: Modified the subject
This set is applied to fsl-qoriq master, awaiting upstream. Thanks.
York
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