No special reason for the current stack address 0x0ff08000. Change it to 0x00100000 to simplify the init_page_table.

There are two types of SoCs in terms of the load address of SPL.

[1] PH1-sLD3, PH1-LD4, PH1-sLD8 SPL is loaded at 0x00040000-0x0004ffff [2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b SPL is loaded at 0x00100000-0x0010ffff

The new stack area (0x000f8000-0x00100000) should be safe for all the cases.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/init_page_table.S | 5 +---- include/configs/uniphier.h | 2 +- 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S index 2d3ad15..4ed2656 100644 --- a/arch/arm/mach-uniphier/init_page_table.S +++ b/arch/arm/mach-uniphier/init_page_table.S @@ -13,15 +13,12 @@ #define DEVICE 0x00002002 /* Non-shareable Device */ #define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */

-#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT)) -#define STACK_SECTION ((CONFIG_SPL_STACK) >> (SECTION_SHIFT)) - .section ".rodata" .align 14 ENTRY(init_page_table) section = 0 .rept NR_SECTIONS - .if section == 0 || section == 1 || section == STACK_SECTION + .if section == 0 || section == 1 attr = NORMAL .else attr = DEVICE diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 8856044..93e1919 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -252,7 +252,7 @@ #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif

-#define CONFIG_SPL_STACK (0x0ff08000) +#define CONFIG_SPL_STACK (0x00100000) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)

#define CONFIG_PANIC_HANG

This function is for local use in the file.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c index de12953..3769ec5 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c @@ -46,7 +46,7 @@ static struct boot_device_info boot_device_table[] = { {BOOT_DEVICE_NONE, "Reserved"}, };

-int get_boot_mode_sel(void) +static int get_boot_mode_sel(void) { return (readl(SG_PINMON0) >> 1) & 0x1f; }

This is the initial commit for the UniPhier clock drivers. Currently, only the Media I/O clock is supported.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/Kconfig | 1 + drivers/clk/Kconfig | 2 + drivers/clk/Makefile | 1 + drivers/clk/uniphier/Kconfig | 13 +++ drivers/clk/uniphier/Makefile | 3 + drivers/clk/uniphier/clk-uniphier-core.c | 159 +++++++++++++++++++++++++++ drivers/clk/uniphier/clk-uniphier-mio.c | 178 +++++++++++++++++++++++++++++++ drivers/clk/uniphier/clk-uniphier.h | 57 ++++++++++ 8 files changed, 414 insertions(+) create mode 100644 drivers/clk/uniphier/Kconfig create mode 100644 drivers/clk/uniphier/Makefile create mode 100644 drivers/clk/uniphier/clk-uniphier-core.c create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c create mode 100644 drivers/clk/uniphier/clk-uniphier.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d2dbb1a..d8b63e9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -689,6 +689,7 @@ config TARGET_COLIBRI_PXA270

config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" + select CLK_UNIPHIER select CPU_V7 select SUPPORT_SPL select SPL diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 9fcde39..a98b74b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,4 +20,6 @@ config SPL_CLK setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper.

+source "drivers/clk/uniphier/Kconfig" + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c9144e3..c51db15 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o +obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig new file mode 100644 index 0000000..0e90c01 --- /dev/null +++ b/drivers/clk/uniphier/Kconfig @@ -0,0 +1,13 @@ +config CLK_UNIPHIER + bool + select CLK + select SPL_CLK + +menu "Clock drivers for UniPhier SoCs" + depends on CLK_UNIPHIER + +config CLK_UNIPHIER_MIO + bool "Clock driver for UniPhier Media I/O block" + default y + +endmenu diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile new file mode 100644 index 0000000..a3168f9 --- /dev/null +++ b/drivers/clk/uniphier/Makefile @@ -0,0 +1,3 @@ +obj-y += clk-uniphier-core.o + +obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c new file mode 100644 index 0000000..e79e0ff --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mapmem.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <clk.h> +#include <dm/device.h> + +#include "clk-uniphier.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int uniphier_clk_enable(struct udevice *dev, int index) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + struct uniphier_clk_gate_data *gate = priv->socdata->gate; + unsigned int nr_gate = priv->socdata->nr_gate; + void __iomem *reg; + u32 mask, data, tmp; + int i; + + for (i = 0; i < nr_gate; i++) { + if (gate[i].index != index) + continue; + + reg = priv->base + gate[i].reg; + mask = gate[i].mask; + data = gate[i].data & mask; + + tmp = readl(reg); + tmp &= ~mask; + tmp |= data & mask; + debug("%s: %p: %08x\n", __func__, reg, tmp); + writel(tmp, reg); + } + + return 0; +} + +static ulong uniphier_clk_get_rate(struct udevice *dev, int index) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + struct uniphier_clk_rate_data *rdata = priv->socdata->rate; + unsigned int nr_rdata = priv->socdata->nr_rate; + void __iomem *reg; + u32 mask, data; + ulong matched_rate = 0; + int i; + + for (i = 0; i < nr_rdata; i++) { + if (rdata[i].index != index) + continue; + + if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED) + return rdata[i].rate; + + reg = priv->base + rdata[i].reg; + mask = rdata[i].mask; + data = rdata[i].data & mask; + if ((readl(reg) & mask) == data) { + if (matched_rate && rdata[i].rate != matched_rate) { + printf("failed to get clk rate for insane register values\n"); + return -EINVAL; + } + matched_rate = rdata[i].rate; + } + } + + debug("%s: rate = %lu\n", __func__, matched_rate); + + return matched_rate; +} + +static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + struct uniphier_clk_rate_data *rdata = priv->socdata->rate; + unsigned int nr_rdata = priv->socdata->nr_rate; + void __iomem *reg; + u32 mask, data, tmp; + ulong best_rate = 0; + int i; + + /* first, decide the best match rate */ + for (i = 0; i < nr_rdata; i++) { + if (rdata[i].index != index) + continue; + + if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED) + return 0; + + if (rdata[i].rate > best_rate && rdata[i].rate <= rate) + best_rate = rdata[i].rate; + } + + if (!best_rate) + return -ENODEV; + + debug("%s: requested rate = %lu, set rate = %lu\n", __func__, + rate, best_rate); + + /* second, really set registers */ + for (i = 0; i < nr_rdata; i++) { + if (rdata[i].index != index || rdata[i].rate != best_rate) + continue; + + reg = priv->base + rdata[i].reg; + mask = rdata[i].mask; + data = rdata[i].data & mask; + + tmp = readl(reg); + tmp &= ~mask; + tmp |= data; + debug("%s: %p: %08x\n", __func__, reg, tmp); + writel(tmp, reg); + } + + return best_rate; +} + +const struct clk_ops uniphier_clk_ops = { + .enable = uniphier_clk_enable, + .get_periph_rate = uniphier_clk_get_rate, + .set_periph_rate = uniphier_clk_set_rate, +}; + +int uniphier_clk_probe(struct udevice *dev) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", + &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = map_sysmem(addr, size); + if (!priv->base) + return -ENOMEM; + + priv->socdata = (void *)dev_get_driver_data(dev); + + return 0; +} + +int uniphier_clk_remove(struct udevice *dev) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + + unmap_sysmem(priv->base); + + return 0; +} diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c new file mode 100644 index 0000000..d91ae34 --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-mio.c @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <clk.h> +#include <dm/device.h> + +#include "clk-uniphier.h" + +#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \ + { \ + .index = (idx), \ + .reg = 0x20 + 0x200 * (ch), \ + .mask = 0x00000100, \ + .data = 0x00000100, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x110 + 0x200 * (ch), \ + .mask = 0x00000001, \ + .data = 0x00000001, \ + } + +#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00000000, \ + .rate = 44444444, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00010000, \ + .rate = 33333333, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00020000, \ + .rate = 50000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00020000, \ + .rate = 66666666, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001000, \ + .rate = 100000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001100, \ + .rate = 40000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001200, \ + .rate = 25000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001300, \ + .rate = 22222222, \ + } + +#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \ + { \ + .index = (idx), \ + .reg = 0x20 + 0x200 * (ch), \ + .mask = 0x30000000, \ + .data = 0x30000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x110 + 0x200 * (ch), \ + .mask = 0x01000000, \ + .data = 0x01000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x114 + 0x200 * (ch), \ + .mask = 0x00000001, \ + .data = 0x00000001, \ + } + +#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \ + { \ + .index = (idx), \ + .reg = 0x20, \ + .mask = 0x02000000, \ + .data = 0x02000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x110, \ + .mask = 0x00020000, \ + .data = 0x00020000, \ + } + +static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = { + UNIPHIER_MIO_CLK_GATE_SD(0, 0), + UNIPHIER_MIO_CLK_GATE_SD(1, 1), + UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */ + UNIPHIER_MIO_CLK_GATE_USB(0, 3), + UNIPHIER_MIO_CLK_GATE_USB(1, 4), + UNIPHIER_MIO_CLK_GATE_USB(2, 5), + UNIPHIER_MIO_CLK_GATE_DMAC(6), + UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */ +}; + +static struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = { + UNIPHIER_MIO_CLK_RATE_SD(0, 0), + UNIPHIER_MIO_CLK_RATE_SD(1, 1), + UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */ +}; + +static struct uniphier_clk_soc_data uniphier_mio_clk_data = { + .gate = uniphier_mio_clk_gate, + .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate), + .rate = uniphier_mio_clk_rate, + .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate), +}; + +static const struct udevice_id uniphier_mio_clk_match[] = { + { + .compatible = "socionext,ph1-sld3-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-ld4-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-pro4-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-sld8-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-pro5-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,proxstream2-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(uniphier_mio_clk) = { + .name = "uniphier-mio-clk", + .id = UCLASS_CLK, + .of_match = uniphier_mio_clk_match, + .probe = uniphier_clk_probe, + .remove = uniphier_clk_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv), + .ops = &uniphier_clk_ops, +}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h new file mode 100644 index 0000000..560b3f8 --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CLK_UNIPHIER_H__ +#define __CLK_UNIPHIER_H__ + +#include <linux/kernel.h> + +struct uniphier_clk_gate_data { + int index; + unsigned int reg; + u32 mask; + u32 data; +}; + +struct uniphier_clk_rate_data { + int index; + unsigned int reg; +#define UNIPHIER_CLK_RATE_IS_FIXED UINT_MAX + u32 mask; + u32 data; + unsigned long rate; +}; + +struct uniphier_clk_soc_data { + struct uniphier_clk_gate_data *gate; + unsigned int nr_gate; + struct uniphier_clk_rate_data *rate; + unsigned int nr_rate; +}; + +#define UNIPHIER_CLK_FIXED_RATE(i, f) \ + { \ + .index = i, \ + .reg = UNIPHIER_CLK_RATE_IS_FIXED, \ + .rate = f, \ + } + +/** + * struct uniphier_clk_priv - private data for UniPhier clock driver + * + * @base: base address of the clock provider + * @socdata: SoC specific data + */ +struct uniphier_clk_priv { + void __iomem *base; + struct uniphier_clk_soc_data *socdata; +}; + +extern const struct clk_ops uniphier_clk_ops; +int uniphier_clk_probe(struct udevice *dev); +int uniphier_clk_remove(struct udevice *dev); + +#endif /* __CLK_UNIPHIER_H__ */

This is a system control block mainly used for clock and reset control.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/dts/uniphier-common32.dtsi | 8 ++++++++ arch/arm/dts/uniphier-ph1-ld4.dtsi | 4 ++++ arch/arm/dts/uniphier-ph1-pro4.dtsi | 4 ++++ arch/arm/dts/uniphier-ph1-pro5.dtsi | 4 ++++ arch/arm/dts/uniphier-ph1-sld3.dtsi | 8 ++++++++ arch/arm/dts/uniphier-ph1-sld8.dtsi | 4 ++++ arch/arm/dts/uniphier-proxstream2.dtsi | 4 ++++ 7 files changed, 36 insertions(+)

diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index de04de1..d3e5a74 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -101,6 +101,14 @@ reg = <0x5f801000 0xe00>; };

+ sysctrl: sysctrl@61840000 { + /* specify compatible in each SoC DTSI */ + reg = <0x61840000 0x4000>; + #clock-cells = <1>; + clock-names = "ref"; + clocks = <&refclk>; + }; + nand: nand@68000000 { compatible = "denali,denali-nand-dt"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 6f15978..6bd4b91 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -160,3 +160,7 @@ &pinctrl { compatible = "socionext,ph1-ld4-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-ld4-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index a236dbc..984f99c 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -200,3 +200,7 @@ &pinctrl { compatible = "socionext,ph1-pro4-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-pro4-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index 120767c..a836176 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -194,3 +194,7 @@ &pinctrl { compatible = "socionext,ph1-pro5-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-pro5-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index 9ff9584..c7a8902 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -206,6 +206,14 @@ interrupts = <0 83 4>; };

+ sysctrl: sysctrl@f1840000 { + compatible = "socionext,ph1-sld3-sysctrl"; + reg = <0xf1840000 0x4000>; + #clock-cells = <1>; + clock-names = "ref"; + clocks = <&refclk>; + }; + nand: nand@f8000000 { compatible = "denali,denali-nand-dt"; reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index e765a4b..9d97fb0 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -160,3 +160,7 @@ &pinctrl { compatible = "socionext,ph1-sld8-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,ph1-sld8-sysctrl"; +}; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index c7423ff..f6f4bbe 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -205,3 +205,7 @@ &pinctrl { compatible = "socionext,proxstream2-pinctrl", "syscon"; }; + +&sysctrl { + compatible = "socionext,proxstream2-sysctrl"; +};

This block provides clock and reset control for MIO (Media I/O) hardware blocks such as USB2.0, SD card, eMMC, etc.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/dts/uniphier-common32.dtsi | 6 ++++++ arch/arm/dts/uniphier-ph1-ld4.dtsi | 6 ++++++ arch/arm/dts/uniphier-ph1-pro4.dtsi | 6 ++++++ arch/arm/dts/uniphier-ph1-pro5.dtsi | 6 ++++++ arch/arm/dts/uniphier-ph1-sld3.dtsi | 8 ++++++++ arch/arm/dts/uniphier-ph1-sld8.dtsi | 6 ++++++ arch/arm/dts/uniphier-proxstream2.dtsi | 6 ++++++ 7 files changed, 44 insertions(+)

diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index 43e5bea..59511bd 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -74,6 +74,12 @@ reg = <0x58c00000 0x400>, <0x59800000 0x2000>; };

+ mio: mioctrl@59810000 { + /* specify compatible in each SoC DTSI */ + reg = <0x59810000 0x800>; + #clock-cells = <1>; + }; + peri: perictrl@59820000 { /* specify compatible in each SoC DTSI */ reg = <0x59820000 0x200>; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 5843097..628a397 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -157,6 +157,12 @@ clock-frequency = <36864000>; };

+&mio { + compatible = "socionext,ph1-ld4-mioctrl"; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; +}; + &peri { compatible = "socionext,ph1-ld4-perictrl"; clock-names = "uart", "i2c"; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index 0c2f02f..bfffe94 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -197,6 +197,12 @@ clock-frequency = <73728000>; };

+&mio { + compatible = "socionext,ph1-pro4-mioctrl"; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; +}; + &peri { compatible = "socionext,ph1-pro4-perictrl"; clock-names = "uart", "fi2c"; diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index 305114c..087b25a 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -191,6 +191,12 @@ clock-frequency = <73728000>; };

+&mio { + compatible = "socionext,ph1-pro5-mioctrl"; + clock-names = "stdmac"; + clocks = <&sysctrl 10>; +}; + &peri { compatible = "socionext,ph1-pro5-perictrl"; clock-names = "uart", "fi2c"; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index c7a8902..91c9ba5 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -178,6 +178,14 @@ reg = <0x59800000 0x2000>; };

+ mio: mioctrl@59810000 { + compatible = "socionext,ph1-sld3-mioctrl"; + reg = <0x59810000 0x800>; + #clock-cells = <1>; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index 7a26b4a..b9ef401 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -157,6 +157,12 @@ clock-frequency = <80000000>; };

+&mio { + compatible = "socionext,ph1-sld8-mioctrl"; + clock-names = "stdmac", "ehci"; + clocks = <&sysctrl 10>, <&sysctrl 18>; +}; + &peri { compatible = "socionext,ph1-sld8-perictrl"; clock-names = "uart", "i2c"; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index f2faf25..a70b135 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -202,6 +202,12 @@ clock-frequency = <88900000>; };

+&mio { + compatible = "socionext,ph1-pro5-mioctrl"; + clock-names = "stdmac"; + clocks = <&sysctrl 10>; +}; + &peri { compatible = "socionext,proxstream2-perictrl"; clock-names = "uart", "fi2c";

Currently, what this driver does is just to set the base address and reset/clock handling. The latter is cared by the clock driver now. There is nothing special for this EHCI controller.

I want to use the generic-ehci driver rather than bothering to convert this driver to Driver Model.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

drivers/usb/host/Kconfig | 7 ---- drivers/usb/host/Makefile | 1 - drivers/usb/host/ehci-uniphier.c | 75 ---------------------------------------- 3 files changed, 83 deletions(-) delete mode 100644 drivers/usb/host/ehci-uniphier.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 39f7185..9332374 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -74,13 +74,6 @@ config USB_EHCI_MX6 ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs.

-config USB_EHCI_UNIPHIER - bool "Support for UniPhier on-chip EHCI USB controller" - depends on ARCH_UNIPHIER && OF_CONTROL - default y - ---help--- - Enables support for the on-chip EHCI controller on UniPhier SoCs. - config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 6183b80..9a87d2b 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o -obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c deleted file mode 100644 index c3f827c..0000000 --- a/drivers/usb/host/ehci-uniphier.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/err.h> -#include <linux/io.h> -#include <usb.h> -#include <mach/mio-regs.h> -#include <fdtdec.h> -#include "ehci.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define FDT gd->fdt_blob -#define COMPAT "socionext,uniphier-ehci" - -static int get_uniphier_ehci_base(int index, struct ehci_hccr **base) -{ - int offset; - - for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT); - offset >= 0; - offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) { - if (index == 0) { - *base = (struct ehci_hccr *) - fdtdec_get_addr(FDT, offset, "reg"); - return 0; - } - index--; - } - - return -ENODEV; /* not found */ -} - -static void uniphier_ehci_reset(int index, int on) -{ - u32 tmp; - - tmp = readl(MIO_USB_RSTCTRL(index)); - if (on) - tmp &= ~MIO_USB_RSTCTRL_XRST; - else - tmp |= MIO_USB_RSTCTRL_XRST; - writel(tmp, MIO_USB_RSTCTRL(index)); -} - -int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, - struct ehci_hcor **hcor) -{ - int ret; - struct ehci_hccr *cr; - struct ehci_hcor *or; - - uniphier_ehci_reset(index, 0); - - ret = get_uniphier_ehci_base(index, &cr); - if (ret < 0) - return ret; - or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase)); - - *hccr = cr; - *hcor = or; - - return 0; -} - -int ehci_hcd_stop(int index) -{ - uniphier_ehci_reset(index, 1); - - return 0; -}

This generic driver will do for the time being.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/clk/clk-ph1-ld4.c | 4 ++-- arch/arm/mach-uniphier/clk/clk-ph1-pro4.c | 4 ++-- arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c | 2 +- arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c | 2 +- arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c | 2 +- arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c | 2 +- configs/uniphier_ld4_sld8_defconfig | 2 ++ configs/uniphier_sld3_defconfig | 2 ++ 8 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c index 4de9bfb..7a34bee 100644 --- a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c @@ -18,7 +18,7 @@ void ph1_ld4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_RSTCTRL_NRST_ETHER; #endif -#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI tmp |= SC_RSTCTRL_NRST_STDMAC; #endif #ifdef CONFIG_NAND_DENALI @@ -32,7 +32,7 @@ void ph1_ld4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_CLKCTRL_CEN_ETHER; #endif -#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; #endif #ifdef CONFIG_NAND_DENALI diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c index 3df017e..c784c31 100644 --- a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c @@ -22,7 +22,7 @@ void ph1_pro4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_RSTCTRL_NRST_ETHER; #endif -#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI tmp |= SC_RSTCTRL_NRST_STDMAC; #endif #ifdef CONFIG_NAND_DENALI @@ -47,7 +47,7 @@ void ph1_pro4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_CLKCTRL_CEN_ETHER; #endif -#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; #endif #ifdef CONFIG_NAND_DENALI diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c index 8168a63..3c06b30 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c @@ -35,7 +35,7 @@ void ph1_ld4_pin_init(void) sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */ #endif

-#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */ sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c index 23b5f93..d5541a9 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c @@ -40,7 +40,7 @@ void ph1_pro4_pin_init(void) sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */ #endif

-#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */ sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */ sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */ diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c index 6fc0dee..367d9f3 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c @@ -9,7 +9,7 @@

void ph1_sld3_pin_init(void) { -#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI sg_set_pinsel(13, 0, 4, 4); /* USB0OC */ sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */

diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c index a4e3e7a..6763584 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c @@ -33,7 +33,7 @@ void ph1_sld8_pin_init(void) sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */ #endif

-#ifdef CONFIG_USB_EHCI_UNIPHIER +#ifdef CONFIG_USB_EHCI sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */ sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index ee3cbad..535f96f 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -27,5 +27,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_UNIPHIER_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig index 4b871d0..e369c45 100644 --- a/configs/uniphier_sld3_defconfig +++ b/configs/uniphier_sld3_defconfig @@ -22,5 +22,7 @@ CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_SPL_NAND_DENALI=y CONFIG_UNIPHIER_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y