Currently we add the U-Boot specific Ethernet MAC DT nodes for the Pine64 via a board-specific add-on .dtsi. However these nodes and properties in there are actually pretty generic for all A64 boards which use a PHY connected via RGMII. Rename the add-on .dtsi to reflect this and make the Pine64 .dtsi a symlink to this new file. This simplifies letting other boards use the EMAC too.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi | 51 +------------------------ arch/arm/dts/sun50i-a64-rgmii-emac.dtsi | 50 ++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 50 deletions(-) mode change 100644 => 120000 arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi create mode 100644 arch/arm/dts/sun50i-a64-rgmii-emac.dtsi

diff --git a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi deleted file mode 100644 index 9c61bea..0000000 --- a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -/ { - aliases { - ethernet0 = &emac; - }; - - soc { - emac: ethernet@01c30000 { - compatible = "allwinner,sun50i-a64-emac"; - reg = <0x01c30000 0x2000>, <0x01c00030 0x4>; - reg-names = "emac", "syscon"; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "ahb"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "ahb"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy = <&phy1>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - }; - }; -}; - -&pio { - rmii_pins: rmii_pins { - allwinner,pins = "PD10", "PD11", "PD13", "PD14", - "PD17", "PD18", "PD19", "PD20", - "PD22", "PD23"; - allwinner,function = "emac"; - allwinner,drive = <3>; - allwinner,pull = <0>; - }; - - rgmii_pins: rgmii_pins { - allwinner,pins = "PD8", "PD9", "PD10", "PD11", - "PD12", "PD13", "PD15", - "PD16", "PD17", "PD18", "PD19", - "PD20", "PD21", "PD22", "PD23"; - allwinner,function = "emac"; - allwinner,drive = <3>; - allwinner,pull = <0>; - }; -}; diff --git a/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi new file mode 120000 index 0000000..350dc2b --- /dev/null +++ b/arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi @@ -0,0 +1 @@ +sun50i-a64-rgmii-emac.dtsi \ No newline at end of file diff --git a/arch/arm/dts/sun50i-a64-rgmii-emac.dtsi b/arch/arm/dts/sun50i-a64-rgmii-emac.dtsi new file mode 100644 index 0000000..9c61bea --- /dev/null +++ b/arch/arm/dts/sun50i-a64-rgmii-emac.dtsi @@ -0,0 +1,50 @@ +/ { + aliases { + ethernet0 = &emac; + }; + + soc { + emac: ethernet@01c30000 { + compatible = "allwinner,sun50i-a64-emac"; + reg = <0x01c30000 0x2000>, <0x01c00030 0x4>; + reg-names = "emac", "syscon"; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "ahb"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "ahb"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; +}; + +&pio { + rmii_pins: rmii_pins { + allwinner,pins = "PD10", "PD11", "PD13", "PD14", + "PD17", "PD18", "PD19", "PD20", + "PD22", "PD23"; + allwinner,function = "emac"; + allwinner,drive = <3>; + allwinner,pull = <0>; + }; + + rgmii_pins: rgmii_pins { + allwinner,pins = "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23"; + allwinner,function = "emac"; + allwinner,drive = <3>; + allwinner,pull = <0>; + }; +};

Both the BananaPi-M64 and the OrangePi-Win use the same Gigabit Ethernet configuration as the Pine64. Use the new generic add-on .dtsi file and have symlinks for each board to enable TFTP boot on these boards.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/dts/sun50i-a64-bananapi-m64-u-boot.dtsi | 1 + arch/arm/dts/sun50i-a64-orangepi-win-u-boot.dtsi | 1 + 2 files changed, 2 insertions(+) create mode 120000 arch/arm/dts/sun50i-a64-bananapi-m64-u-boot.dtsi create mode 120000 arch/arm/dts/sun50i-a64-orangepi-win-u-boot.dtsi

diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64-u-boot.dtsi b/arch/arm/dts/sun50i-a64-bananapi-m64-u-boot.dtsi new file mode 120000 index 0000000..350dc2b --- /dev/null +++ b/arch/arm/dts/sun50i-a64-bananapi-m64-u-boot.dtsi @@ -0,0 +1 @@ +sun50i-a64-rgmii-emac.dtsi \ No newline at end of file diff --git a/arch/arm/dts/sun50i-a64-orangepi-win-u-boot.dtsi b/arch/arm/dts/sun50i-a64-orangepi-win-u-boot.dtsi new file mode 120000 index 0000000..350dc2b --- /dev/null +++ b/arch/arm/dts/sun50i-a64-orangepi-win-u-boot.dtsi @@ -0,0 +1 @@ +sun50i-a64-rgmii-emac.dtsi \ No newline at end of file

Instead of hard-coding GPIO pins used for a certain peripheral, we should just use the pinctrl information from the DT. The sun8i-emac driver has some simple implementation of that, so let's just generalize this and copy the code to a more common location. On the way we add support for the new, generic pinctrl binding now used by all Allwinner SoCs.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- arch/arm/include/asm/arch-sunxi/gpio.h | 3 ++ arch/arm/mach-sunxi/pinmux.c | 79 ++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 24f8520..b5a4b32 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -240,4 +240,7 @@ int axp_gpio_init(void); static inline int axp_gpio_init(void) { return 0; } #endif

+int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node, + int mux_sel); + #endif /* _SUNXI_GPIO_H */ diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c index b026f78..ae36fe9 100644 --- a/arch/arm/mach-sunxi/pinmux.c +++ b/arch/arm/mach-sunxi/pinmux.c @@ -9,6 +9,9 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/gpio.h> +#include <fdtdec.h> +#include <fdt_support.h> +#include <dt-bindings/pinctrl/sun4i-a10.h>

void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) { @@ -69,3 +72,79 @@ int sunxi_gpio_set_pull(u32 pin, u32 val)

return 0; } + +static int sunxi_gpio_setup_single_node(const void * volatile fdt_blob, + int offset, int mux_sel) +{ + int drive, pull, pin, i; + const char *pin_name; + + drive = fdt_getprop_u32_default_node(fdt_blob, offset, 0, + "drive-strength", ~0); + if (drive != ~0) { + if (drive <= 10) + drive = SUN4I_PINCTRL_10_MA; + else if (drive <= 20) + drive = SUN4I_PINCTRL_20_MA; + else if (drive <= 30) + drive = SUN4I_PINCTRL_30_MA; + else + drive = SUN4I_PINCTRL_40_MA; + } else { + drive = fdt_getprop_u32_default_node(fdt_blob, offset, 0, + "allwinner,drive", ~0); + } + + if (fdt_get_property(fdt_blob, offset, "bias-pull-up", NULL)) + pull = SUN4I_PINCTRL_PULL_UP; + else if (fdt_get_property(fdt_blob, offset, "bias-disable", NULL)) + pull = SUN4I_PINCTRL_NO_PULL; + else if (fdt_get_property(fdt_blob, offset, "bias-pull-down", NULL)) + pull = SUN4I_PINCTRL_PULL_DOWN; + else + pull = fdt_getprop_u32_default_node(fdt_blob, offset, 0, + "allwinner,pull", ~0); + + for (i = 0; ; i++) { + pin_name = fdt_stringlist_get(fdt_blob, offset, + "allwinner,pins", i, NULL); + if (!pin_name) { + pin_name = fdt_stringlist_get(fdt_blob, offset, + "pins", i, NULL); + if (!pin_name) + break; + } + pin = sunxi_name_to_gpio(pin_name); + if (pin < 0) + continue; + + sunxi_gpio_set_cfgpin(pin, mux_sel); + if (drive != ~0) + sunxi_gpio_set_drv(pin, drive); + if (pull != ~0) + sunxi_gpio_set_pull(pin, pull); + } + + return i; +} + +int sunxi_gpio_setup_dt_pins(const void * volatile fdt_blob, int node, + int mux_sel) +{ + int offset, pins = 0, idx; + + for (idx = 0; ; idx++) { + offset = fdtdec_lookup_phandle_index(fdt_blob, node, + "pinctrl-0", idx); + if (offset < 0) { + if (idx == 0) + return offset; + + return pins; + } + + pins += sunxi_gpio_setup_single_node(fdt_blob, offset, mux_sel); + } + + return pins; +}

The Ethernet MAC used in newer Allwinner SoCs (H3, A64, H5) is about to get an upstream Linux driver very soon (it's already lurking in -next). This one uses a slightly different binding from the original one used by the U-Boot driver. The differences to the old binding are: - The "syscon" address is held in a separate node, referenced via a phandle in the "syscon" property. - The reference to the PHY is held in a property called "phy-handle", not "phy". - The PHY register is at offset 0x30 in the syscon device, not at 0. - The internal PHY is activated when a capable SoC selects MII mode.

Teach the U-Boot driver how to find its resources in a "new-style" DT, so that we can use a Linux kernel compatible DT for U-Boot as well. This keeps support for the old binding (for now?), to allow a smooth transition.

Signed-off-by: Andre Przywara andre.przywara@arm.com --- drivers/net/sun8i_emac.c | 51 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 44 insertions(+), 7 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index af77134..8320518 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -278,7 +278,7 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) int ret; u32 reg;

- reg = readl(priv->sysctl_reg); + reg = readl(priv->sysctl_reg + 0x30);

if (priv->variant == H3_EMAC) { ret = sun8i_emac_set_syscon_ephy(priv, &reg); @@ -309,7 +309,7 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) return -EINVAL; }

- writel(reg, priv->sysctl_reg); + writel(reg, priv->sysctl_reg + 0x30);

return 0; } @@ -733,17 +733,50 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) #endif

pdata->iobase = devfdt_get_addr_name(dev, "emac"); + if (pdata->iobase == FDT_ADDR_T_NONE) + pdata->iobase = devfdt_get_addr(dev); + if (pdata->iobase == FDT_ADDR_T_NONE) { + debug("%s: Cannot find MAC base address\n", __func__); + return -EINVAL; + } + priv->sysctl_reg = devfdt_get_addr_name(dev, "syscon"); + if (priv->sysctl_reg == FDT_ADDR_T_NONE) { + const fdt32_t *reg; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); + if (offset < 0) { + debug("%s: cannot find syscon node\n", __func__); + return -EINVAL; + } + reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); + if (!reg) { + debug("%s: cannot find reg property in syscon node\n", + __func__); + return -EINVAL; + } + priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + } else + priv->sysctl_reg -= 0x30; + if (priv->sysctl_reg == FDT_ADDR_T_NONE) { + debug("%s: Cannot find syscon base address\n", __func__); + return -EINVAL; + }

pdata->phy_interface = -1; priv->phyaddr = -1; priv->use_internal_phy = false;

- offset = fdtdec_lookup_phandle(gd->fdt_blob, node, - "phy"); - if (offset > 0) - priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", - -1); + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy"); + if (offset < 0) + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, + "phy-handle"); + if (offset < 0) { + debug("%s: Cannot find PHY address\n", __func__); + return -EINVAL; + } + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);

phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);

@@ -768,6 +801,10 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) if (fdt_getprop(gd->fdt_blob, node, "allwinner,use-internal-phy", NULL)) priv->use_internal_phy = true; + else { + if (pdata->phy_interface == PHY_INTERFACE_MODE_MII) + priv->use_internal_phy = true; + } }

priv->interface = pdata->phy_interface;