[U-Boot] [PATCH v2 00/16] stm32m1 patches for v2019.10
Some remaining patches for stm32mp1 - some cleanup in files - add 2 specific commands for stm32mp1 board - use OF_SYSTEM_SETUP to update kernel device tree - synchronization with latest device tree
Changes in v2: - missing alignment on ethernet@5800a000 - set ethernet0 phy-mode to "rgmii-id" for dk1 (needed modification not yet upstreamed)
Patrick Delaunay (16): stm32mp1: deactivate WATCHDOG in defconfig stm32mp1: call regulators_enable_boot_on in board_init stm32mp1: syscon: remove etzpc support stm32mp1: syscon: remove stgen dt-bindings: pinctrl: stm32: add new entry for package information stm32mp1: export get_cpu_package function stm32mp1: update package information in device tree stm32mp1: update device tree with ETZPC status stm32mp1: add stboard command stm32mp1: key: add stm32key command stm32mp1: update README stm32mp1: cosmetic: remove unnecessary include stm32mp1: configs: Add CONFIG_OF_SPL_REMOVE_PROPS stm32mp1: add check for presence of environment in boot device stm32mp1: force boot_net_usb_start ARM: dts: stm32mp1: sync device tree with v5.2-rc4
arch/arm/Kconfig | 1 + arch/arm/dts/stm32mp15-ddr.dtsi | 2 +- arch/arm/dts/stm32mp157-pinctrl.dtsi | 270 ++++++++++++++++++++- arch/arm/dts/stm32mp157-u-boot.dtsi | 67 ++--- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 4 - arch/arm/dts/stm32mp157a-dk1.dts | 32 ++- arch/arm/dts/stm32mp157c-dk2.dts | 1 + arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 15 +- arch/arm/dts/stm32mp157c-ed1.dts | 205 ++++------------ arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 3 - arch/arm/dts/stm32mp157c-ev1.dts | 12 +- arch/arm/dts/stm32mp157c.dtsi | 215 +++++++++++----- arch/arm/mach-stm32mp/Kconfig | 15 ++ arch/arm/mach-stm32mp/Makefile | 2 + arch/arm/mach-stm32mp/cmd_stm32key.c | 101 ++++++++ arch/arm/mach-stm32mp/cpu.c | 7 +- arch/arm/mach-stm32mp/fdt.c | 223 +++++++++++++++++ arch/arm/mach-stm32mp/include/mach/stm32.h | 3 +- arch/arm/mach-stm32mp/include/mach/sys_proto.h | 9 + arch/arm/mach-stm32mp/syscon.c | 2 - board/st/stm32mp1/Kconfig | 7 + board/st/stm32mp1/Makefile | 1 + board/st/stm32mp1/README | 15 +- board/st/stm32mp1/cmd_stboard.c | 145 +++++++++++ board/st/stm32mp1/spl.c | 1 - board/st/stm32mp1/stm32mp1.c | 4 + configs/stm32mp15_basic_defconfig | 3 +- configs/stm32mp15_trusted_defconfig | 2 - .../pinctrl/st,stm32-pinctrl.txt | 101 +++++++- drivers/clk/clk_stm32mp1.c | 3 +- include/configs/stm32mp1.h | 7 +- include/dt-bindings/pinctrl/stm32-pinfunc.h | 6 + 32 files changed, 1165 insertions(+), 319 deletions(-) create mode 100644 arch/arm/mach-stm32mp/cmd_stm32key.c create mode 100644 arch/arm/mach-stm32mp/fdt.c create mode 100644 board/st/stm32mp1/cmd_stboard.c
Deactivate WATCHDOG by default in u-boot to avoid issue to boot kernel and rootfs without the needed daemon to reload it.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
configs/stm32mp15_basic_defconfig | 2 -- configs/stm32mp15_trusted_defconfig | 2 -- 2 files changed, 4 deletions(-)
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 4aa184f..b1fc3a2 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -110,5 +110,3 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_WDT=y -CONFIG_WDT_STM32MP=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 5fe9477..ae9bc76 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -100,5 +100,3 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_WDT=y -CONFIG_WDT_STM32MP=y
Le 05/07/2019 à 17:20, Patrick Delaunay a écrit :
Deactivate WATCHDOG by default in u-boot to avoid issue to boot kernel and rootfs without the needed daemon to reload it.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
configs/stm32mp15_basic_defconfig | 2 -- configs/stm32mp15_trusted_defconfig | 2 -- 2 files changed, 4 deletions(-)
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 4aa184f..b1fc3a2 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -110,5 +110,3 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_WDT=y -CONFIG_WDT_STM32MP=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 5fe9477..ae9bc76 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -100,5 +100,3 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_WDT=y -CONFIG_WDT_STM32MP=y
Tested-by: Pierre-Jean Texier pjtexier@koncepto.io
Regards,
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Deactivate WATCHDOG by default in u-boot to avoid issue to boot kernel and rootfs without the needed daemon to reload it.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
configs/stm32mp15_basic_defconfig | 2 -- configs/stm32mp15_trusted_defconfig | 2 -- 2 files changed, 4 deletions(-)
Applied to u-boot-stm32/master, thanks!
Patrick
-- 2.7.4
U-Boot activates regulators by reading the "regulator-boot-on" property in DT; it is requested by M4 early Boot feature.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
board/st/stm32mp1/stm32mp1.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 7769293..e4d1723 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -515,6 +515,10 @@ int board_init(void)
board_key_check();
+#ifdef CONFIG_DM_REGULATOR + regulators_enable_boot_on(_DEBUG); +#endif + sysconf_init();
if (IS_ENABLED(CONFIG_LED))
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
U-Boot activates regulators by reading the "regulator-boot-on" property in DT; it is requested by M4 early Boot feature.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
board/st/stm32mp1/stm32mp1.c | 4 ++++ 1 file changed, 4 insertions(+)
Applied to u-boot-stm32/master, thanks!
Patrick
Support for ETZPC is removed as this device is not present in Linux kernel device tree.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
arch/arm/mach-stm32mp/include/mach/stm32.h | 1 - arch/arm/mach-stm32mp/syscon.c | 1 - 2 files changed, 2 deletions(-)
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 6795352..1e3299a 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -36,7 +36,6 @@ /* enumerated used to identify the SYSCON driver instance */ enum { STM32MP_SYSCON_UNKNOWN, - STM32MP_SYSCON_ETZPC, STM32MP_SYSCON_PWR, STM32MP_SYSCON_STGEN, STM32MP_SYSCON_SYSCFG, diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index 242f834..e10c42e 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -9,7 +9,6 @@ #include <asm/arch/stm32.h>
static const struct udevice_id stm32mp_syscon_ids[] = { - { .compatible = "st,stm32mp1-etzpc", .data = STM32MP_SYSCON_ETZPC }, { .compatible = "st,stm32mp1-pwr", .data = STM32MP_SYSCON_PWR }, { .compatible = "st,stm32-stgen", .data = STM32MP_SYSCON_STGEN }, { .compatible = "st,stm32mp157-syscfg",
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Support for ETZPC is removed as this device is not present in Linux kernel device tree.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
arch/arm/mach-stm32mp/include/mach/stm32.h | 1 - arch/arm/mach-stm32mp/syscon.c | 1 - 2 files changed, 2 deletions(-)
Applied to u-boot-stm32/master, thanks!
Patrick
Reduce difference with kernel Linux device tree.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
arch/arm/dts/stm32mp157-u-boot.dtsi | 7 ------- arch/arm/mach-stm32mp/include/mach/stm32.h | 2 +- arch/arm/mach-stm32mp/syscon.c | 1 - drivers/clk/clk_stm32mp1.c | 3 +-- 4 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi index 09560e2..c9f534e 100644 --- a/arch/arm/dts/stm32mp157-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157-u-boot.dtsi @@ -31,13 +31,6 @@
soc { u-boot,dm-pre-reloc; - - stgen: stgen@5C008000 { - compatible = "st,stm32-stgen"; - reg = <0x5C008000 0x1000>; - status = "okay"; - u-boot,dm-pre-reloc; - }; }; };
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 1e3299a..1d4b548 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -15,6 +15,7 @@ #define STM32_DBGMCU_BASE 0x50081000 #define STM32_TZC_BASE 0x5C006000 #define STM32_ETZPC_BASE 0x5C007000 +#define STM32_STGEN_BASE 0x5C008000 #define STM32_TAMP_BASE 0x5C00A000
#define STM32_USART1_BASE 0x5C000000 @@ -37,7 +38,6 @@ enum { STM32MP_SYSCON_UNKNOWN, STM32MP_SYSCON_PWR, - STM32MP_SYSCON_STGEN, STM32MP_SYSCON_SYSCFG, };
diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index e10c42e..6070837 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -10,7 +10,6 @@
static const struct udevice_id stm32mp_syscon_ids[] = { { .compatible = "st,stm32mp1-pwr", .data = STM32MP_SYSCON_PWR }, - { .compatible = "st,stm32-stgen", .data = STM32MP_SYSCON_STGEN }, { .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG }, { } diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index f295e48..5f15853 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -1542,8 +1542,7 @@ static void stgen_config(struct stm32mp1_clk_priv *priv) u32 stgenc, cntfid0; ulong rate;
- stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN); - + stgenc = STM32_STGEN_BASE; cntfid0 = readl(stgenc + STGENC_CNTFID0); p = stm32mp1_clk_get_parent(priv, STGEN_K); rate = stm32mp1_clk_get(priv, p);
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Reduce difference with kernel Linux device tree.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
arch/arm/dts/stm32mp157-u-boot.dtsi | 7 ------- arch/arm/mach-stm32mp/include/mach/stm32.h | 2 +- arch/arm/mach-stm32mp/syscon.c | 1 - drivers/clk/clk_stm32mp1.c | 3 +-- 4 files changed, 2 insertions(+), 11 deletions(-)
Applied to u-boot-stm32/master, thanks!
Patrick
Add "st,package" entry. Possibles values are: -STM32MP_PKG_AA for LFBGA448 (18*18) package -STM32MP_PKG_AB for LFBGA354 (16*16) package -STM32MP_PKG_AC for TFBGA361 (12*12) package -STM32MP_PKG_AD for TFBGA257 (10*10) package
see Linux commit 966d9b928f626a54a0c27c0fdae1e3dfe9bab416 for v5.2-rc1
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
.../pinctrl/st,stm32-pinctrl.txt | 101 ++++++++++++++++++--- include/dt-bindings/pinctrl/stm32-pinfunc.h | 6 ++ 2 files changed, 94 insertions(+), 13 deletions(-)
diff --git a/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt b/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt index c41ae91..0016925 100644 --- a/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt +++ b/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt @@ -8,8 +8,13 @@ controllers onto these pads. Pin controller node: Required properies: - compatible: value should be one of the following: - (a) "st,stm32f429-pinctrl" - (b) "st,stm32f746-pinctrl" + "st,stm32f429-pinctrl" + "st,stm32f469-pinctrl" + "st,stm32f746-pinctrl" + "st,stm32f769-pinctrl" + "st,stm32h743-pinctrl" + "st,stm32mp157-pinctrl" + "st,stm32mp157-z-pinctrl" - #address-cells: The value of this property must be 1 - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to @@ -32,13 +37,30 @@ Required properties:
Optional properties: - reset: : Reference to the reset controller - - interrupt-parent: phandle of the interrupt parent to which the external - GPIO interrupts are forwarded to. - - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node - which includes IRQ mux selection register, and the offset of the IRQ mux - selection register. + - st,syscfg: Should be phandle/offset/mask. + -The phandle to the syscon node which includes IRQ mux selection register. + -The offset of the IRQ mux selection register + -The field mask of IRQ mux, needed if different of 0xf. + - gpio-ranges: Define a dedicated mapping between a pin-controller and + a gpio controller. Format is <&phandle a b c> with: + -(phandle): phandle of pin-controller. + -(a): gpio base offset in range. + -(b): pin base offset in range. + -(c): gpio count in range + This entry has to be used either if there are holes inside a bank: + GPIOB0/B1/B2/B14/B15 (see example 2) + or if banks are not contiguous: + GPIOA/B/C/E... + NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller + have to use a "gpio-ranges" entry. + More details in Documentation/devicetree/bindings/gpio/gpio.txt. + - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line + used to select GPIOs as interrupts). + - hwlocks: reference to a phandle of a hardware spinlock provider node. + - st,package: Indicates the SOC package used. + More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
-Example: +Example 1: #include <dt-bindings/pinctrl/stm32f429-pinfunc.h> ...
@@ -60,6 +82,43 @@ Example: pin-functions nodes follow... };
+Example 2: +#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +... + + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOA"; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOB"; + ngpios = 4; + gpio-ranges = <&pinctrl 0 16 3>, + <&pinctrl 14 30 2>; + }; + + + ... + pin-functions nodes follow... + }; + + Contents of function subnode node: ---------------------------------- Subnode format @@ -83,14 +142,31 @@ Required properties: - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) - function: The function number, can be: - * 0 : GPIO IN + * 0 : GPIO * 1 : Alternate Function 0 * 2 : Alternate Function 1 * 3 : Alternate Function 2 * ... * 16 : Alternate Function 15 * 17 : Analog - * 18 : GPIO OUT + + To simplify the usage, macro is available to generate "pinmux" field. + This macro is available here: + - include/dt-bindings/pinctrl/stm32-pinfunc.h + + Some examples of using macro: + /* GPIO A9 set as alernate function 2 */ + ... { + pinmux = <STM32_PINMUX('A', 9, AF2)>; + }; + /* GPIO A9 set as GPIO */ + ... { + pinmux = <STM32_PINMUX('A', 9, GPIO)>; + }; + /* GPIO A9 set as analog */ + ... { + pinmux = <STM32_PINMUX('A', 9, ANALOG)>; + };
Optional properties: - GENERIC_PINCONFIG: is the generic pinconfig options to use. @@ -114,13 +190,13 @@ pin-controller { ... usart1_pins_a: usart1@0 { pins1 { - pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('A', 9, AF7)>; bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('A', 10, AF7)>; bias-disable; }; }; @@ -129,5 +205,4 @@ pin-controller { &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; - status = "okay"; }; diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index b5a2174..e6fb8ad 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -32,5 +32,11 @@
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
+/* package information */ +#define STM32MP_PKG_AA 0x1 +#define STM32MP_PKG_AB 0x2 +#define STM32MP_PKG_AC 0x4 +#define STM32MP_PKG_AD 0x8 + #endif /* _DT_BINDINGS_STM32_PINFUNC_H */
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com
Add "st,package" entry. Possibles values are: -STM32MP_PKG_AA for LFBGA448 (18*18) package -STM32MP_PKG_AB for LFBGA354 (16*16) package -STM32MP_PKG_AC for TFBGA361 (12*12) package -STM32MP_PKG_AD for TFBGA257 (10*10) package
see Linux commit 966d9b928f626a54a0c27c0fdae1e3dfe9bab416 for v5.2-rc1
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
.../pinctrl/st,stm32-pinctrl.txt | 101 ++++++++++++++++++--- include/dt-bindings/pinctrl/stm32-pinfunc.h | 6 ++ 2 files changed, 94 insertions(+), 13 deletions(-)
Applied to u-boot-stm32/master, thanks!
Patrick
Prepare update of package information update in Linux device tree.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
arch/arm/mach-stm32mp/cpu.c | 7 +------ arch/arm/mach-stm32mp/include/mach/sys_proto.h | 9 +++++++++ 2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index e1a0a13..d4f2ea8 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -78,11 +78,6 @@ #define PKG_SHIFT 27 #define PKG_MASK GENMASK(2, 0)
-#define PKG_AA_LBGA448 4 -#define PKG_AB_LBGA354 3 -#define PKG_AC_TFBGA361 2 -#define PKG_AD_TFBGA257 1 - #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) #ifndef CONFIG_STM32MP1_TRUSTED static void security_init(void) @@ -277,7 +272,7 @@ u32 get_cpu_type(void) }
/* Get Package options from OTP */ -static u32 get_cpu_package(void) +u32 get_cpu_package(void) { return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); } diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 71a3ba7..99eefab 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -19,5 +19,14 @@ u32 get_cpu_type(void);
/* return CPU_REV constants */ u32 get_cpu_rev(void); + +/* Get Package options from OTP */ +u32 get_cpu_package(void); + +#define PKG_AA_LBGA448 4 +#define PKG_AB_LBGA354 3 +#define PKG_AC_TFBGA361 2 +#define PKG_AD_TFBGA257 1 + /* return boot mode */ u32 get_bootmode(void);
Hi,
To: u-boot@lists.denx.de Cc: Patrick DELAUNAY patrick.delaunay@st.com; U-Boot STM32 <uboot- stm32@st-md-mailman.stormreply.com>; Patrice CHOTARD patrice.chotard@st.com; Albert Aribaud albert.u.boot@aribaud.net Subject: [PATCH v2 06/16] stm32mp1: export get_cpu_package function Importance: High
Prepare update of package information update in Linux device tree.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
arch/arm/mach-stm32mp/cpu.c | 7 +------ arch/arm/mach-stm32mp/include/mach/sys_proto.h | 9 +++++++++ 2 files changed, 10 insertions(+), 6 deletions(-)
Applied to u-boot-stm32/master, thanks!
Patrick
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
arch/arm/Kconfig | 1 + arch/arm/mach-stm32mp/Makefile | 1 + arch/arm/mach-stm32mp/fdt.c | 45 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+) create mode 100644 arch/arm/mach-stm32mp/fdt.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f5a7630..6f9c201 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1488,6 +1488,7 @@ config ARCH_STM32MP select MISC select OF_CONTROL select OF_LIBFDT + select OF_SYSTEM_SETUP select PINCTRL select REGMAP select SUPPORT_SPL diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index 1493914..e59bd81 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -17,3 +17,4 @@ endif endif obj-$(CONFIG_ARMV7_PSCI) += psci.o obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c new file mode 100644 index 0000000..c635353 --- /dev/null +++ b/arch/arm/mach-stm32mp/fdt.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#include <common.h> +#include <fdt_support.h> +#include <asm/arch/sys_proto.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, bd_t *bd) +{ + int ret = 0; + u32 pkg; + + switch (get_cpu_package()) { + case PKG_AA_LBGA448: + pkg = STM32MP_PKG_AA; + break; + case PKG_AB_LBGA354: + pkg = STM32MP_PKG_AB; + break; + case PKG_AC_TFBGA361: + pkg = STM32MP_PKG_AC; + break; + case PKG_AD_TFBGA257: + pkg = STM32MP_PKG_AD; + break; + default: + pkg = 0; + break; + } + if (pkg) { + do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl", + "st,package", pkg, false); + do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl", + "st,package", pkg, false); + } + + return ret; +}
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
arch/arm/Kconfig | 1 + arch/arm/mach-stm32mp/Makefile | 1 + arch/arm/mach-stm32mp/fdt.c | 45 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+) create mode 100644 arch/arm/mach-stm32mp/fdt.c
Applied to u-boot-stm32/master, thanks!
Patrick
U-Boot should disable nodes in device tree if needed according ETZPC status in ft_system_setup().
ETZPC itself use an array on addresses to do the match between the status bits and the node.
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
arch/arm/mach-stm32mp/Kconfig | 7 ++ arch/arm/mach-stm32mp/fdt.c | 178 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 185 insertions(+)
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index d9ad6b4..9c5c93c 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -83,6 +83,13 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 Partition on the second MMC to load U-Boot from when the MMC is being used in raw mode
+config STM32_ETZPC + bool "STM32 Extended TrustZone Protection" + depends on TARGET_STM32MP1 + default y + help + Say y to enable STM32 Extended TrustZone Protection + config BOOTSTAGE_STASH_ADDR default 0xC3000000
diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index c635353..82c430b 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -7,6 +7,178 @@ #include <fdt_support.h> #include <asm/arch/sys_proto.h> #include <dt-bindings/pinctrl/stm32-pinfunc.h> +#include <linux/io.h> + +#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n)) +#define ETZPC_DECPROT_NB 6 + +#define DECPROT_MASK 0x03 +#define NB_PROT_PER_REG 0x10 +#define DECPROT_NB_BITS 2 + +#define DECPROT_SECURED 0x00 +#define DECPROT_WRITE_SECURE 0x01 +#define DECPROT_MCU_ISOLATION 0x02 +#define DECPROT_NON_SECURED 0x03 + +#define ETZPC_RESERVED 0xffffffff + +static const u32 stm32mp1_ip_addr[] = { + 0x5c008000, /* 00 stgenc */ + 0x54000000, /* 01 bkpsram */ + 0x5c003000, /* 02 iwdg1 */ + 0x5c000000, /* 03 usart1 */ + 0x5c001000, /* 04 spi6 */ + 0x5c002000, /* 05 i2c4 */ + ETZPC_RESERVED, /* 06 reserved */ + 0x54003000, /* 07 rng1 */ + 0x54002000, /* 08 hash1 */ + 0x54001000, /* 09 cryp1 */ + 0x5a003000, /* 0A ddrctrl */ + 0x5a004000, /* 0B ddrphyc */ + 0x5c009000, /* 0C i2c6 */ + ETZPC_RESERVED, /* 0D reserved */ + ETZPC_RESERVED, /* 0E reserved */ + ETZPC_RESERVED, /* 0F reserved */ + 0x40000000, /* 10 tim2 */ + 0x40001000, /* 11 tim3 */ + 0x40002000, /* 12 tim4 */ + 0x40003000, /* 13 tim5 */ + 0x40004000, /* 14 tim6 */ + 0x40005000, /* 15 tim7 */ + 0x40006000, /* 16 tim12 */ + 0x40007000, /* 17 tim13 */ + 0x40008000, /* 18 tim14 */ + 0x40009000, /* 19 lptim1 */ + 0x4000a000, /* 1A wwdg1 */ + 0x4000b000, /* 1B spi2 */ + 0x4000c000, /* 1C spi3 */ + 0x4000d000, /* 1D spdifrx */ + 0x4000e000, /* 1E usart2 */ + 0x4000f000, /* 1F usart3 */ + 0x40010000, /* 20 uart4 */ + 0x40011000, /* 21 uart5 */ + 0x40012000, /* 22 i2c1 */ + 0x40013000, /* 23 i2c2 */ + 0x40014000, /* 24 i2c3 */ + 0x40015000, /* 25 i2c5 */ + 0x40016000, /* 26 cec */ + 0x40017000, /* 27 dac */ + 0x40018000, /* 28 uart7 */ + 0x40019000, /* 29 uart8 */ + ETZPC_RESERVED, /* 2A reserved */ + ETZPC_RESERVED, /* 2B reserved */ + 0x4001c000, /* 2C mdios */ + ETZPC_RESERVED, /* 2D reserved */ + ETZPC_RESERVED, /* 2E reserved */ + ETZPC_RESERVED, /* 2F reserved */ + 0x44000000, /* 30 tim1 */ + 0x44001000, /* 31 tim8 */ + ETZPC_RESERVED, /* 32 reserved */ + 0x44003000, /* 33 usart6 */ + 0x44004000, /* 34 spi1 */ + 0x44005000, /* 35 spi4 */ + 0x44006000, /* 36 tim15 */ + 0x44007000, /* 37 tim16 */ + 0x44008000, /* 38 tim17 */ + 0x44009000, /* 39 spi5 */ + 0x4400a000, /* 3A sai1 */ + 0x4400b000, /* 3B sai2 */ + 0x4400c000, /* 3C sai3 */ + 0x4400d000, /* 3D dfsdm */ + 0x4400e000, /* 3E tt_fdcan */ + ETZPC_RESERVED, /* 3F reserved */ + 0x50021000, /* 40 lptim2 */ + 0x50022000, /* 41 lptim3 */ + 0x50023000, /* 42 lptim4 */ + 0x50024000, /* 43 lptim5 */ + 0x50027000, /* 44 sai4 */ + 0x50025000, /* 45 vrefbuf */ + 0x4c006000, /* 46 dcmi */ + 0x4c004000, /* 47 crc2 */ + 0x48003000, /* 48 adc */ + 0x4c002000, /* 49 hash2 */ + 0x4c003000, /* 4A rng2 */ + 0x4c005000, /* 4B cryp2 */ + ETZPC_RESERVED, /* 4C reserved */ + ETZPC_RESERVED, /* 4D reserved */ + ETZPC_RESERVED, /* 4E reserved */ + ETZPC_RESERVED, /* 4F reserved */ + ETZPC_RESERVED, /* 50 sram1 */ + ETZPC_RESERVED, /* 51 sram2 */ + ETZPC_RESERVED, /* 52 sram3 */ + ETZPC_RESERVED, /* 53 sram4 */ + ETZPC_RESERVED, /* 54 retram */ + 0x49000000, /* 55 otg */ + 0x48004000, /* 56 sdmmc3 */ + 0x48005000, /* 57 dlybsd3 */ + 0x48000000, /* 58 dma1 */ + 0x48001000, /* 59 dma2 */ + 0x48002000, /* 5A dmamux */ + 0x58002000, /* 5B fmc */ + 0x58003000, /* 5C qspi */ + 0x58004000, /* 5D dlybq */ + 0x5800a000, /* 5E eth */ + ETZPC_RESERVED, /* 5F reserved */ +}; + +/* fdt helper */ +static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr) +{ + int node; + + for (node = fdt_first_subnode(fdt, offset); + node >= 0; + node = fdt_next_subnode(fdt, node)) { + if (addr == (u32)fdt_getprop(fdt, node, "reg", 0)) { + if (fdtdec_get_is_enabled(fdt, node)) { + fdt_status_disabled(fdt, node); + + return true; + } + return false; + } + } + + return false; +} + +static int stm32_fdt_fixup_etzpc(void *fdt) +{ + const u32 *array; + int array_size, i; + int soc_node, offset, shift; + u32 addr, status, decprot[ETZPC_DECPROT_NB]; + + array = stm32mp1_ip_addr; + array_size = ARRAY_SIZE(stm32mp1_ip_addr); + + for (i = 0; i < ETZPC_DECPROT_NB; i++) + decprot[i] = readl(ETZPC_DECPROT(i)); + + soc_node = fdt_path_offset(fdt, "/soc"); + if (soc_node < 0) + return soc_node; + + for (i = 0; i < array_size; i++) { + offset = i / NB_PROT_PER_REG; + shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS; + status = (decprot[offset] >> shift) & DECPROT_MASK; + addr = array[i]; + + debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status); + + if (addr == ETZPC_RESERVED || + status == DECPROT_NON_SECURED) + continue; + + if (fdt_disable_subnode_by_address(fdt, soc_node, addr)) + printf("ETZPC: 0x%08x node disabled, decprot %d=%d\n", + addr, i, status); + } + + return 0; +}
/* * This function is called right before the kernel is booted. "blob" is the @@ -17,6 +189,12 @@ int ft_system_setup(void *blob, bd_t *bd) int ret = 0; u32 pkg;
+ if (CONFIG_IS_ENABLED(STM32_ETZPC)) { + ret = stm32_fdt_fixup_etzpc(blob); + if (ret) + return ret; + } + switch (get_cpu_package()) { case PKG_AA_LBGA448: pkg = STM32MP_PKG_AA;
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
U-Boot should disable nodes in device tree if needed according ETZPC status in ft_system_setup().
ETZPC itself use an array on addresses to do the match between the status bits and the node.
Signed-off-by: Benjamin Gaignard benjamin.gaignard@st.com Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
arch/arm/mach-stm32mp/Kconfig | 7 ++ arch/arm/mach-stm32mp/fdt.c | 178 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 185 insertions(+)
Applied to u-boot-stm32/master, thanks!
Patrick
Allow to update board identification in OTP 59.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
board/st/stm32mp1/Kconfig | 7 ++ board/st/stm32mp1/Makefile | 1 + board/st/stm32mp1/cmd_stboard.c | 145 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 board/st/stm32mp1/cmd_stboard.c
diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig index 5ab9415..92d8f90 100644 --- a/board/st/stm32mp1/Kconfig +++ b/board/st/stm32mp1/Kconfig @@ -9,4 +9,11 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "stm32mp1"
+config CMD_STBOARD + bool "stboard - command for OTP board information" + default y + help + This compile the stboard command to + read and write the board in the OTP. + endif diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile index 8188075..3c6c035 100644 --- a/board/st/stm32mp1/Makefile +++ b/board/st/stm32mp1/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-y += stm32mp1.o +obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o endif
obj-y += board.o diff --git a/board/st/stm32mp1/cmd_stboard.c b/board/st/stm32mp1/cmd_stboard.c new file mode 100644 index 0000000..f781c36 --- /dev/null +++ b/board/st/stm32mp1/cmd_stboard.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#include <common.h> +#include <console.h> +#include <misc.h> +#include <dm/device.h> +#include <dm/uclass.h> + +static bool check_stboard(u16 board) +{ + unsigned int i; + const u16 st_board_id[] = { + 0x1272, + 0x1263, + 0x1264, + 0x1298, + 0x1341, + 0x1497, + }; + + for (i = 0; i < ARRAY_SIZE(st_board_id); i++) + if (board == st_board_id[i]) + return true; + + return false; +} + +static void display_stboard(u32 otp) +{ + printf("Board: MB%04x Var%d Rev.%c-%02d\n", + otp >> 16, + (otp >> 12) & 0xF, + ((otp >> 8) & 0xF) - 1 + 'A', + otp & 0xF); +} + +static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ret; + u32 otp; + u8 revision; + unsigned long board, variant, bom; + struct udevice *dev; + int confirmed = argc == 6 && !strcmp(argv[1], "-y"); + + argc -= 1 + confirmed; + argv += 1 + confirmed; + + if (argc != 0 && argc != 4) + return CMD_RET_USAGE; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), + &otp, sizeof(otp)); + + if (ret) { + puts("OTP read error"); + return CMD_RET_FAILURE; + } + + if (argc == 0) { + if (!otp) + puts("Board : OTP board FREE\n"); + else + display_stboard(otp); + return CMD_RET_SUCCESS; + } + + if (otp) { + display_stboard(otp); + printf("ERROR: OTP board not FREE\n"); + return CMD_RET_FAILURE; + } + + if (strict_strtoul(argv[0], 16, &board) < 0 || + board == 0 || board > 0xFFFF) { + printf("argument %d invalid: %s\n", 1, argv[0]); + return CMD_RET_USAGE; + } + + if (strict_strtoul(argv[1], 10, &variant) < 0 || + variant == 0 || variant > 15) { + printf("argument %d invalid: %s\n", 2, argv[1]); + return CMD_RET_USAGE; + } + + revision = argv[2][0] - 'A' + 1; + if (strlen(argv[2]) > 1 || revision == 0 || revision > 15) { + printf("argument %d invalid: %s\n", 3, argv[2]); + return CMD_RET_USAGE; + } + + if (strict_strtoul(argv[3], 10, &bom) < 0 || + bom == 0 || bom > 15) { + printf("argument %d invalid: %s\n", 4, argv[3]); + return CMD_RET_USAGE; + } + + otp = (board << 16) | (variant << 12) | (revision << 8) | bom; + display_stboard(otp); + printf("=> OTP[%d] = %08X\n", BSEC_OTP_BOARD, otp); + + if (!check_stboard((u16)board)) { + printf("Unknown board MB%04x\n", (u16)board); + return CMD_RET_FAILURE; + } + if (!confirmed) { + printf("Warning: Programming BOARD in OTP is irreversible!\n"); + printf("Really perform this OTP programming? <y/N>\n"); + + if (!confirm_yesno()) { + puts("BOARD programming aborted\n"); + return CMD_RET_FAILURE; + } + } + + ret = misc_write(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD), + &otp, sizeof(otp)); + + if (ret) { + puts("BOARD programming error\n"); + return CMD_RET_FAILURE; + } + puts("BOARD programming done\n"); + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(stboard, 6, 0, do_stboard, + "read/write board reference in OTP", + "\n" + " Print current board information\n" + "stboard [-y] <Board> <Variant> <Revision> <BOM>\n" + " Write board information\n" + " - Board: xxxx, example 1264 for MB1264\n" + " - Variant: 1 ... 15\n" + " - Revision: A...O\n" + " - BOM: 1...15\n");
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Allow to update board identification in OTP 59.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
board/st/stm32mp1/Kconfig | 7 ++ board/st/stm32mp1/Makefile | 1 + board/st/stm32mp1/cmd_stboard.c | 145 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 board/st/stm32mp1/cmd_stboard.c
Applied to u-boot-stm32/master, thanks!
Patrick
Add dedicated command to register in fuse a public hash key provided by keygen tool.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
arch/arm/mach-stm32mp/Kconfig | 8 +++ arch/arm/mach-stm32mp/Makefile | 1 + arch/arm/mach-stm32mp/cmd_stm32key.c | 101 +++++++++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 arch/arm/mach-stm32mp/cmd_stm32key.c
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 9c5c93c..d13d76e 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -90,6 +90,14 @@ config STM32_ETZPC help Say y to enable STM32 Extended TrustZone Protection
+config CMD_STM32KEY + bool "command stm32key to fuse public key hash" + default y + depends on CMD_FUSE + help + fuse public key hash in corresponding fuse used to authenticate + binary. + config BOOTSTAGE_STASH_ADDR default 0xC3000000
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index e59bd81..7745060 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -11,6 +11,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-y += bsec.o +obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o ifndef CONFIG_STM32MP1_TRUSTED obj-$(CONFIG_SYSRESET) += cmd_poweroff.o endif diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c new file mode 100644 index 0000000..f1f26e7 --- /dev/null +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#include <common.h> +#include <command.h> +#include <console.h> +#include <misc.h> +#include <dm/device.h> +#include <dm/uclass.h> + +#define STM32_OTP_HASH_KEY_START 24 +#define STM32_OTP_HASH_KEY_SIZE 8 + +static void read_hash_value(u32 addr) +{ + int i; + + for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) { + printf("OTP value %i: %x\n", STM32_OTP_HASH_KEY_START + i, + __be32_to_cpu(*(u32 *)addr)); + addr += 4; + } +} + +static void fuse_hash_value(u32 addr, bool print) +{ + struct udevice *dev; + u32 word, val; + int i, ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + if (ret) { + pr_err("Can't find stm32mp_bsec driver\n"); + return; + } + + for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) { + if (print) + printf("Fuse OTP %i : %x\n", + STM32_OTP_HASH_KEY_START + i, + __be32_to_cpu(*(u32 *)addr)); + + word = STM32_OTP_HASH_KEY_START + i; + val = __be32_to_cpu(*(u32 *)addr); + misc_write(dev, STM32_BSEC_OTP(word), &val, 4); + + addr += 4; + } +} + +static int confirm_prog(void) +{ + puts("Warning: Programming fuses is an irreversible operation!\n" + " This may brick your system.\n" + " Use this command only if you are sure of what you are doing!\n" + "\nReally perform this fuse programming? <y/N>\n"); + + if (confirm_yesno()) + return 1; + + puts("Fuse programming aborted\n"); + return 0; +} + +static int do_stm32key(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 addr; + const char *op = argc >= 2 ? argv[1] : NULL; + int confirmed = argc > 3 && !strcmp(argv[2], "-y"); + + argc -= 2 + confirmed; + argv += 2 + confirmed; + + if (argc < 1) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[0], NULL, 16); + if (!addr) + return CMD_RET_USAGE; + + if (!strcmp(op, "read")) + read_hash_value(addr); + + if (!strcmp(op, "fuse")) { + if (!confirmed && !confirm_prog()) + return CMD_RET_FAILURE; + fuse_hash_value(addr, !confirmed); + } + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(stm32key, 4, 1, do_stm32key, + "Fuse ST Hash key", + "read <addr>: Read the hash store at addr in memory\n" + "stm32key fuse [-y] <addr> : Fuse hash store at addr in otp\n");
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Add dedicated command to register in fuse a public hash key provided by keygen tool.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
arch/arm/mach-stm32mp/Kconfig | 8 +++ arch/arm/mach-stm32mp/Makefile | 1 + arch/arm/mach-stm32mp/cmd_stm32key.c | 101 +++++++++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 arch/arm/mach-stm32mp/cmd_stm32key.c
Applied to u-boot-stm32/master, thanks!
Patrick
Add latest information and correct some information.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
board/st/stm32mp1/README | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README index b0c8325..dc36a21 100644 --- a/board/st/stm32mp1/README +++ b/board/st/stm32mp1/README @@ -25,6 +25,10 @@ It features: Everything is supported in Linux but U-Boot is limited to: 1. UART 2. SDCard/MMC controller (SDMMC) +3. NAND controller (FMC) +4. NOR controller (QSPI) +5. USB controller (OTG DWC2) +6. Ethernet controller
And the necessary drivers 1. I2C @@ -54,13 +58,13 @@ with FSBL = First Stage Bootloader TF-A performs a full initialization of Secure peripherals and installs a secure monitor. U-Boot is running in normal world and uses TF-A monitor - to access to secure resources + to access to secure resources.
2) The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig) BootRom => FSBL = U-Boot SPL => SSBL = U-Boot SPL has limited security initialisation U-Boot is running in secure mode and provide a secure monitor to the kernel - with only PSCI support (Power State Coordination Interface defined by ARM) + with only PSCI support (Power State Coordination Interface defined by ARM).
All the STM32MP1 boards supported by U-Boot use the same generic board stm32mp1 which support all the bootable devices. @@ -111,6 +115,9 @@ the supported device trees for stm32mp157 are: # export KBUILD_OUTPUT=stm32mp15_trusted # export KBUILD_OUTPUT=stm32mp15_basic
+ you can build outside of code directory: + # export KBUILD_OUTPUT=../build/stm32mp15_trusted + 4. Configure U-Boot:
# make <defconfig_file> @@ -170,6 +177,8 @@ the supported device trees for stm32mp157 are:
You can select the boot mode, on the board ed1 with the switch SW1
+- on the daugther board ed1 with the switch SW1 : BOOT0, BOOT1, BOOT2 + ----------------------------------- Boot Mode BOOT2 BOOT1 BOOT0 ----------------------------------- @@ -267,7 +276,7 @@ for example: with gpt table with 128 entries # dd if=tf-a.stm32 of=/dev/mmcblk0p2 # dd if=u-boot.stm32 of=/dev/mmcblk0p3
-To boot from SDCard, select BootPinMode = 1 1 1 and reset. +To boot from SDCard, select BootPinMode = 1 0 1 and reset.
8. Prepare eMMC ===============
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Add latest information and correct some information.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
board/st/stm32mp1/README | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)
Applied to u-boot-stm32/master, thanks!
Patrick
Remove post.h include as it is used in spl.c
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
board/st/stm32mp1/spl.c | 1 - 1 file changed, 1 deletion(-)
diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index a7844f2..e19be0f 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -9,7 +9,6 @@ #include <dm.h> #include <ram.h> #include <asm/io.h> -#include <post.h> #include <power/pmic.h> #include <power/stpmic1.h> #include <asm/arch/ddr.h>
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Remove post.h include as it is used in spl.c
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
board/st/stm32mp1/spl.c | 1 - 1 file changed, 1 deletion(-)
Applied to u-boot-stm32/master, thanks!
Patrick
Removes unused device tree property in SPL to reduce the SPL size by 1kB
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
configs/stm32mp15_basic_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index b1fc3a2..965ea71 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -43,6 +43,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_EXT4=y CONFIG_ENV_IS_IN_SPI_FLASH=y
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Removes unused device tree property in SPL to reduce the SPL size by 1kB
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
configs/stm32mp15_basic_defconfig | 1 + 1 file changed, 1 insertion(+)
Applied to u-boot-stm32/master, thanks!
Patrick
For boot from flash, check presence of default environment to force save env.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
include/configs/stm32mp1.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 1d385e0..6c74b4b 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -112,6 +112,7 @@ "if test ${boot_device} = serial || test ${boot_device} = usb;" \ "then stm32prog ${boot_device} ${boot_instance}; " \ "else " \ + "run env_check;" \ "if test ${boot_device} = mmc;" \ "then env set boot_targets "mmc${boot_instance}"; fi;" \ "if test ${boot_device} = nand;" \ @@ -143,6 +144,9 @@ "ramdisk_addr_r=0xc4400000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ + "env_default=1\0" \ + "env_check=if test $env_default -eq 1;"\ + " then env set env_default 0;env save;fi\0" \ STM32MP_BOOTCMD \ STM32MP_MTDPARTS \ BOOTENV
Le 05/07/2019 à 17:20, Patrick Delaunay a écrit :
For boot from flash, check presence of default environment to force save env.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
include/configs/stm32mp1.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 1d385e0..6c74b4b 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -112,6 +112,7 @@ "if test ${boot_device} = serial || test ${boot_device} = usb;" \ "then stm32prog ${boot_device} ${boot_instance}; " \ "else " \
"run env_check;" \@@ -143,6 +144,9 @@ "ramdisk_addr_r=0xc4400000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \
- "env_default=1\0" \
- "env_check=if test $env_default -eq 1;"\
" then env set env_default 0;env save;fi\0" \
Tested: stm32mp157a-dk1 (OS Buildroot with ^metadata_csum option for mke2fs)
STM32MP> env print env_default env_default=1 STM32MP> run bootcmd Boot over mmc0! Saving Environment to EXT4... Journal Scan Completed Recovery required Journal Recovery Completed file found, deleting update journal finished File System is consistent update journal finished done OK switch to partitions #0, OK mmc0 is current device Scanning mmc 0:4... Found /boot/extlinux/extlinux.conf Retrieving file: /boot/extlinux/extlinux.conf 125 bytes read in 3 ms (40 KiB/s) 1: stm32mp15-buildroot Retrieving file: /boot/zImage 3948320 bytes read in 170 ms (22.1 MiB/s) append: root=/dev/mmcblk0p4 rootwait Retrieving file: /boot/stm32mp157a-dk1.dtb 38698 bytes read in 5 ms (7.4 MiB/s) ...
So,
Tested-by: Pierre-Jean Texier pjtexier@koncepto.io
Regards,
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
For boot from flash, check presence of default environment to force save env.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
include/configs/stm32mp1.h | 4 ++++ 1 file changed, 4 insertions(+)
Applied to u-boot-stm32/master, thanks!
Patrick
Prevent USB enumeration and avoid unnecessary delay in bootcmd_pxe as Ethernet device is not attached to USB.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: None
include/configs/stm32mp1.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 6c74b4b..94485a1 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -149,7 +149,8 @@ " then env set env_default 0;env save;fi\0" \ STM32MP_BOOTCMD \ STM32MP_MTDPARTS \ - BOOTENV + BOOTENV \ + "boot_net_usb_start=true\0"
#endif /* ifndef CONFIG_SPL_BUILD */ #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Prevent USB enumeration and avoid unnecessary delay in bootcmd_pxe as Ethernet device is not attached to USB.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2: None
include/configs/stm32mp1.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Applied to u-boot-stm32/master, thanks!
Patrick
Synchronize device tree with v5.2-rc4 label and update the associated u-boot dtsi.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com ---
Changes in v2: - missing alignment on ethernet@5800a000 - set ethernet0 phy-mode to "rgmii-id" for dk1 (needed modification not yet upstreamed)
arch/arm/dts/stm32mp15-ddr.dtsi | 2 +- arch/arm/dts/stm32mp157-pinctrl.dtsi | 270 ++++++++++++++++++++++++++++++- arch/arm/dts/stm32mp157-u-boot.dtsi | 60 ++++--- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 4 - arch/arm/dts/stm32mp157a-dk1.dts | 32 ++-- arch/arm/dts/stm32mp157c-dk2.dts | 1 + arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 15 +- arch/arm/dts/stm32mp157c-ed1.dts | 205 +++++------------------ arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 3 - arch/arm/dts/stm32mp157c-ev1.dts | 12 +- arch/arm/dts/stm32mp157c.dtsi | 215 +++++++++++++++++------- 11 files changed, 541 insertions(+), 278 deletions(-)
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 4172c02..0164e34 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -5,7 +5,7 @@
/ { soc { - ddr: ddr@0x5A003000{ + ddr: ddr@5A003000{ u-boot,dm-pre-reloc;
compatible = "st,stm32mp1-ddr"; diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 4c424c4..9bae850 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -14,6 +14,7 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + hwlocks = <&hwspinlock 0>; pins-are-numbered;
gpioa: gpio@50002000 { @@ -164,6 +165,27 @@ }; };
+ cec_pins_sleep_a: cec-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ + }; + }; + + cec_pins_b: cec-1 { + pins { + pinmux = <STM32_PINMUX('B', 6, AF5)>; + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + cec_pins_sleep_b: cec-sleep-1 { + pins { + pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -269,7 +291,14 @@ }; };
- i2c1_pins_b: i2c1-1 { + i2c1_pins_sleep_a: i2c1-1 { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ + }; + }; + + i2c1_pins_b: i2c1-2 { pins { pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ @@ -289,7 +318,14 @@ }; };
- i2c2_pins_b: i2c2-1 { + i2c2_pins_sleep_a: i2c2-1 { + pins { + pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ + <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ + }; + }; + + i2c2_pins_b: i2c2-2 { pins { pinmux = <STM32_PINMUX('Z', 0, AF3)>, /* I2C2_SCL */ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ @@ -309,6 +345,152 @@ }; };
+ i2c5_pins_sleep_a: i2c5-1 { + pins { + pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ + + }; + }; + + ltdc_pins_a: ltdc-a-0 { + pins { + pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ + <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ + <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ + <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ + <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ + <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ + <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ + <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ + <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ + <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ + <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ + <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ + <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ + <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ + <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ + <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ + <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ + <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ + <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ + <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ + <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ + <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ + <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ + <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ + <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ + <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ + <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_pins_sleep_a: ltdc-a-1 { + pins { + pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ + <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ + <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ + <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ + <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ + <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ + <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ + <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ + <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ + <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ + <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ + <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ + <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ + <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ + <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ + <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ + <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ + <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ + <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ + <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ + }; + }; + + ltdc_pins_b: ltdc-b-0 { + pins { + pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ + <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ + <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ + <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ + <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ + <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ + <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ + <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ + <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ + <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ + <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ + <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ + <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ + <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ + <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ + <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ + <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ + <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ + <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ + <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ + <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ + <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ + <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ + <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ + <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ + <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ + <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_pins_sleep_b: ltdc-b-1 { + pins { + pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ + <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ + <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ + <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ + <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ + <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ + <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ + <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ + <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ + <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ + <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ + <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ + <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ + <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ + <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ + <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ + <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ + <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ + <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ + <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ + <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ + <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ + <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ + <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ + <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ + <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ + <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ @@ -322,6 +504,13 @@ }; };
+ m_can1_sleep_pins_a: m_can1-sleep@0 { + pins { + pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ @@ -393,7 +582,8 @@ slew-rate = <3>; }; }; - sdmmc1_b4_pins_a: sdmmc1-b4@0 { + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ @@ -407,18 +597,61 @@ }; };
- sdmmc1_dir_pins_a: sdmmc1-dir@0 { + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */ - <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ slew-rate = <3>; drive-push-pull; bias-pull-up; }; + pins2{ + pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + bias-pull-up; + }; }; - sdmmc2_b4_pins_a: sdmmc2-b4@0 { + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ + <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ @@ -432,7 +665,7 @@ }; };
- sdmmc2_d47_pins_a: sdmmc2-d47@0 { + sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ @@ -444,6 +677,19 @@ }; };
+ spdifrx_pins_a: spdifrx-0 { + pins { + pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ + bias-disable; + }; + }; + + spdifrx_sleep_pins_a: spdifrx-1 { + pins { + pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ + }; + }; + spi2_pins_a: spi2-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ @@ -522,6 +768,7 @@ pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + hwlocks = <&hwspinlock 0>;
gpioz: gpio@54004000 { gpio-controller; @@ -546,6 +793,13 @@ }; };
+ i2c4_pins_sleep_a: i2c4-1 { + pins { + pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ + <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ + }; + }; + spi1_pins_a: spi1-0 { pins1 { pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi index c9f534e..f7c7acc 100644 --- a/arch/arm/dts/stm32mp157-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157-u-boot.dtsi @@ -21,11 +21,11 @@ pinctrl1 = &pinctrl_z; };
- config { + clocks { u-boot,dm-pre-reloc; };
- clocks { + reboot { u-boot,dm-pre-reloc; };
@@ -35,42 +35,26 @@ };
&bsec { - u-boot,dm-pre-reloc; -}; - -&clk_hsi { - u-boot,dm-pre-reloc; -}; - -&clk_hse { - u-boot,dm-pre-reloc; -}; - -&clk_lse { - u-boot,dm-pre-reloc; -}; - -&clk_lsi { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; };
&clk_csi { u-boot,dm-pre-reloc; };
-&rcc { +&clk_hsi { u-boot,dm-pre-reloc; };
-&rcc_reboot { +&clk_hse { u-boot,dm-pre-reloc; };
-&pinctrl { +&clk_lsi { u-boot,dm-pre-reloc; };
-&pinctrl_z { +&clk_lse { u-boot,dm-pre-reloc; };
@@ -134,6 +118,34 @@ u-boot,dm-pre-reloc; };
-&iwdg2 { +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pinctrl_z { + u-boot,dm-pre-reloc; +}; + +&pwr { u-boot,dm-pre-reloc; }; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&sdmmc1 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +}; + +&sdmmc2 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +}; + +&sdmmc3 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +}; + +&usbotg_hs { + compatible = "st,stm32mp1-hsotg", "snps,dwc2"; +}; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index 0f32a38..36c852d 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -194,7 +194,3 @@ u-boot,force-b-session-valid; hnp-srp-disable; }; - -&v3v3 { - regulator-always-on; -}; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index e36773d..adb2464 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -39,12 +39,19 @@ }; };
+&cec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cec_pins_b>; + pinctrl-1 = <&cec_pins_sleep_b>; + status = "okay"; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>;
@@ -58,12 +65,14 @@ }; };
+ &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; + /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names;
@@ -88,17 +97,13 @@ pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; status = "okay";
- st,main-control-register = <0x04>; - st,vin-control-register = <0xc0>; - st,usb-control-register = <0x20>; - regulators { compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; ldo3-supply = <&vdd_ddr>; ldo6-supply = <&v3v3>; @@ -107,7 +112,7 @@
vddcore: buck1 { regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; @@ -187,7 +192,6 @@ regulator-max-microvolt = <1200000>; regulator-always-on; interrupts = <IT_CURLIM_LDO6 0>; - };
vref_ddr: vref_ddr { @@ -204,7 +208,6 @@ vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; - regulator-active-discharge; };
vbus_sw: pwr_sw2 { @@ -216,8 +219,9 @@
onkey { compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; status = "okay"; };
@@ -228,6 +232,10 @@ }; };
+&ipcc { + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; @@ -246,8 +254,10 @@ };
&sdmmc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; broken-cd; st,neg-edge; bus-width = <4>; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 9a81d2d..020ea0f 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -42,6 +42,7 @@ compatible = "orisetech,otm8009a"; reg = <0>; reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; status = "okay";
port { diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 55f9903..200601e 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -156,6 +156,10 @@ }; };
+&sdmmc1 { + u-boot,dm-spl; +}; + &sdmmc1_b4_pins_a { u-boot,dm-spl; pins { @@ -165,12 +169,15 @@
&sdmmc1_dir_pins_a { u-boot,dm-spl; - pins { + pins1 { + u-boot,dm-spl; + }; + pins2 { u-boot,dm-spl; }; };
-&sdmmc1 { +&sdmmc2 { u-boot,dm-spl; };
@@ -188,10 +195,6 @@ }; };
-&sdmmc2 { - u-boot,dm-spl; -}; - &uart4 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index b10208f..11981d6 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -19,6 +19,7 @@ };
memory@c0000000 { + device_type = "memory"; reg = <0xC0000000 0x40000000>; };
@@ -40,7 +41,7 @@ }; };
-&hwspinlock { +&dts { status = "okay"; };
@@ -50,23 +51,20 @@ i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names;
- pmic: stpmic1@33 { + pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; - interrupts = <0 2>; - interrupt-parent = <&gpioa>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; status = "okay";
- st,main_control_register = <0x04>; - st,vin_control_register = <0xc0>; - st,usb_control_register = <0x30>; - regulators { compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; ldo2-supply = <&v3v3>; ldo3-supply = <&vdd_ddr>; @@ -80,20 +78,8 @@ regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on; - regulator-initial-mode = <2>; + regulator-initial-mode = <0>; regulator-over-current-protection; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1200000>; - regulator-mode = <8>; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; };
vdd_ddr: buck2 { @@ -101,22 +87,8 @@ regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; - regulator-initial-mode = <2>; + regulator-initial-mode = <0>; regulator-over-current-protection; - - regulator-state-standby { - regulator-suspend-microvolt = <1350000>; - regulator-on-in-suspend; - regulator-mode = <8>; - }; - regulator-state-mem { - regulator-suspend-microvolt = <1350000>; - regulator-on-in-suspend; - regulator-mode = <8>; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; };
vdd: buck3 { @@ -124,46 +96,18 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; - st,mask_reset; - regulator-initial-mode = <8>; + st,mask-reset; + regulator-initial-mode = <0>; regulator-over-current-protection; - - regulator-state-standby { - regulator-suspend-microvolt = <3300000>; - regulator-on-in-suspend; - regulator-mode = <8>; - }; - regulator-state-mem { - regulator-suspend-microvolt = <3300000>; - regulator-on-in-suspend; - regulator-mode = <8>; - }; - regulator-state-disk { - regulator-suspend-microvolt = <3300000>; - regulator-on-in-suspend; - regulator-mode = <8>; - }; };
v3v3: buck4 { regulator-name = "v3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; + regulator-always-on; regulator-over-current-protection; - regulator-initial-mode = <8>; - - regulator-state-standby { - regulator-suspend-microvolt = <3300000>; - regulator-unchanged-in-suspend; - regulator-mode = <8>; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; + regulator-initial-mode = <0>; };
vdda: ldo1 { @@ -171,18 +115,6 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = <IT_CURLIM_LDO1 0>; - interrupt-parent = <&pmic>; - - regulator-state-standby { - regulator-suspend-microvolt = <2900000>; - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; };
v2v8: ldo2 { @@ -190,36 +122,14 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; interrupts = <IT_CURLIM_LDO2 0>; - interrupt-parent = <&pmic>; - - regulator-state-standby { - regulator-suspend-microvolt = <2800000>; - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; };
vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; - regulator-min-microvolt = <0000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; regulator-always-on; regulator-over-current-protection; - - regulator-state-standby { - regulator-off-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; };
vdd_usb: ldo4 { @@ -227,17 +137,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; interrupts = <IT_CURLIM_LDO4 0>; - interrupt-parent = <&pmic>; - - regulator-state-standby { - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; };
vdd_sd: ldo5 { @@ -245,19 +144,7 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = <IT_CURLIM_LDO5 0>; - interrupt-parent = <&pmic>; regulator-boot-on; - - regulator-state-standby { - regulator-suspend-microvolt = <2900000>; - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; };
v1v8: ldo6 { @@ -265,66 +152,53 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; interrupts = <IT_CURLIM_LDO6 0>; - interrupt-parent = <&pmic>; - - regulator-state-standby { - regulator-suspend-microvolt = <1800000>; - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; };
vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; regulator-over-current-protection; - - regulator-state-standby { - regulator-on-in-suspend; - }; - regulator-state-mem { - regulator-on-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; };
bst_out: boost { regulator-name = "bst_out"; interrupts = <IT_OCP_BOOST 0>; - interrupt-parent = <&pmic>; };
vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; - interrupt-parent = <&pmic>; - regulator-active-discharge; };
vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = <IT_OCP_SWOUT 0>; - interrupt-parent = <&pmic>; regulator-active-discharge; }; }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; }; };
-&iwdg2 { - timeout-sec = <32>; +&ipcc { status = "okay"; };
-&pinctrl { - hwlocks = <&hwspinlock 0>; +&iwdg2 { + timeout-sec = <32>; + status = "okay"; };
&pwr { @@ -340,7 +214,10 @@ };
&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; broken-cd; st,sig-dir; st,neg-edge; @@ -348,11 +225,6 @@ bus-width = <4>; vmmc-supply = <&vdd_sd>; vqmmc-supply = <&sd_switch>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - sd-uhs-sdr104; status = "okay"; };
@@ -371,6 +243,9 @@
&timers6 { status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; timer@5 { status = "okay"; }; @@ -382,6 +257,10 @@ status = "okay"; };
+&usbotg_hs { + vbus-supply = <&vbus_otg>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; }; diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 994092a..b656eb1 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -56,6 +56,3 @@ }; };
-&v3v3 { - regulator-always-on; -}; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 663e52a..ca2a333 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -6,6 +6,7 @@ /dts-v1/;
#include "stm32mp157c-ed1.dts" +#include <dt-bindings/gpio/gpio.h>
/ { model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; @@ -157,8 +158,9 @@ };
&m_can1 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; status = "okay"; };
@@ -194,6 +196,9 @@ };
&timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm2_pins_a>; @@ -206,6 +211,8 @@ };
&timers8 { + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm8_pins_a>; @@ -218,6 +225,8 @@ };
&timers12 { + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm12_pins_a>; @@ -232,7 +241,6 @@ &usbh_ehci { phys = <&usbphyc_port0>; phy-names = "usb"; - vbus-supply = <&vbus_sw>; status = "okay"; };
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 7321585..d15fba0 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -35,28 +35,6 @@ cpu_on = <0x84000003>; };
- aliases { - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; - serial0 = &usart1; - serial1 = &usart2; - serial2 = &usart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &usart6; - serial6 = &uart7; - serial7 = &uart8; - }; - intc: interrupt-controller@a0021000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; @@ -106,6 +84,38 @@ }; };
+ thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&dts>; + + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&rcc>; + offset = <0x404>; + mask = <0x1>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -120,6 +130,12 @@ reg = <0x40000000 0x400>; clocks = <&rcc TIM2_K>; clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; status = "disabled";
pwm { @@ -141,6 +157,13 @@ reg = <0x40001000 0x400>; clocks = <&rcc TIM3_K>; clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled";
pwm { @@ -162,6 +185,11 @@ reg = <0x40002000 0x400>; clocks = <&rcc TIM4_K>; clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4"; status = "disabled";
pwm { @@ -183,6 +211,13 @@ reg = <0x40003000 0x400>; clocks = <&rcc TIM5_K>; clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled";
pwm { @@ -204,6 +239,8 @@ reg = <0x40004000 0x400>; clocks = <&rcc TIM6_K>; clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; status = "disabled";
timer@5 { @@ -220,6 +257,8 @@ reg = <0x40005000 0x400>; clocks = <&rcc TIM7_K>; clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; status = "disabled";
timer@6 { @@ -347,6 +386,19 @@ status = "disabled"; };
+ spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; + reg = <0x4000d000 0x400>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + status = "disabled"; + }; + usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; @@ -487,6 +539,15 @@ reg = <0x44000000 0x400>; clocks = <&rcc TIM1_K>; clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; status = "disabled";
pwm { @@ -508,6 +569,15 @@ reg = <0x44001000 0x400>; clocks = <&rcc TIM8_K>; clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; status = "disabled";
pwm { @@ -565,6 +635,11 @@ reg = <0x44006000 0x400>; clocks = <&rcc TIM15_K>; clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; status = "disabled";
pwm { @@ -586,6 +661,9 @@ reg = <0x44007000 0x400>; clocks = <&rcc TIM16_K>; clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; status = "disabled";
pwm { @@ -606,6 +684,9 @@ reg = <0x44008000 0x400>; clocks = <&rcc TIM17_K>; clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; status = "disabled";
pwm { @@ -706,14 +787,14 @@
m_can1: can@4400e000 { compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x2800>; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; reg-names = "m_can", "message_ram"; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; };
@@ -811,13 +892,14 @@ };
sdmmc3: sdmmc@48004000 { - compatible = "st,stm32-sdmmc2"; - reg = <0x48004000 0x400>, <0x48005000 0x400>; - reg-names = "sdmmc", "delay"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x48004000 0x400>; + reg-names = "sdmmc"; interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>; clocks = <&rcc SDMMC3_K>; + clock-names = "apb_pclk"; resets = <&rcc SDMMC3_R>; - st,idma = <1>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; @@ -825,7 +907,7 @@ };
usbotg_hs: usb-otg@49000000 { - compatible = "st,stm32mp1-hsotg", "snps,dwc2"; + compatible = "snps,dwc2"; reg = <0x49000000 0x10000>; clocks = <&rcc USBO_K>; clock-names = "otg"; @@ -846,6 +928,20 @@ reg = <0x4c000000 0x400>; clocks = <&rcc HSEM>; clock-names = "hwspinlock"; + }; + + ipcc: mailbox@4c001000 { + compatible = "st,stm32mp1-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = + <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <&exti 61 1>; + interrupt-names = "rx", "tx", "wakeup"; + clocks = <&rcc IPCC>; + wakeup-source; status = "disabled"; };
@@ -856,13 +952,6 @@ #reset-cells = <1>; };
- rcc_reboot: rcc-reboot@50000000 { - compatible = "syscon-reboot"; - regmap = <&rcc>; - offset = <0x404>; - mask = <0x1>; - }; - pwr: pwr@50001000 { compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd"; reg = <0x50001000 0x400>; @@ -872,7 +961,7 @@ clocks = <&rcc PLL2_R>; clock-names = "phyclk";
- pwr-regulators@c { + pwr-regulators { compatible = "st,stm32mp1,pwr-reg"; st,tzcr = <&rcc 0x0 0x1>;
@@ -906,6 +995,7 @@ syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; };
lptimer2: timer@50021000 { @@ -994,6 +1084,16 @@ status = "disabled"; };
+ dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc TMPSENS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + cryp1: cryp@54001000 { compatible = "st,stm32mp1-cryp"; reg = <0x54001000 0x400>; @@ -1059,26 +1159,27 @@ };
sdmmc1: sdmmc@58005000 { - compatible = "st,stm32-sdmmc2"; - reg = <0x58005000 0x1000>, <0x58006000 0x1000>; - reg-names = "sdmmc", "delay"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x58005000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; - st,idma = <1>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; - status = "disabled"; };
sdmmc2: sdmmc@58007000 { - compatible = "st,stm32-sdmmc2"; - reg = <0x58007000 0x1000>, <0x58008000 0x1000>; - reg-names = "sdmmc", "delay"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x58007000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; - st,idma = <1>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; @@ -1102,25 +1203,21 @@ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; reg = <0x5800a000 0x2000>; reg-names = "stmmaceth"; - interrupts-extended = - <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, - <&exti 70 1>; - interrupt-names = "macirq", - "eth_wake_irq", - "stm32_pwr_wakeup"; + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", - "ethstp"; + "ethstp", + "syscfg-clk"; clocks = <&rcc ETHMAC>, <&rcc ETHTX>, <&rcc ETHRX>, - <&rcc ETHSTP>; + <&rcc ETHSTP>, + <&rcc SYSCFG>; st,syscon = <&syscfg 0x4>; snps,mixed-burst; snps,pbl = <2>; - snps,en-tx-lpi-clockgating; snps,axi-config = <&stmmac_axi_config_0>; snps,tso; status = "disabled"; @@ -1245,6 +1342,12 @@ reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; };
i2c6: i2c@5c009000 {
Hi Patrick,
Le 05/07/2019 à 17:20, Patrick Delaunay a écrit :
Synchronize device tree with v5.2-rc4 label and update the associated u-boot dtsi.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2:
missing alignment on ethernet@5800a000
set ethernet0 phy-mode to "rgmii-id" for dk1 (needed modification not yet upstreamed)
arch/arm/dts/stm32mp15-ddr.dtsi | 2 +- arch/arm/dts/stm32mp157-pinctrl.dtsi | 270 ++++++++++++++++++++++++++++++- arch/arm/dts/stm32mp157-u-boot.dtsi | 60 ++++--- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 4 - arch/arm/dts/stm32mp157a-dk1.dts | 32 ++-- arch/arm/dts/stm32mp157c-dk2.dts | 1 + arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 15 +- arch/arm/dts/stm32mp157c-ed1.dts | 205 +++++------------------ arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 3 - arch/arm/dts/stm32mp157c-ev1.dts | 12 +- arch/arm/dts/stm32mp157c.dtsi | 215 +++++++++++++++++------- 11 files changed, 541 insertions(+), 278 deletions(-)
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 4172c02..0164e34 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -5,7 +5,7 @@
/ { soc {
ddr: ddr@0x5A003000{
ddr: ddr@5A003000{ u-boot,dm-pre-reloc; compatible = "st,stm32mp1-ddr";diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 4c424c4..9bae850 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -14,6 +14,7 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>;
hwlocks = <&hwspinlock 0>; pins-are-numbered; gpioa: gpio@50002000 {@@ -164,6 +165,27 @@ }; };
cec_pins_sleep_a: cec-sleep-0 {pins {pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */};};cec_pins_b: cec-1 {pins {pinmux = <STM32_PINMUX('B', 6, AF5)>;bias-disable;drive-open-drain;slew-rate = <0>;};};cec_pins_sleep_b: cec-sleep-1 {pins {pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */};};ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */@@ -269,7 +291,14 @@ }; };
i2c1_pins_b: i2c1-1 {
i2c1_pins_sleep_a: i2c1-1 {pins {pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */<STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */};};i2c1_pins_b: i2c1-2 { pins { pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */@@ -289,7 +318,14 @@ }; };
i2c2_pins_b: i2c2-1 {
i2c2_pins_sleep_a: i2c2-1 {pins {pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */<STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */};};i2c2_pins_b: i2c2-2 { pins { pinmux = <STM32_PINMUX('Z', 0, AF3)>, /* I2C2_SCL */ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */@@ -309,6 +345,152 @@ }; };
i2c5_pins_sleep_a: i2c5-1 {pins {pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */<STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */};};ltdc_pins_a: ltdc-a-0 {pins {pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */<STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */<STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */<STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */<STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */<STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */<STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */<STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */<STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */<STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */<STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */<STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */<STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */<STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */<STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */<STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */<STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */<STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */<STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */<STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */<STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */<STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */<STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */<STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */<STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */<STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */<STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */<STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */bias-disable;drive-push-pull;slew-rate = <1>;};};ltdc_pins_sleep_a: ltdc-a-1 {pins {pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */<STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */<STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */<STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */<STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */<STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */<STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */<STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */<STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */<STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */<STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */<STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */<STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */<STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */<STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */<STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */<STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */<STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */<STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */<STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */<STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */<STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */<STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */<STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */<STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */<STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */<STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */};};ltdc_pins_b: ltdc-b-0 {pins {pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */<STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */<STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */<STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */<STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */<STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */<STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */<STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */<STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */<STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */<STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */<STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */bias-disable;drive-push-pull;slew-rate = <1>;};};ltdc_pins_sleep_b: ltdc-b-1 {pins {pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */<STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */<STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */<STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */<STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */<STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */<STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */<STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */<STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */<STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */<STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */<STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */<STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */<STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */<STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */<STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */<STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */<STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */<STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */<STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */<STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */<STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */<STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */<STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */<STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */<STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */<STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */<STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */};};m_can1_pins_a: m-can1-0 { pins1 { pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */@@ -322,6 +504,13 @@ }; };
m_can1_sleep_pins_a: m_can1-sleep@0 {pins {pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */<STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */};};pwm2_pins_a: pwm2-0 { pins { pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */@@ -393,7 +582,8 @@ slew-rate = <3>; }; };
sdmmc1_b4_pins_a: sdmmc1-b4@0 {
sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */@@ -407,18 +597,61 @@ }; };
sdmmc1_dir_pins_a: sdmmc1-dir@0 {
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {pins1 {pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */<STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */slew-rate = <3>;drive-push-pull;bias-disable;};pins2{pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */slew-rate = <3>;drive-open-drain;bias-disable;};};sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins {pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */};};sdmmc1_dir_pins_a: sdmmc1-dir-0 {pins1 { pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */<STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ slew-rate = <3>; drive-push-pull; bias-pull-up; };pins2{pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */bias-pull-up;}; };
sdmmc2_b4_pins_a: sdmmc2-b4@0 {
sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {pins {pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */<STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */<STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */};};sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */@@ -432,7 +665,7 @@ }; };
sdmmc2_d47_pins_a: sdmmc2-d47@0 {
sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */@@ -444,6 +677,19 @@ }; };
spdifrx_pins_a: spdifrx-0 {pins {pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */bias-disable;};};spdifrx_sleep_pins_a: spdifrx-1 {pins {pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */};};spi2_pins_a: spi2-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */@@ -522,6 +768,7 @@ pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>;
hwlocks = <&hwspinlock 0>; gpioz: gpio@54004000 { gpio-controller;@@ -546,6 +793,13 @@ }; };
i2c4_pins_sleep_a: i2c4-1 {pins {pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */<STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */};};spi1_pins_a: spi1-0 { pins1 { pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi index c9f534e..f7c7acc 100644 --- a/arch/arm/dts/stm32mp157-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157-u-boot.dtsi @@ -21,11 +21,11 @@ pinctrl1 = &pinctrl_z; };
- config {
- clocks { u-boot,dm-pre-reloc; };
- clocks {
- reboot { u-boot,dm-pre-reloc; };
@@ -35,42 +35,26 @@ };
&bsec {
- u-boot,dm-pre-reloc;
-};
-&clk_hsi {
- u-boot,dm-pre-reloc;
-};
-&clk_hse {
- u-boot,dm-pre-reloc;
-};
-&clk_lse {
- u-boot,dm-pre-reloc;
-};
-&clk_lsi {
- u-boot,dm-pre-reloc;
u-boot,dm-pre-proper; };
&clk_csi { u-boot,dm-pre-reloc; };
-&rcc { +&clk_hsi { u-boot,dm-pre-reloc; };
-&rcc_reboot { +&clk_hse { u-boot,dm-pre-reloc; };
-&pinctrl { +&clk_lsi { u-boot,dm-pre-reloc; };
-&pinctrl_z { +&clk_lse { u-boot,dm-pre-reloc; };
@@ -134,6 +118,34 @@ u-boot,dm-pre-reloc; };
-&iwdg2 { +&pinctrl {
- u-boot,dm-pre-reloc;
+};
+&pinctrl_z {
- u-boot,dm-pre-reloc;
+};
+&pwr { u-boot,dm-pre-reloc; };
+&rcc {
- u-boot,dm-pre-reloc;
+};
+&sdmmc1 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+};
+&sdmmc2 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+};
+&sdmmc3 {
- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+};
+&usbotg_hs {
- compatible = "st,stm32mp1-hsotg", "snps,dwc2";
+}; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index 0f32a38..36c852d 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -194,7 +194,3 @@ u-boot,force-b-session-valid; hnp-srp-disable; };
-&v3v3 {
- regulator-always-on;
-}; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index e36773d..adb2464 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -39,12 +39,19 @@ }; };
+&cec {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cec_pins_b>;
- pinctrl-1 = <&cec_pins_sleep_b>;
- status = "okay";
+};
- ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>;
@@ -58,12 +65,14 @@ }; };
- &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay";
- /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names;
@@ -88,17 +97,13 @@ pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>;
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
st,main-control-register = <0x04>;st,vin-control-register = <0xc0>;st,usb-control-register = <0x20>;- regulators { compatible = "st,stpmic1-regulators";
ldo1-supply = <&v3v3>; ldo3-supply = <&vdd_ddr>; ldo6-supply = <&v3v3>;@@ -107,7 +112,7 @@
vddcore: buck1 { regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>;@@ -187,7 +192,6 @@ regulator-max-microvolt = <1200000>; regulator-always-on; interrupts = <IT_CURLIM_LDO6 0>;
}; vref_ddr: vref_ddr {@@ -204,7 +208,6 @@ vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>;
regulator-active-discharge; }; vbus_sw: pwr_sw2 {@@ -216,8 +219,9 @@
onkey { compatible = "st,stpmic1-onkey";
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; interrupt-names = "onkey-falling", "onkey-rising";power-off-time-sec = <10>; status = "okay";@@ -228,6 +232,10 @@ }; };
+&ipcc {
- status = "okay";
+};
- &iwdg2 { timeout-sec = <32>; status = "okay";
@@ -246,8 +254,10 @@ };
&sdmmc1 {
- pinctrl-names = "default";
- pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; broken-cd; st,neg-edge; bus-width = <4>;
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 9a81d2d..020ea0f 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -42,6 +42,7 @@ compatible = "orisetech,otm8009a"; reg = <0>; reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
power-supply = <&v3v3>;status = "okay";
port {
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 55f9903..200601e 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -156,6 +156,10 @@ }; };
+&sdmmc1 {
- u-boot,dm-spl;
+};
- &sdmmc1_b4_pins_a { u-boot,dm-spl; pins {
@@ -165,12 +169,15 @@
&sdmmc1_dir_pins_a { u-boot,dm-spl;
- pins {
- pins1 {
u-boot,dm-spl;- };
- pins2 { u-boot,dm-spl; }; };
-&sdmmc1 { +&sdmmc2 { u-boot,dm-spl; };
@@ -188,10 +195,6 @@ }; };
-&sdmmc2 {
- u-boot,dm-spl;
-};
- &uart4 { u-boot,dm-pre-reloc; };
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index b10208f..11981d6 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -19,6 +19,7 @@ };
memory@c0000000 {
device_type = "memory";@@ -40,7 +41,7 @@ }; };
-&hwspinlock { +&dts { status = "okay"; };
@@ -50,23 +51,20 @@ i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
- pmic: stpmic1@33 {
- pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>;
interrupts = <0 2>;interrupt-parent = <&gpioa>;
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
st,main_control_register = <0x04>;st,vin_control_register = <0xc0>;st,usb_control_register = <0x30>;- regulators { compatible = "st,stpmic1-regulators";
ldo1-supply = <&v3v3>; ldo2-supply = <&v3v3>; ldo3-supply = <&vdd_ddr>;@@ -80,20 +78,8 @@ regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on;
regulator-initial-mode = <2>;
regulator-initial-mode = <0>; regulator-over-current-protection;
regulator-state-standby {regulator-on-in-suspend;regulator-suspend-microvolt = <1200000>;regulator-mode = <8>;};regulator-state-mem {regulator-off-in-suspend;};regulator-state-disk {regulator-off-in-suspend;}; }; vdd_ddr: buck2 {@@ -101,22 +87,8 @@ regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on;
regulator-initial-mode = <2>;
regulator-initial-mode = <0>; regulator-over-current-protection;
regulator-state-standby {regulator-suspend-microvolt = <1350000>;regulator-on-in-suspend;regulator-mode = <8>;};regulator-state-mem {regulator-suspend-microvolt = <1350000>;regulator-on-in-suspend;regulator-mode = <8>;};regulator-state-disk {regulator-off-in-suspend;}; }; vdd: buck3 {@@ -124,46 +96,18 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on;
st,mask_reset;regulator-initial-mode = <8>;
st,mask-reset;regulator-initial-mode = <0>; regulator-over-current-protection;
regulator-state-standby {regulator-suspend-microvolt = <3300000>;regulator-on-in-suspend;regulator-mode = <8>;};regulator-state-mem {regulator-suspend-microvolt = <3300000>;regulator-on-in-suspend;regulator-mode = <8>;};regulator-state-disk {regulator-suspend-microvolt = <3300000>;regulator-on-in-suspend;regulator-mode = <8>;}; }; v3v3: buck4 { regulator-name = "v3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>;regulator-boot-on;
regulator-always-on; regulator-over-current-protection;
regulator-initial-mode = <8>;regulator-state-standby {regulator-suspend-microvolt = <3300000>;regulator-unchanged-in-suspend;regulator-mode = <8>;};regulator-state-mem {regulator-off-in-suspend;};regulator-state-disk {regulator-off-in-suspend;};
regulator-initial-mode = <0>; }; vdda: ldo1 {@@ -171,18 +115,6 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = <IT_CURLIM_LDO1 0>;
interrupt-parent = <&pmic>;regulator-state-standby {regulator-suspend-microvolt = <2900000>;regulator-unchanged-in-suspend;};regulator-state-mem {regulator-off-in-suspend;};regulator-state-disk {regulator-off-in-suspend;}; }; v2v8: ldo2 {@@ -190,36 +122,14 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; interrupts = <IT_CURLIM_LDO2 0>;
interrupt-parent = <&pmic>;regulator-state-standby {regulator-suspend-microvolt = <2800000>;regulator-unchanged-in-suspend;};regulator-state-mem {regulator-off-in-suspend;};regulator-state-disk {regulator-off-in-suspend;}; }; vtt_ddr: ldo3 { regulator-name = "vtt_ddr";regulator-min-microvolt = <0000000>;regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <500000>;regulator-max-microvolt = <750000>; regulator-always-on; regulator-over-current-protection;
regulator-state-standby {regulator-off-in-suspend;};regulator-state-mem {regulator-off-in-suspend;};regulator-state-disk {regulator-off-in-suspend;}; }; vdd_usb: ldo4 {@@ -227,17 +137,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; interrupts = <IT_CURLIM_LDO4 0>;
interrupt-parent = <&pmic>;regulator-state-standby {regulator-unchanged-in-suspend;};regulator-state-mem {regulator-off-in-suspend;};regulator-state-disk {regulator-off-in-suspend;}; }; vdd_sd: ldo5 {@@ -245,19 +144,7 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = <IT_CURLIM_LDO5 0>;
interrupt-parent = <&pmic>; regulator-boot-on;regulator-state-standby {regulator-suspend-microvolt = <2900000>;regulator-unchanged-in-suspend;};regulator-state-mem {regulator-off-in-suspend;};regulator-state-disk {regulator-off-in-suspend;}; }; v1v8: ldo6 {@@ -265,66 +152,53 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; interrupts = <IT_CURLIM_LDO6 0>;
interrupt-parent = <&pmic>;regulator-state-standby {regulator-suspend-microvolt = <1800000>;regulator-unchanged-in-suspend;};regulator-state-mem {regulator-off-in-suspend;};regulator-state-disk {regulator-off-in-suspend;}; }; vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; regulator-over-current-protection;regulator-state-standby {regulator-on-in-suspend;};regulator-state-mem {regulator-on-in-suspend;};regulator-state-disk {regulator-off-in-suspend;}; }; bst_out: boost { regulator-name = "bst_out"; interrupts = <IT_OCP_BOOST 0>;interrupt-parent = <&pmic>; }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>;interrupt-parent = <&pmic>;regulator-active-discharge; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = <IT_OCP_SWOUT 0>;interrupt-parent = <&pmic>; regulator-active-discharge; };};
onkey {compatible = "st,stpmic1-onkey";interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;interrupt-names = "onkey-falling", "onkey-rising";power-off-time-sec = <10>;status = "okay";};watchdog {compatible = "st,stpmic1-wdt";status = "disabled";};-&iwdg2 {
- timeout-sec = <32>;
+&ipcc { status = "okay"; };
-&pinctrl {
- hwlocks = <&hwspinlock 0>;
+&iwdg2 {
timeout-sec = <32>;
status = "okay"; };
&pwr {
@@ -340,7 +214,10 @@ };
&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; broken-cd; st,sig-dir; st,neg-edge;
@@ -348,11 +225,6 @@ bus-width = <4>; vmmc-supply = <&vdd_sd>; vqmmc-supply = <&sd_switch>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-ddr50;
- sd-uhs-sdr104; status = "okay"; };
@@ -371,6 +243,9 @@
&timers6 { status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names; timer@5 { status = "okay"; };
@@ -382,6 +257,10 @@ status = "okay"; };
+&usbotg_hs {
- vbus-supply = <&vbus_otg>;
+};
- &usbphyc_port0 { phy-supply = <&vdd_usb>; };
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 994092a..b656eb1 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -56,6 +56,3 @@ }; };
-&v3v3 {
- regulator-always-on;
-}; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 663e52a..ca2a333 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -6,6 +6,7 @@ /dts-v1/;
#include "stm32mp157c-ed1.dts" +#include <dt-bindings/gpio/gpio.h>
/ { model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; @@ -157,8 +158,9 @@ };
&m_can1 {
- pinctrl-names = "default";
- pinctrl-names = "default", "sleep"; pinctrl-0 = <&m_can1_pins_a>;
- pinctrl-1 = <&m_can1_sleep_pins_a>; status = "okay"; };
@@ -194,6 +196,9 @@ };
&timers2 {
- /* spare dmas for other usage (un-delete to enable pwm capture) */
- /delete-property/dmas;
- /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm2_pins_a>;
@@ -206,6 +211,8 @@ };
&timers8 {
- /delete-property/dmas;
- /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm8_pins_a>;
@@ -218,6 +225,8 @@ };
&timers12 {
- /delete-property/dmas;
- /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm12_pins_a>;
@@ -232,7 +241,6 @@ &usbh_ehci { phys = <&usbphyc_port0>; phy-names = "usb";
- vbus-supply = <&vbus_sw>; status = "okay"; };
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 7321585..d15fba0 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -35,28 +35,6 @@ cpu_on = <0x84000003>; };
- aliases {
gpio0 = &gpioa;gpio1 = &gpiob;gpio2 = &gpioc;gpio3 = &gpiod;gpio4 = &gpioe;gpio5 = &gpiof;gpio6 = &gpiog;gpio7 = &gpioh;gpio8 = &gpioi;gpio9 = &gpioj;gpio10 = &gpiok;serial0 = &usart1;serial1 = &usart2;serial2 = &usart3;serial3 = &uart4;serial4 = &uart5;serial5 = &usart6;serial6 = &uart7;serial7 = &uart8;- };
- intc: interrupt-controller@a0021000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>;
@@ -106,6 +84,38 @@ }; };
- thermal-zones {
cpu_thermal: cpu-thermal {polling-delay-passive = <0>;polling-delay = <0>;thermal-sensors = <&dts>;trips {cpu_alert1: cpu-alert1 {temperature = <85000>;hysteresis = <0>;type = "passive";};cpu-crit {temperature = <120000>;hysteresis = <0>;type = "critical";};};cooling-maps {};};- };
- reboot {
compatible = "syscon-reboot";regmap = <&rcc>;offset = <0x404>;mask = <0x1>;- };
- soc { compatible = "simple-bus"; #address-cells = <1>;
@@ -120,6 +130,12 @@ reg = <0x40000000 0x400>; clocks = <&rcc TIM2_K>; clock-names = "int";
dmas = <&dmamux1 18 0x400 0x1>,<&dmamux1 19 0x400 0x1>,<&dmamux1 20 0x400 0x1>,<&dmamux1 21 0x400 0x1>,<&dmamux1 22 0x400 0x1>;dma-names = "ch1", "ch2", "ch3", "ch4", "up"; status = "disabled"; pwm {@@ -141,6 +157,13 @@ reg = <0x40001000 0x400>; clocks = <&rcc TIM3_K>; clock-names = "int";
dmas = <&dmamux1 23 0x400 0x1>,<&dmamux1 24 0x400 0x1>,<&dmamux1 25 0x400 0x1>,<&dmamux1 26 0x400 0x1>,<&dmamux1 27 0x400 0x1>,<&dmamux1 28 0x400 0x1>;dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled"; pwm {@@ -162,6 +185,11 @@ reg = <0x40002000 0x400>; clocks = <&rcc TIM4_K>; clock-names = "int";
dmas = <&dmamux1 29 0x400 0x1>,<&dmamux1 30 0x400 0x1>,<&dmamux1 31 0x400 0x1>,<&dmamux1 32 0x400 0x1>;dma-names = "ch1", "ch2", "ch3", "ch4"; status = "disabled"; pwm {@@ -183,6 +211,13 @@ reg = <0x40003000 0x400>; clocks = <&rcc TIM5_K>; clock-names = "int";
dmas = <&dmamux1 55 0x400 0x1>,<&dmamux1 56 0x400 0x1>,<&dmamux1 57 0x400 0x1>,<&dmamux1 58 0x400 0x1>,<&dmamux1 59 0x400 0x1>,<&dmamux1 60 0x400 0x1>;dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled"; pwm {@@ -204,6 +239,8 @@ reg = <0x40004000 0x400>; clocks = <&rcc TIM6_K>; clock-names = "int";
dmas = <&dmamux1 69 0x400 0x1>;dma-names = "up"; status = "disabled"; timer@5 {@@ -220,6 +257,8 @@ reg = <0x40005000 0x400>; clocks = <&rcc TIM7_K>; clock-names = "int";
dmas = <&dmamux1 70 0x400 0x1>;dma-names = "up"; status = "disabled"; timer@6 {@@ -347,6 +386,19 @@ status = "disabled"; };
spdifrx: audio-controller@4000d000 {compatible = "st,stm32h7-spdifrx";#sound-dai-cells = <0>;reg = <0x4000d000 0x400>;clocks = <&rcc SPDIF_K>;clock-names = "kclk";interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;dmas = <&dmamux1 93 0x400 0x01>,<&dmamux1 94 0x400 0x01>;dma-names = "rx", "rx-ctrl";status = "disabled";};- usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>;
@@ -487,6 +539,15 @@ reg = <0x44000000 0x400>; clocks = <&rcc TIM1_K>; clock-names = "int";
dmas = <&dmamux1 11 0x400 0x1>,<&dmamux1 12 0x400 0x1>,<&dmamux1 13 0x400 0x1>,<&dmamux1 14 0x400 0x1>,<&dmamux1 15 0x400 0x1>,<&dmamux1 16 0x400 0x1>,<&dmamux1 17 0x400 0x1>;dma-names = "ch1", "ch2", "ch3", "ch4","up", "trig", "com"; status = "disabled"; pwm {@@ -508,6 +569,15 @@ reg = <0x44001000 0x400>; clocks = <&rcc TIM8_K>; clock-names = "int";
dmas = <&dmamux1 47 0x400 0x1>,<&dmamux1 48 0x400 0x1>,<&dmamux1 49 0x400 0x1>,<&dmamux1 50 0x400 0x1>,<&dmamux1 51 0x400 0x1>,<&dmamux1 52 0x400 0x1>,<&dmamux1 53 0x400 0x1>;dma-names = "ch1", "ch2", "ch3", "ch4","up", "trig", "com"; status = "disabled"; pwm {@@ -565,6 +635,11 @@ reg = <0x44006000 0x400>; clocks = <&rcc TIM15_K>; clock-names = "int";
dmas = <&dmamux1 105 0x400 0x1>,<&dmamux1 106 0x400 0x1>,<&dmamux1 107 0x400 0x1>,<&dmamux1 108 0x400 0x1>;dma-names = "ch1", "up", "trig", "com"; status = "disabled"; pwm {@@ -586,6 +661,9 @@ reg = <0x44007000 0x400>; clocks = <&rcc TIM16_K>; clock-names = "int";
dmas = <&dmamux1 109 0x400 0x1>,<&dmamux1 110 0x400 0x1>;dma-names = "ch1", "up"; status = "disabled"; pwm {@@ -606,6 +684,9 @@ reg = <0x44008000 0x400>; clocks = <&rcc TIM17_K>; clock-names = "int";
dmas = <&dmamux1 111 0x400 0x1>,<&dmamux1 112 0x400 0x1>;dma-names = "ch1", "up"; status = "disabled"; pwm {@@ -706,14 +787,14 @@
m_can1: can@4400e000 { compatible = "bosch,m_can";
reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
reg = <0x4400e000 0x400>, <0x44011000 0x1400>; reg-names = "m_can", "message_ram"; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled";@@ -811,13 +892,14 @@ };
sdmmc3: sdmmc@48004000 {
compatible = "st,stm32-sdmmc2";reg = <0x48004000 0x400>, <0x48005000 0x400>;reg-names = "sdmmc", "delay";
compatible = "arm,pl18x", "arm,primecell";arm,primecell-periphid = <0x10153180>;reg = <0x48004000 0x400>;reg-names = "sdmmc"; interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>; clocks = <&rcc SDMMC3_K>;clock-names = "apb_pclk"; resets = <&rcc SDMMC3_R>;
st,idma = <1>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>;@@ -825,7 +907,7 @@ };
usbotg_hs: usb-otg@49000000 {
compatible = "st,stm32mp1-hsotg", "snps,dwc2";
compatible = "snps,dwc2"; reg = <0x49000000 0x10000>; clocks = <&rcc USBO_K>; clock-names = "otg";@@ -846,6 +928,20 @@ reg = <0x4c000000 0x400>; clocks = <&rcc HSEM>; clock-names = "hwspinlock";
};ipcc: mailbox@4c001000 {compatible = "st,stm32mp1-ipcc";#mbox-cells = <1>;reg = <0x4c001000 0x400>;st,proc-id = <0>;interrupts-extended =<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,<&exti 61 1>;interrupt-names = "rx", "tx", "wakeup";clocks = <&rcc IPCC>;wakeup-source; status = "disabled";@@ -856,13 +952,6 @@ #reset-cells = <1>; };
rcc_reboot: rcc-reboot@50000000 {compatible = "syscon-reboot";regmap = <&rcc>;offset = <0x404>;mask = <0x1>;};- pwr: pwr@50001000 { compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd"; reg = <0x50001000 0x400>;
@@ -872,7 +961,7 @@ clocks = <&rcc PLL2_R>; clock-names = "phyclk";
pwr-regulators@c {
pwr-regulators { compatible = "st,stm32mp1,pwr-reg"; st,tzcr = <&rcc 0x0 0x1>;@@ -906,6 +995,7 @@ syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>;
clocks = <&rcc SYSCFG>;};
lptimer2: timer@50021000 {
@@ -994,6 +1084,16 @@ status = "disabled"; };
dts: thermal@50028000 {compatible = "st,stm32-thermal";reg = <0x50028000 0x100>;interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;clocks = <&rcc TMPSENS>;clock-names = "pclk";#thermal-sensor-cells = <0>;status = "disabled";};- cryp1: cryp@54001000 { compatible = "st,stm32mp1-cryp"; reg = <0x54001000 0x400>;
@@ -1059,26 +1159,27 @@ };
sdmmc1: sdmmc@58005000 {
compatible = "st,stm32-sdmmc2";reg = <0x58005000 0x1000>, <0x58006000 0x1000>;reg-names = "sdmmc", "delay";
compatible = "arm,pl18x", "arm,primecell";arm,primecell-periphid = <0x10153180>;reg = <0x58005000 0x1000>;interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>;clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>;
st,idma = <1>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>;status = "disabled";};
sdmmc2: sdmmc@58007000 {
compatible = "st,stm32-sdmmc2";reg = <0x58007000 0x1000>, <0x58008000 0x1000>;reg-names = "sdmmc", "delay";
compatible = "arm,pl18x", "arm,primecell";arm,primecell-periphid = <0x10153180>;reg = <0x58007000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; clocks = <&rcc SDMMC2_K>;clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>;
st,idma = <1>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>;@@ -1102,25 +1203,21 @@ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; reg = <0x5800a000 0x2000>; reg-names = "stmmaceth";
interrupts-extended =<&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;interrupt-names = "macirq","eth_wake_irq","stm32_pwr_wakeup";
interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "macirq"; clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx",
"ethstp";
"ethstp","syscfg-clk"; clocks = <&rcc ETHMAC>, <&rcc ETHTX>, <&rcc ETHRX>,
<&rcc ETHSTP>;
<&rcc ETHSTP>,<&rcc SYSCFG>; st,syscon = <&syscfg 0x4>; snps,mixed-burst; snps,pbl = <2>;
snps,en-tx-lpi-clockgating; snps,axi-config = <&stmmac_axi_config_0>; snps,tso; status = "disabled";@@ -1245,6 +1342,12 @@ reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>;
ts_cal1: calib@5c {reg = <0x5c 0x2>;};ts_cal2: calib@5e {reg = <0x5e 0x2>;};};
i2c6: i2c@5c009000 {
Tested: stm32mp157a-dk1
Tested-by: Pierre-Jean Texier pjtexier@koncepto.io
Regards,
Hi,
From: Patrick DELAUNAY patrick.delaunay@st.com Sent: vendredi 5 juillet 2019 17:20
Synchronize device tree with v5.2-rc4 label and update the associated u-boot dtsi.
Signed-off-by: Patrick Delaunay patrick.delaunay@st.com
Changes in v2:
- missing alignment on ethernet@5800a000
- set ethernet0 phy-mode to "rgmii-id" for dk1 (needed modification not yet upstreamed)
arch/arm/dts/stm32mp15-ddr.dtsi | 2 +- arch/arm/dts/stm32mp157-pinctrl.dtsi | 270 ++++++++++++++++++++++++++++++- arch/arm/dts/stm32mp157-u-boot.dtsi | 60 ++++--- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 4 - arch/arm/dts/stm32mp157a-dk1.dts | 32 ++-- arch/arm/dts/stm32mp157c-dk2.dts | 1 + arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 15 +- arch/arm/dts/stm32mp157c-ed1.dts | 205 +++++------------------ arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 3 - arch/arm/dts/stm32mp157c-ev1.dts | 12 +- arch/arm/dts/stm32mp157c.dtsi | 215 +++++++++++++++++------- 11 files changed, 541 insertions(+), 278 deletions(-)
Applied to u-boot-stm32/master, thanks!
Patrick
participants (3)
-
Patrick DELAUNAY -
Patrick Delaunay
-
Pierre-Jean Texier