[U-Boot] [PATCH] arm: dts: socfpga: stratix10: Fix memory node
Commit 5dfd5607af2114047bd ("ARM: socfpga: Pull DRAM size from DT") get memory size from DT. So, we need to update memory size in memory node. Otherwise, it cause U-boot hang.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/dts/socfpga_stratix10_socdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c6ab0ae..6e8ddcd 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -36,8 +36,8 @@
memory { device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0 0 0x80000000>; /* 2GB */ + u-boot,dm-pre-reloc; }; };
On 07/12/2018 01:13 PM, Ley Foon Tan wrote:
Commit 5dfd5607af2114047bd ("ARM: socfpga: Pull DRAM size from DT") get memory size from DT. So, we need to update memory size in memory node. Otherwise, it cause U-boot hang.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_stratix10_socdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c6ab0ae..6e8ddcd 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -36,8 +36,8 @@
memory { device_type = "memory";
/* We expect the bootloader to fill in the reg */reg = <0 0 0 0>;
reg = <0 0 0 0x80000000>; /* 2GB */u-boot,dm-pre-reloc;};
Applied, thanks
MCR instruction only available in ARM 32-bit. So, compile MCR instruction when ARM 32-bit is enabled.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/board.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index cb6530f..26d84be 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -19,6 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
void s_init(void) { +#ifndef CONFIG_ARM64 /* * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled. * This is optional on CycloneV / ArriaV. @@ -29,6 +30,7 @@ void s_init(void) { "isb\n" "dsb\n" ::"r"(0x0)); +#endif }
/*
On 07/12/2018 01:13 PM, Ley Foon Tan wrote:
MCR instruction only available in ARM 32-bit. So, compile MCR instruction when ARM 32-bit is enabled.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/mach-socfpga/board.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index cb6530f..26d84be 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -19,6 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
void s_init(void) { +#ifndef CONFIG_ARM64 /* * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled. * This is optional on CycloneV / ArriaV. @@ -29,6 +30,7 @@ void s_init(void) { "isb\n" "dsb\n" ::"r"(0x0)); +#endif }
/*
Applied, thanks
participants (2)
-
Ley Foon Tan -
Marek Vasut