[PATCH v1 0/4] Agilex's clock driver updates and fixes
- Add clock enable. - Add clock source for NAND. - Add additional PLL configurations via mebus writes. - U-Boot proper will not re-initialize the clock again if it's already initialized by SPL.
Chee Hong Ang (2): clk: agilex: Handle clock configuration differently in SPL and U-Boot proper clk: agilex: Additional membus writes for HPS PLL
Ley Foon Tan (2): clk: agilex: Add NAND clock support clk: agilex: Add clock enable support
drivers/clk/altera/clk-agilex.c | 113 +++++++++++++++++++++++++++----- 1 file changed, 97 insertions(+), 16 deletions(-)
From: Ley Foon Tan ley.foon.tan@intel.com
Add get nand_clk and nand_x clock support.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- drivers/clk/altera/clk-agilex.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 0042958f4c..2ef9292f93 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -533,7 +533,10 @@ static ulong socfpga_clk_get_rate(struct clk *clk) case AGILEX_EMAC2_CLK: return clk_get_emac_clk_hz(plat, clk->id); case AGILEX_USB_CLK: + case AGILEX_NAND_X_CLK: return clk_get_l4_mp_clk_hz(plat); + case AGILEX_NAND_CLK: + return clk_get_l4_mp_clk_hz(plat) / 4; default: return -ENXIO; }
From: Ley Foon Tan ley.foon.tan@intel.com
Some drivers probing failed if clock enable function is not supported in clock driver. So, add clock enable function to clock driver to solve it.
Return 0 (success) for *.enable function because all clocks are enabled by default in clock driver probe.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- drivers/clk/altera/clk-agilex.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 2ef9292f93..b5cf187364 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -542,6 +542,11 @@ static ulong socfpga_clk_get_rate(struct clk *clk) } }
+static int socfpga_clk_enable(struct clk *clk) +{ + return 0; +} + static int socfpga_clk_probe(struct udevice *dev) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -565,6 +570,7 @@ static int socfpga_clk_ofdata_to_platdata(struct udevice *dev) }
static struct clk_ops socfpga_clk_ops = { + .enable = socfpga_clk_enable, .get_rate = socfpga_clk_get_rate, };
Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- drivers/clk/altera/clk-agilex.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index b5cf187364..c83eb2efb9 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -171,6 +171,16 @@ static void clk_basic_init(struct udevice *dev, if (!cfg) return;
+#ifdef CONFIG_SPL_BUILD + /* Always force clock manager into boot mode before any configuration */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); +#else + /* Skip clock configuration in SSBL if it's not in boot mode */ + if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE)) + return; +#endif + /* Put both PLLs in bypass */ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL); clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
-----Original Message----- From: Ang, Chee Hong chee.hong.ang@intel.com Sent: Friday, July 10, 2020 8:55 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; See, Chin Liang chin.liang.see@intel.com; Tan, Ley Foon ley.foon.tan@intel.com; Ang, Chee Hong chee.hong.ang@intel.com Subject: [PATCH v1 3/4] clk: agilex: Handle clock configuration differently in SPL and U-Boot proper
Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com
drivers/clk/altera/clk-agilex.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index b5cf187364..c83eb2efb9 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -171,6 +171,16 @@ static void clk_basic_init(struct udevice *dev, if (!cfg) return;
+#ifdef CONFIG_SPL_BUILD
- /* Always force clock manager into boot mode before any
configuration */
- clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) |CLKMGR_CTRL_BOOTMODE); #else
"#else" is at the end of line, is this patch display issue or coding issue?
Regards Ley Foon
From: Ang, Chee Hong chee.hong.ang@intel.com Sent: Friday, July 10, 2020 8:55 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; See, Chin Liang chin.liang.see@intel.com; Tan, Ley Foon ley.foon.tan@intel.com; Ang, Chee Hong chee.hong.ang@intel.com Subject: [PATCH v1 3/4] clk: agilex: Handle clock configuration differently in SPL and U-Boot proper
Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot
mode'
before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com
drivers/clk/altera/clk-agilex.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index b5cf187364..c83eb2efb9 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -171,6 +171,16 @@ static void clk_basic_init(struct udevice *dev, if (!cfg) return;
+#ifdef CONFIG_SPL_BUILD
- /* Always force clock manager into boot mode before any
configuration */
- clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) |CLKMGR_CTRL_BOOTMODE); #else
"#else" is at the end of line, is this patch display issue or coding issue?
Only happen in display. Code is fine.
Regards Ley Foon
Add additional membus writes to configure main and peripheral PLL for Agilex's clock manager.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com --- drivers/clk/altera/clk-agilex.c | 94 +++++++++++++++++++++++++++------ 1 file changed, 78 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index c83eb2efb9..5b34731a24 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -47,8 +47,66 @@ static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val) #define MEMBUS_MAINPLL 0 #define MEMBUS_PERPLL 1 #define MEMBUS_TIMEOUT 1000 -#define MEMBUS_ADDR_CLKSLICE 0x27 -#define MEMBUS_CLKSLICE_SYNC_MODE_EN 0x80 + +#define MEMBUS_CLKSLICE_REG 0x27 +#define MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG 0xb3 +#define MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG 0xe6 +#define MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG 0x03 +#define MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG 0x07 + +static const struct { + u32 reg; + u32 val; + u32 mask; +} membus_pll[] = { + { + MEMBUS_CLKSLICE_REG, + /* + * BIT[7:7] + * Enable source synchronous mode + */ + BIT(7), + BIT(7) + }, + { + MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG, + /* + * BIT[0:0] + * Sets synthcalfosc_init_centerfreq=1 to limit overshoot + * frequency during lock + */ + BIT(0), + BIT(0) + }, + { + MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG, + /* + * BIT[0:0] + * Sets synthppm_watchdogtmr_vf0=1 to give the pll more time + * to settle before lock is asserted. + */ + BIT(0), + BIT(0) + }, + { + MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG, + /* + * BIT[6:0] + * Centering duty cycle for clkslice0 output + */ + 0x4a, + GENMASK(6, 0) + }, + { + MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG, + /* + * BIT[6:0] + * Centering duty cycle for clkslice1 output + */ + 0x4a, + GENMASK(6, 0) + }, +};
static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll, int timeout) @@ -126,6 +184,20 @@ static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll, return 0; }
+static void membus_pll_configs(struct socfpga_clk_platdata *plat, u32 pll) +{ + int i; + u32 rdata; + + for (i = 0; i < ARRAY_SIZE(membus_pll); i++) { + membus_read_pll(plat, pll, membus_pll[i].reg, + &rdata, MEMBUS_TIMEOUT); + membus_write_pll(plat, pll, membus_pll[i].reg, + ((rdata & ~membus_pll[i].mask) | membus_pll[i].val), + MEMBUS_TIMEOUT); + } +} + static u32 calc_vocalib_pll(u32 pllm, u32 pllglob) { u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib; @@ -166,7 +238,6 @@ static void clk_basic_init(struct udevice *dev, { struct socfpga_clk_platdata *plat = dev_get_platdata(dev); u32 vcocalib; - u32 rdata;
if (!cfg) return; @@ -226,19 +297,10 @@ static void clk_basic_init(struct udevice *dev, CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB, CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
- /* Membus programming to set mainpll and perripll to - * source synchronous mode - */ - membus_read_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, &rdata, - MEMBUS_TIMEOUT); - membus_write_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, - (rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN), - MEMBUS_TIMEOUT); - membus_read_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, &rdata, - MEMBUS_TIMEOUT); - membus_write_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, - (rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN), - MEMBUS_TIMEOUT); + /* Membus programming for mainpll */ + membus_pll_configs(plat, MEMBUS_MAINPLL); + /* Membus programming for peripll */ + membus_pll_configs(plat, MEMBUS_PERPLL);
cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
-----Original Message----- From: Ang, Chee Hong chee.hong.ang@intel.com Sent: Friday, July 10, 2020 8:55 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; See, Chin Liang chin.liang.see@intel.com; Tan, Ley Foon ley.foon.tan@intel.com; Ang, Chee Hong chee.hong.ang@intel.com Subject: [PATCH v1 4/4] clk: agilex: Additional membus writes for HPS PLL
Add additional membus writes to configure main and peripheral PLL for Agilex's clock manager.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com
Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com
participants (3)
-
Ang, Chee Hong -
Chee Hong Ang
-
Tan, Ley Foon