[U-Boot] [PATCH v2 1/2] board: ge: bx50v3: fix AR8033 reset timing issue
Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet
Signed-off-by: Ken Lin yungching0725@gmail.com --- Changes from v1 - Fix the missing Signed-off-by issue
board/ge/bx50v3/bx50v3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 2fc1144cda..80b4ba1b8b 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
/* Reset AR8033 PHY */ gpio_direction_output(IMX_GPIO_NR(1, 28), 0); - udelay(500); + mdelay(10); gpio_set_value(IMX_GPIO_NR(1, 28), 1); + mdelay(1); }
static iomux_v3_cfg_t const usdhc2_pads[] = {
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin yungching0725@gmail.com --- Changes from v1 - New commit message
board/ge/bx50v3/bx50v3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 80b4ba1b8b..0acf655c0e 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -307,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev) /* set debug port address: SerDes Test and System Mode Control */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); /* enable rgmii tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + /* set the reserved bits to avoid board specific voltage peak issue*/ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
return 0; }
On 21/02/2017 02:56, Ken Lin wrote:
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin yungching0725@gmail.com
Changes from v1
- New commit message
board/ge/bx50v3/bx50v3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 80b4ba1b8b..0acf655c0e 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -307,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev) /* set debug port address: SerDes Test and System Mode Control */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); /* enable rgmii tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
/* set the reserved bits to avoid board specific voltage peak issue*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
return 0;
}
Reviewed-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
Hi Yung-Ching,
https://patchwork.ozlabs.org/patch/730332/ was applied to u-boot-net.git.
Thanks! -Joe
On 21/02/2017 02:56, Ken Lin wrote:
Add the delay (10ms) to ensure the clock is stable and to meet the clock-to-reset(1ms) requirement recommended in the AR8033 datasheet
Signed-off-by: Ken Lin yungching0725@gmail.com
Changes from v1
- Fix the missing Signed-off-by issue
board/ge/bx50v3/bx50v3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 2fc1144cda..80b4ba1b8b 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
/* Reset AR8033 PHY */ gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
- udelay(500);
- mdelay(10); gpio_set_value(IMX_GPIO_NR(1, 28), 1);
- mdelay(1);
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
Reviewed-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
Hi Yung-Ching,
https://patchwork.ozlabs.org/patch/730331/ was applied to u-boot-net.git.
Thanks! -Joe
participants (3)
-
Joe Hershberger -
Ken Lin -
Stefano Babic